CN105609138A - Shifting register, gate driving circuit, display panel and display device - Google Patents
Shifting register, gate driving circuit, display panel and display device Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The invention discloses a shifting register, a gate driving circuit, a display panel and a display device. The shifting register comprises an input module, a reset module, a pull-up module, a pull-down module and an output control module, and further comprises an input protection module. According to the shifting register, the input module, the reset module, the pull-up module, the pull-down module and the output control module can be controlled by respective control terminals to output scanning signals and achieve the gate driving effect; as the input protection module is additionally arranged, a signal input end is connected with a second reference signal end when the signal input end generates static electricity, the static electricity is directly discharged through the second reference signal end, it is prevented that the shifting register is damaged when the static electricity is led in, and the static-electricity protection capacity of the shifting register is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a shift register, a grid driving circuit, a display panel and a display device.
Background
At present, along with the development of liquid crystal display technology, the liquid crystal panel industry is more and more competitive, and reducing the production cost of the liquid crystal display panel becomes the preferred scheme for improving the competitiveness of panel manufacturers, and in order to reduce the production cost of the display panel, generally, technical personnel in related technical field use the edge of the display panel to build a grid drive circuit, the grid drive circuit comprises a plurality of shift registers, each shift register corresponds to a grid line, the plurality of shift registers are arranged in series, a trigger signal transmitted step by step is arranged between two adjacent shift registers, each shift register receives the trigger signal, outputs a grid line scanning signal to the corresponding grid line, and transmits the trigger signal to the next stage unit circuit to realize the grid drive function, the design can omit the independent arrangement of a grid drive chip in the frame area of the display panel, the narrow frame design of the display panel is facilitated, the production cost of related products is reduced, and the market competitiveness of the display products is improved.
However, when external static electricity is introduced into the conventional shift register, the conventional shift register cannot effectively protect the shift register circuit and the display panel from being damaged, and the introduction of the static electricity easily affects the shift register and the display panel to realize normal functions.
Therefore, how to improve the electrostatic protection capability of the shift register is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides a shift register, a grid driving circuit, a display panel and a display device, which are used for improving the electrostatic protection capability of the shift register.
An embodiment of the present invention provides a shift register, including: the device comprises an input module, a reset module, a pull-up module, a pull-down module and an output control module; further comprising: an input protection module; wherein,
the input end of the input module is connected with a first reference signal end, the control end of the input module is connected with a signal input end, the output end of the input module is connected with a first node, and the input module is used for pulling up the potential of the first node under the control of the signal input end;
the reset module is used for pulling down the potential of the first node under the control of the reset signal end or the second node;
a first input end and a first control end of the pull-up module are respectively connected with the first reference signal end, a second input end is connected with the second reference signal end, a second control end is connected with the first node, and an output end is connected with the second node;
the input end of the pull-down module is connected with the second reference signal end, the control end of the pull-down module is connected with the first node, the output end of the pull-down module is connected with the second node, and the pull-down module is used for pulling down the potential of the second node under the control of the first node;
the output control module is connected among the second reference signal terminal, the first node, the second node, a clock signal terminal and a scanning signal output terminal, and is used for controlling the scanning signal output terminal to output a signal of the clock signal terminal under the control of the first node and conducting the second reference signal terminal and the scanning signal output terminal under the control of the second node;
the input end of the input protection module is connected with the signal input end, the control end and the output end of the input protection module are respectively connected with the second reference signal end, and the input protection module is used for conducting the signal input end and the second reference signal end when the signal input end generates static electricity.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input protection module specifically includes: a first switching transistor;
and the grid electrode and the drain electrode of the first switch transistor are respectively connected with the second reference signal end, and the source electrode of the first switch transistor is connected with the signal input end.
In a possible implementation manner, the shift register provided in an embodiment of the present invention further includes: an output protection module;
the input end of the output protection module is connected with the scanning signal output end, the control end and the output end are respectively connected with the second reference signal end, and the output protection module is used for conducting the scanning signal output end and the second reference signal end when the scanning signal output end generates static electricity.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output protection module specifically includes: a second switching transistor;
and the grid electrode and the drain electrode of the second switch transistor are respectively connected with the second reference signal end, and the source electrode of the second switch transistor is connected with the scanning signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the output control module specifically includes: the first output control module and the second output control module; wherein,
the first output control module is connected among the first node, the clock signal end and the scanning signal output end, and is used for controlling the scanning signal output end to output a signal of the clock signal end under the control of the first node;
the second output control module is connected among the second reference signal end, the second node and the scanning signal output end, and is used for conducting the second reference signal end and the scanning signal output end under the control of the second node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the first output control module specifically includes: a third switching transistor and a first capacitor; wherein,
the grid electrode of the third switching transistor is connected with the first node, the source electrode of the third switching transistor is connected with the clock signal end, and the drain electrode of the third switching transistor is connected with the scanning signal output end;
the first capacitor is connected between the first node and the scanning signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output control module specifically includes: a fourth switching transistor;
and the grid electrode of the fourth switching transistor is connected with the second node, the source electrode of the fourth switching transistor is connected with the second reference signal end, and the drain electrode of the fourth switching transistor is connected with the scanning signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the second output control module further includes: a fifth switching transistor;
and the grid electrode of the fifth switching transistor is used for inputting a detection control signal, the source electrode of the fifth switching transistor is connected with the second reference signal end, and the drain electrode of the fifth switching transistor is connected with the scanning signal output end.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the input module specifically includes: a sixth switching transistor;
and the grid electrode of the sixth switching transistor is connected with the signal input end, the source electrode of the sixth switching transistor is connected with the first reference signal end, and the drain electrode of the sixth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the reset module specifically includes: a seventh switching transistor and an eighth switching transistor; wherein,
a gate of the seventh switching transistor is connected to the reset signal terminal, a source thereof is connected to the second reference signal terminal, and a drain thereof is connected to the first node;
and the gate of the eighth switching transistor is connected with the second node, the source of the eighth switching transistor is connected with the second reference signal end, and the drain of the eighth switching transistor is connected with the first node.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the pull-up module specifically includes: a ninth switching transistor, a tenth switching transistor, and an eleventh switching transistor; wherein,
a gate and a source of the ninth switching transistor are respectively connected to the first reference signal terminal, and a drain of the ninth switching transistor is respectively connected to a gate of the tenth switching transistor and a drain of the eleventh switching transistor;
a source of the tenth switching transistor is connected to the first reference signal terminal, and a drain thereof is connected to the second node;
a gate of the eleventh switching transistor is connected to the first node, and a source thereof is connected to the second reference signal terminal.
In a possible implementation manner, in the shift register provided in an embodiment of the present invention, the pull-down module specifically includes: a twelfth switching transistor;
and the grid electrode of the twelfth switching transistor is connected with the first node, the source electrode of the twelfth switching transistor is connected with the second reference signal end, and the drain electrode of the twelfth switching transistor is connected with the second node.
The embodiment of the invention provides a gate driving circuit, which comprises a plurality of cascaded shift registers, except for a first shift register and a last shift register, a scanning signal output end of each shift register inputs a trigger signal to a signal input end of a next adjacent shift register, and inputs a reset signal to a reset signal end of a previous adjacent shift register; a scanning signal output end of the first shift register inputs a trigger signal to a signal input end of the second shift register; and the scanning signal output end of the last shift register inputs a reset signal to the scanning signal output end of the last shift register and the reset signal end of the last shift register.
The embodiment of the invention provides a display panel, which comprises the gate driving circuit provided by the embodiment of the invention.
The embodiment of the invention provides a display device which comprises the display panel provided by the embodiment of the invention.
The embodiment of the invention has the beneficial effects that:
the embodiment of the invention provides a shift register, a grid drive circuit, a display panel and a display device, wherein the shift register comprises: the device comprises an input module, a reset module, a pull-up module, a pull-down module and an output control module; further comprising: an input protection module; the input module is used for pulling up the potential of the first node under the control of the signal input end; the reset module is used for pulling down the potential of the first node under the control of a reset signal end or the second node; the pull-up module is used for pulling up the potential of the second node under the control of the first reference signal end and the first node; the pull-down module is used for pulling down the potential of the second node under the control of the first node; the output control module is used for controlling the scanning signal output end to output a signal of the clock signal end under the control of the first node and conducting the second reference signal end and the scanning signal output end under the control of the second node; the input protection module is used for conducting the signal input end and the second reference signal end when the signal input end generates static electricity. Therefore, the shift register not only can realize the output of scanning signals under the control of respective control ends through the input module, the reset module, the pull-up module, the pull-down module and the output control module to realize the effect of grid drive, but also can conduct the signal input end and the second reference signal end when the signal input end generates static electricity by adding the input protection module, so that the static electricity is directly discharged through the second reference signal end, the shift register is prevented from being damaged by the introduction of the static electricity, and the static electricity protection capability of the shift register is improved.
Drawings
Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a specific structure of a shift register according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating an input/output operation of a shift register according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention.
Detailed Description
The following describes in detail specific embodiments of a shift register, a gate driver circuit, a display panel, and a display device according to embodiments of the present invention with reference to the accompanying drawings.
An embodiment of the present invention provides a shift register, as shown in fig. 1, which may include: the device comprises an input module 01, a reset module 02, an upward pulling module 03, a downward pulling module 04 and an output control module 05; the method can also comprise the following steps: an input protection module 06; wherein,
the Input end of the Input module 01 is connected with a first reference signal end Vref1, the control end is connected with a signal Input end Input, the output end is connected with a first node P1, and the Input module 01 is used for pulling up the potential of the first node P1 under the control of the signal Input end Input;
the input end of the Reset module 02 is connected with a second reference signal end Vref2, the first control end is connected with a Reset signal end Reset, the second control end is connected with a second node P2, the output end is connected with a first node P1, and the Reset module 02 is used for pulling down the potential of the first node P1 under the control of the Reset signal end Reset or the second node P2;
a first input end and a first control end of the pull-up module 03 are respectively connected with a first reference signal end Vref1, a second input end is connected with a second reference signal end Vref2, a second control end is connected with a first node P1, an output end is connected with a second node P2, and the pull-up module 03 is used for pulling up the potential of the second node P2 under the control of the first reference signal end Vref1 and the first node P1;
the input end of the pull-down module 04 is connected with the second reference signal end Vref2, the control end is connected with the first node P1, the output end is connected with the second node P2, and the pull-down module 04 is used for pulling down the potential of the second node P2 under the control of the first node P1;
the output control module 05 is connected between the second reference signal terminal Vref2, the first node P1, the second node P2, the clock signal terminal CLK and the scan signal output terminal Out, and the output control module 05 is configured to control the scan signal output terminal Out to output a signal of the clock signal terminal CLK under the control of the first node P1 and to conduct the second reference signal terminal Vref2 with the scan signal output terminal Out under the control of the second node P2;
the Input end of the Input protection module 06 is connected to the signal Input end, the control end and the output end are respectively connected to the second reference signal end Vref2, and the Input protection module 06 is configured to switch on the signal Input end Input and the second reference signal end Vref2 when the signal Input end Input generates static electricity.
According to the shift register provided by the embodiment of the invention, the output of the scanning signal is realized under the control of the respective control ends through the input module, the reset module, the pull-up module, the pull-down module and the output control module, so that the effect of grid driving is realized, and the signal input end is conducted with the second reference signal end when the signal input end generates static electricity by adding the input protection module, so that the static electricity is directly discharged through the second reference signal end, the shift register is prevented from being damaged by the introduction of the static electricity, and the static electricity protection capability of the shift register is improved.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the input protection module 06 may specifically include: a first switching transistor T1; the gate and the drain of the first switching transistor T1 are respectively connected to a second reference signal terminal Vref2, and the source is connected to the signal Input terminal Input. Specifically, when external static electricity is introduced into the signal Input terminal Input, due to the capacitive coupling principle, a coupling capacitance is generated between the signal Input terminal Input and the gate of the first switch transistor T1, and further, the potential of the gate of the first switch transistor T1 is increased, so that the first switch transistor T1 is in a conducting state, the conducting first switch transistor T1 conducts the signal Input terminal Input and the second reference signal terminal Vref2, and thus, a large static current introduced by the signal Input terminal Input is discharged through the second reference signal terminal Vref2, and static electricity is prevented from being output to the inside of the display panel through the shift register, and normal display of the display panel is affected. In addition, the conduction voltage of the first switching transistor is set to be far larger than the threshold voltage, so that the first switching transistor can be prevented from being conducted when the shift register works normally to influence the normal work of the shift register, and the conduction of the first switching transistor indicates that static electricity is introduced, which is an abnormal condition.
In specific implementation, as shown in fig. 2, the shift register provided in the embodiment of the present invention may further include: an output protection module 07; the input end of the output protection module 07 is connected with the scanning signal output end Out, the control end and the output end are respectively connected with the second reference signal end Vref2, and the output protection module 07 is used for conducting the scanning signal output end Out and the second reference signal end Vref2 when the scanning signal output end Out generates static electricity. Specifically, in the shift register provided in the embodiment of the present invention, an output protection module may be further disposed at the output end, so that when static electricity is generated at the scan signal output end, the static electricity may be released to the second reference signal end through the output protection module, and then the static electricity is released through the second reference signal end, so as to prevent the static electricity from being output to the inside of the display panel, and normal display of the display panel is affected.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the output protection module 07 may specifically include: a second switching transistor T2; the gate and drain of the second switching transistor T2 are connected to a second reference signal terminal Vref2, respectively, and the source is connected to the scan signal output terminal Out. Specifically, when external static electricity is introduced into the scan signal output terminal Out, due to the capacitive coupling principle, a coupling capacitance is generated between the scan signal output terminal Out and the gate of the second switch transistor T2, and further, the potential of the gate of the second switch transistor T2 is increased, so that the second switch transistor T2 is in a conducting state, the conducting second switch transistor T2 conducts the scan signal output terminal Out and the second reference signal terminal Vref2, and thus, a large static electricity current introduced by the scan signal output terminal Out is discharged through the second reference signal terminal Vref2, and static electricity is prevented from being output to the inside of the display panel through the shift register, and normal display of the display panel is affected. In addition, the conduction voltage of the second switching transistor is set to be far larger than the threshold voltage, so that the second switching transistor can be prevented from being conducted when the shift register works normally to influence the normal work of the shift register, and the conduction of the second switching transistor indicates that static electricity is introduced, which is an abnormal condition.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the output control module may specifically include: a first output control module 051 and a second output control module 052; the first output control module 051 is connected among the first node P1, the clock signal terminal CLK and the scanning signal output terminal Out, and the first output control module 051 is used for controlling the scanning signal output terminal Out to output a signal of the clock signal terminal CLK under the control of the first node P1; the second output control module 052 is connected between the second reference signal terminal Vref2, the second node P2 and the scan signal output terminal Out, and the second output control module 052 is used to turn on the second reference signal terminal Vref2 and the scan signal output terminal Out under the control of the second node P2.
Specifically, the first output control module 051 and the second output control module 052 respectively correspond to a signal of the output clock signal terminal CLKB and a signal of the second reference signal terminal Verf2 under the control of the first node P1 and the second node P2, so that the shift register outputs a scanning signal to a corresponding gate line in a corresponding time period, and drives the display panel to realize progressive scanning.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the first output control module 051 may specifically include: a third switching transistor T3 and a first capacitor C1; the gate of the third switching transistor T3 is connected to the first node P1, the source is connected to the clock signal terminal CLK, and the drain is connected to the scan signal output terminal Out; the first capacitor C1 is connected between the first node P1 and the scan signal output terminal Out. Specifically, when the potential of the first node P1 is pulled high, the third switching transistor T3 is in a conducting state, the conducting third switching transistor T3 conducts the clock signal terminal CLK and the scan signal output terminal Out, and the first capacitor C1 performs a bootstrap action on the potential of the first node P1, so as to further maintain the potential of the first node P1.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the second output control module 052 may specifically include: a fourth switching transistor T4; the fourth switching transistor T4 has a gate connected to the second node P2, a source connected to the second reference signal terminal Vref2, and a drain connected to the scan signal output terminal Out. Specifically, when the potential of the second node P2 is pulled high, the fourth switching transistor T4 is in a conducting state, and the conducting fourth switching transistor T4 conducts the second reference signal terminal Vref2 with the scan signal output terminal Out, so that the scan signal output terminal Out outputs the signal of the second reference signal terminal Vref 2.
In a specific implementation, in the shift register provided in the embodiment of the present invention, the second output control module 052 may further include a fifth switching transistor T5, a gate of the fifth switching transistor T5 is used to input the detection control signal GCL, a source of the fifth switching transistor T5 is connected to the second reference signal terminal Vref2, and a drain of the fifth switching transistor T5 is connected to the scan signal output terminal Out, that is, when the shift register normally operates, the gate of the fifth switching transistor T5 inputs the low-level detection control signal GCL, and the fifth switching transistor T5 is in an off state; when the display panel performs the single board test, the gate of the fifth switching transistor T5 inputs the detection control signal GCL with a high potential, at this time, the fifth switching transistor T5 is in a conducting state, and the conducting fifth switching transistor T5 conducts the second reference signal terminal Vref2 with the scan signal output terminal Out, so that the signal of the second reference signal terminal Vref2 can be output to the scan signal output terminal Out, thereby implementing the test that the gate line of the display panel is opened.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the input module 01 may specifically include: a sixth switching transistor T6; the sixth switching transistor T6 has a gate connected to the signal Input terminal Input, a source connected to the first reference signal terminal Vref1, and a drain connected to the first node P1. Specifically, when the signal Input terminal Input inputs a signal, the sixth switching transistor T6 is in a conducting state, and the conducting sixth switching transistor T6 conducts the first reference signal terminal Vref1 to the first node P1, so as to pull up the potential of the first node P1.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the reset module 02 may specifically include: a seventh switching transistor T7 and an eighth switching transistor T8; wherein the seventh switching transistor T7 has a gate connected to the Reset signal terminal Reset, a source connected to the second reference signal terminal Vref2, and a drain connected to the first node P1; the eighth switching transistor T8 has a gate connected to the second node P2, a source connected to the second reference signal terminal Vref2, and a drain connected to the first node P1. Specifically, when the Reset signal terminal Reset inputs a signal, the seventh switching transistor T7 is in a conducting state, the conducting seventh switching transistor T7 conducts the second reference signal terminal Vref2 with the first node P1, and further transmits the signal of the second reference signal terminal Vref2 to the first node P1, and the potential of the first node P1 is pulled down; when the potential of the second node P2 is pulled high, the eighth switch transistor T8 is in a conducting state, the conducting eighth switch transistor T8 conducts the second reference signal terminal Vref2 with the first node P1, and further transmits the signal of the second reference signal terminal Vref2 to the first node P1, and the potential of the first node P1 is pulled low.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the pull-up module 03 may specifically include: a ninth switching transistor T9, a tenth switching transistor T10, and an eleventh switching transistor T11; wherein a gate and a source of the ninth switching transistor T9 are respectively connected to the first reference signal terminal Vref1, and a drain thereof is respectively connected to a gate of the tenth switching transistor T10 and a drain of the eleventh switching transistor T11; the tenth switching transistor T10 has a source connected to the first reference signal terminal Vref1 and a drain connected to the second node P2; the eleventh switching transistor T11 has a gate connected to the first node P1 and a source connected to the second reference signal terminal Vref 2.
Specifically, when the potential of the first node P1 is pulled low, the eleventh switching transistor T11 is in an off state, since the gate and the source of the ninth switching transistor T9 are respectively connected to the first reference signal terminal Vref1, the ninth switching transistor T9 is in a normally-on state, and further outputs the signal of the first reference signal terminal Vref1 to the gate of the tenth switching transistor T10 and the drain of the eleventh switching transistor T11, the eleventh switching transistor T11 is in an off state, and the tenth switching transistor T10 is turned on under the control of the signal of the first reference signal terminal Vref1, and further turns on the first reference signal terminal Vref1 and the second node P2, so as to pull up the potential of the second node P2.
In a specific implementation, as shown in fig. 2, in the shift register provided in the embodiment of the present invention, the pull-down module 04 may specifically include: a twelfth switching transistor T12; the twelfth switching transistor T12 has a gate connected to the first node P1, a source connected to the second reference signal terminal Vref2, and a drain connected to the second node P2. Specifically, when the potential of the first node P1 is pulled high, the twelfth switching transistor T12 is in a conducting state, and the conducting twelfth switching transistor T12 conducts the second reference signal terminal Verf2 and the second node P2, so as to pull down the potential of the second node P2.
It should be noted that the switching transistor mentioned in the above embodiments of the present invention may be a Thin Film Transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), and is not limited herein. In specific implementations, the sources and drains of these transistors may be interchanged without specific distinction. A thin film transistor will be described as an example in describing specific embodiments.
The following describes the normal operation process (when no external static electricity is introduced) of the shift register provided by the embodiment of the present invention with reference to the shift register shown in fig. 2 and the input/output timing diagram shown in fig. 2 and shown in fig. 3. Specifically, three stages t1 to t3 in the input/output timing diagram shown in fig. 3 are selected. In the following description, a high level signal is denoted by 1, and a low level signal is denoted by 0.
At stage t1, Input is equal to 1, CLK is equal to 0, Reset is equal to 0, Vref1 is equal to 1, and Vref2 is equal to 0. Since Input is equal to 1, the sixth switching transistor T6 is turned on, the turned-on sixth switching transistor T6 turns on the first reference signal terminal Vref1 and the first node P1, further pulls the potential of the first node P1 high, and charges the first capacitor C1, since the potential of the first node P1 is pulled high, the third switching transistor T3, the eleventh switching transistor T11 and the twelfth switching transistor T12 are in a turned-on state, the turned-on third switching transistor T3 turns on the clock signal terminal CLK and the scan signal output terminal Out, and since CLK is equal to 0 at this time, the scan signal output terminal Out outputs a low level signal; the turned-on eleventh switching transistor T11 turns on the gate of the tenth switching transistor T10 with the second reference signal terminal Vref2, so that the tenth switching transistor T10 is in an off state; the turned-on twelfth switching transistor T12 turns on the second node P2 and the second reference signal terminal Vref2, and pulls down the potential of the second node P2. the stage t1 is a charging stage.
At stage t2, Input is 0, CLK is 1, Reset is 0, Vref1 is 1, and Vref2 is 0. Due to the bootstrap action of the first capacitor C1, the potential of the first node P1 is further raised, so that the third switching transistor T3 is still in a conducting state, and at this time CLK is equal to 1, so that the scan signal output terminal Out outputs a high level signal, and at the same time, the eleventh switching transistor T11 and the twelfth switching transistor T12 are still in a conducting state, so that the potential of the second node P2 continues to be pulled low. the stage t2 is a scan signal output stage.
At stage t3, Input is 0, CLK is 0, Reset is 1, Vref1 is 1, and Vref2 is 0. Since Reset is equal to 1, the seventh switching transistor T7 is turned on, and the turned-on seventh switching transistor T7 turns on the second reference signal terminal Vref2 and the first node P1, thereby pulling the potential of the first node P1 low; since the potential of the first node P1 is pulled low, the third switching transistor T3 is in an off state. At this time, since the potential of the first node P1 is pulled low, the eleventh switching transistor T11 is in an off state, and the gate and the source of the ninth switching transistor T9 are both connected to the first reference signal terminal Vref1, so the ninth switching transistor T9 is turned on, the turned-on ninth switching transistor T9 turns on the first reference signal terminal Vref1 and the gate of the tenth switching transistor T10, and at this time, the eleventh switching transistor T11 is in an off state, so the tenth switching transistor T10 is turned on under the control of the signal inputted from the first reference signal terminal Vref1, and further turns on the first reference signal terminal Vref1 and the second node P2, so the potential of the second node P2 is pulled high, at this time, since the potential of the second node P2 is pulled high, the fourth switching transistor T4 is turned on under the control of the second node P2, the turned-on fourth switching transistor T4 turns on the low level signal terminal VGL and the scan signal output terminal Out, therefore, the scanning signal output end Out outputs a low level signal, and the noise of the scanning signal output end Out is eliminated; meanwhile, the eighth switching transistor T8 is turned on under the control of the second node P2, and the turned-on eighth switching transistor T8 turns on the second reference signal terminal Vref2 and the first node P1, further pulling down the potential of the first node P1, and eliminating the noise of the first node P1. the t3 phase is a non-scan signal output phase.
In the subsequent time period, the scan signal output end Out will output a low level signal until a signal Input end inputs a high level signal again in a certain time period, and the shift register will repeat the above work process.
The above is a normal working process when the shift register has no external static electricity, when the signal Input terminal Input has external static electricity, due to the capacitive coupling principle, a coupling capacitance may be generated between the signal Input terminal Input and the gate of the first switch transistor T1, thereby causing the potential of the gate of the first switch transistor T1 to rise, so that the first switch transistor T1 is in a conducting state, the conducting first switch transistor T1 conducts the signal Input terminal Input and the second reference signal terminal Vref2, thereby causing a large electrostatic current introduced by the signal Input terminal Input to be discharged through the second reference signal terminal Vref2, preventing static electricity from being output to the inside of the display panel through the shift register, and affecting the normal display of the display panel. Similarly, when external static electricity is introduced into the scan signal output terminal Out, due to the capacitive coupling principle, a coupling capacitance may be generated between the scan signal output terminal Out and the gate of the second switch transistor T2, which further causes the potential of the gate of the second switch transistor T2 to increase, so that the second switch transistor T2 is in a conducting state, the conducting second switch transistor T2 conducts the scan signal output terminal Out and the second reference signal terminal Vref2, thereby discharging a large electrostatic current introduced by the scan signal output terminal Out through the second reference signal terminal Vref2, preventing static electricity from being output to the inside of the display panel through the shift register, and affecting normal display of the display panel.
Based on the same inventive concept, an embodiment of the present invention provides a gate driving circuit, including a plurality of cascaded shift registers provided by the embodiment of the present invention, except for a first shift register and a last shift register, a scan signal output end of each shift register inputs a trigger signal to a signal input end of a next adjacent shift register, and inputs a reset signal to a reset signal end of a previous adjacent shift register; a scanning signal output end of the first shift register inputs a trigger signal to a signal input end of the second shift register; and the scanning signal output end of the last shift register inputs a reset signal to the scanning signal output end of the last shift register and the reset signal end of the last shift register.
For convenience of illustration, fig. 4 shows only eight shift registers, which are the 1 st stage shift register, the 2 nd stage shift register, the 3 rd stage shift register, the 4 th stage shift register, the N-3 rd stage shift register, the N-2 nd stage shift register, the N-1 st stage shift register, and the N th stage shift register. The signal output end Out of the N-1 th stage shift register not only outputs a gate start signal to a gate line connected thereto, but also outputs a reset signal to the N-2 th stage shift register, and simultaneously outputs a trigger signal to the nth stage shift register.
Specifically, each shift register in the gate driving circuit is identical to the shift register provided by the present invention in function and structure, and repeated descriptions are omitted.
Based on the same inventive concept, embodiments of the present invention provide a display panel, including the gate driving circuit provided in embodiments of the present invention. Since the principle of the display panel to solve the problem is similar to that of the gate driving circuit, the implementation of the display panel can refer to the implementation of the gate driving circuit, and repeated descriptions are omitted.
Based on the same inventive concept, an embodiment of the present invention provides a display device, including the display panel provided in the embodiment of the present invention. The display device can be applied to any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Since the principle of the display device to solve the problem is similar to that of the display panel, the display device can be implemented by the display panel, and repeated descriptions are omitted.
The embodiment of the invention provides a shift register, a grid drive circuit, a display panel and a display device, wherein the shift register comprises: the device comprises an input module, a reset module, a pull-up module, a pull-down module and an output control module; further comprising: an input protection module; the input module is used for pulling up the potential of the first node under the control of the signal input end; the reset module is used for pulling down the potential of the first node under the control of a reset signal end or the second node; the pull-up module is used for pulling up the potential of the second node under the control of the first reference signal end and the first node; the pull-down module is used for pulling down the potential of the second node under the control of the first node; the output control module is used for controlling the scanning signal output end to output a signal of the clock signal end under the control of the first node and conducting the second reference signal end and the scanning signal output end under the control of the second node; the input protection module is used for conducting the signal input end and the second reference signal end when the signal input end generates static electricity. Therefore, the shift register not only can realize the output of scanning signals under the control of respective control ends through the input module, the reset module, the pull-up module, the pull-down module and the output control module to realize the effect of grid drive, but also can conduct the signal input end and the second reference signal end when the signal input end generates static electricity by adding the input protection module, so that the static electricity is directly discharged through the second reference signal end, the shift register is prevented from being damaged by the introduction of the static electricity, and the static electricity protection capability of the shift register is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (15)
1. A shift register, comprising: the device comprises an input module, a reset module, a pull-up module, a pull-down module and an output control module; it is characterized by also comprising: an input protection module; wherein,
the input end of the input module is connected with a first reference signal end, the control end of the input module is connected with a signal input end, the output end of the input module is connected with a first node, and the input module is used for pulling up the potential of the first node under the control of the signal input end;
the reset module is used for pulling down the potential of the first node under the control of the reset signal end or the second node;
a first input end and a first control end of the pull-up module are respectively connected with the first reference signal end, a second input end is connected with the second reference signal end, a second control end is connected with the first node, and an output end is connected with the second node;
the input end of the pull-down module is connected with the second reference signal end, the control end of the pull-down module is connected with the first node, the output end of the pull-down module is connected with the second node, and the pull-down module is used for pulling down the potential of the second node under the control of the first node;
the output control module is connected among the second reference signal terminal, the first node, the second node, a clock signal terminal and a scanning signal output terminal, and is used for controlling the scanning signal output terminal to output a signal of the clock signal terminal under the control of the first node and conducting the second reference signal terminal and the scanning signal output terminal under the control of the second node;
the input end of the input protection module is connected with the signal input end, the control end and the output end of the input protection module are respectively connected with the second reference signal end, and the input protection module is used for conducting the signal input end and the second reference signal end when the signal input end generates static electricity.
2. The shift register of claim 1, wherein the input protection module specifically comprises: a first switching transistor;
and the grid electrode and the drain electrode of the first switch transistor are respectively connected with the second reference signal end, and the source electrode of the first switch transistor is connected with the signal input end.
3. The shift register of claim 2, further comprising: an output protection module;
the input end of the output protection module is connected with the scanning signal output end, the control end and the output end are respectively connected with the second reference signal end, and the output protection module is used for conducting the scanning signal output end and the second reference signal end when the scanning signal output end generates static electricity.
4. The shift register according to claim 3, wherein the output protection module specifically comprises: a second switching transistor;
and the grid electrode and the drain electrode of the second switch transistor are respectively connected with the second reference signal end, and the source electrode of the second switch transistor is connected with the scanning signal output end.
5. The shift register according to any one of claims 1 to 4, wherein the output control module specifically comprises: the first output control module and the second output control module; wherein,
the first output control module is connected among the first node, the clock signal end and the scanning signal output end, and is used for controlling the scanning signal output end to output a signal of the clock signal end under the control of the first node;
the second output control module is connected among the second reference signal end, the second node and the scanning signal output end, and is used for conducting the second reference signal end and the scanning signal output end under the control of the second node.
6. The shift register according to claim 5, wherein the first output control module specifically comprises: a third switching transistor and a first capacitor; wherein,
the grid electrode of the third switching transistor is connected with the first node, the source electrode of the third switching transistor is connected with the clock signal end, and the drain electrode of the third switching transistor is connected with the scanning signal output end;
the first capacitor is connected between the first node and the scanning signal output end.
7. The shift register according to claim 5, wherein the second output control module specifically comprises: a fourth switching transistor;
and the grid electrode of the fourth switching transistor is connected with the second node, the source electrode of the fourth switching transistor is connected with the second reference signal end, and the drain electrode of the fourth switching transistor is connected with the scanning signal output end.
8. The shift register of claim 7, wherein the second output control module further comprises: a fifth switching transistor;
and the grid electrode of the fifth switching transistor is used for inputting a detection control signal, the source electrode of the fifth switching transistor is connected with the second reference signal end, and the drain electrode of the fifth switching transistor is connected with the scanning signal output end.
9. The shift register according to any one of claims 1 to 4, wherein the input module specifically comprises: a sixth switching transistor;
and the grid electrode of the sixth switching transistor is connected with the signal input end, the source electrode of the sixth switching transistor is connected with the first reference signal end, and the drain electrode of the sixth switching transistor is connected with the first node.
10. The shift register according to any one of claims 1 to 4, wherein the reset module specifically comprises: a seventh switching transistor and an eighth switching transistor; wherein,
a gate of the seventh switching transistor is connected to the reset signal terminal, a source thereof is connected to the second reference signal terminal, and a drain thereof is connected to the first node;
and the gate of the eighth switching transistor is connected with the second node, the source of the eighth switching transistor is connected with the second reference signal end, and the drain of the eighth switching transistor is connected with the first node.
11. The shift register according to any of claims 1 to 4, wherein the pull-up module, in particular, comprises: a ninth switching transistor, a tenth switching transistor, and an eleventh switching transistor; wherein,
a gate and a source of the ninth switching transistor are respectively connected to the first reference signal terminal, and a drain of the ninth switching transistor is respectively connected to a gate of the tenth switching transistor and a drain of the eleventh switching transistor;
a source of the tenth switching transistor is connected to the first reference signal terminal, and a drain thereof is connected to the second node;
a gate of the eleventh switching transistor is connected to the first node, and a source thereof is connected to the second reference signal terminal.
12. The shift register according to any of claims 1 to 4, wherein the pull-down module comprises: a twelfth switching transistor;
and the grid electrode of the twelfth switching transistor is connected with the first node, the source electrode of the twelfth switching transistor is connected with the second reference signal end, and the drain electrode of the twelfth switching transistor is connected with the second node.
13. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 12, which are cascade-connected, wherein the scan signal output terminal of each shift register except for the first shift register and the last shift register inputs a trigger signal to the signal input terminal of the next shift register adjacent thereto and inputs a reset signal to the reset signal terminal of the previous shift register adjacent thereto; a scanning signal output end of the first shift register inputs a trigger signal to a signal input end of the second shift register; and the scanning signal output end of the last shift register inputs a reset signal to the scanning signal output end of the last shift register and the reset signal end of the last shift register.
14. A display panel comprising the gate driver circuit according to claim 13.
15. A display device characterized by comprising the display panel according to claim 14.
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