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CN103441108A - 一种芯片正装bga封装结构 - Google Patents

一种芯片正装bga封装结构 Download PDF

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CN103441108A
CN103441108A CN2013103808097A CN201310380809A CN103441108A CN 103441108 A CN103441108 A CN 103441108A CN 2013103808097 A CN2013103808097 A CN 2013103808097A CN 201310380809 A CN201310380809 A CN 201310380809A CN 103441108 A CN103441108 A CN 103441108A
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metal
chip
substrate
bump
bga
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李宗怿
顾骁
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及一种芯片正装BGA封装结构,所述结构包括基板(1),所述基板(1)正面正装有芯片(2),所述芯片(2)正面与基板(1)正面之间通过金属线(9)相连接,所述芯片(2)正面设置有多个第二金属凸块(5),所述芯片(2)周围的基板(1)正面设置多个第一金属凸块(4),所述芯片(2)、第一金属凸块(4)和第二金属凸块(5)外围的区域包封有塑封料(6),所述塑封料(6)与第一金属凸块(4)和第二金属凸块(5)顶部齐平,所述塑封料(6)正面电镀有金属层(7),所述基板(1)背面设置有多个金属球(8)。本发明的有益效果是:它在不增加BGA封装厚度的情况下,通过封装工艺形成整体金属散热装置,提高了整体散热效果。

Description

一种芯片正装BGA封装结构
技术领域
本发明涉及一种芯片正装BGA封装结构,属于半导体封装技术领域。
背景技术
现今,半导体封装产业为了满足各种高功耗芯片要求,其大多在BGA表面放置散热片(如图1所示),散热片虽然增加了封装TOP面的散热效果,但也因此增加了BGA产品的整体高度,很难应用于对BGA封装要求较薄的产品如手机、笔记本等手持设备,而AP等芯片由于考虑到多核运算等,其功率要求也越来越高,对散热的要求也越来越高,无散热片的形式难以胜任要求,但增加散热片又难以满足产品应用环境对厚度的要求。而且带散热片的BGA生产方法,通常是在BGA生产加工完后,再用胶料压合散热片,因此散热片并没有与基板或芯片表面的热源直接接触,其散热效果不好。
发明内容
本发明的目的在于克服上述不足,提供一种芯片正装BGA封装结构,它在不增加BGA封装厚度的情况下,通过封装工艺将金属凸块集成于BGA 塑封体上,凸块底面与基板表面或芯片表面相接触,凸块顶面通过电镀工艺使其与塑封料表面电镀金属层构成一个整体的散热装置,由于金属凸块直接与基板表面或芯片表面相连,热量可以直接传导至电镀金属层表面,并通过电镀金属层表面与空气的对流辐射作用,提高了整体散热效果。
本发明的目的是这样实现的:一种芯片正装BGA封装结构,它包括基板,所述基板正面通过导电或不导电粘结物质正装有芯片,所述芯片正面与基板正面之间通过金属线相连接,所述芯片正面设置有多个第二金属凸块,所述芯片周围的基板正面设置多个第一金属凸块,所述芯片、第一金属凸块和第二金属凸块外围的区域包封有塑封料,所述塑封料与第一金属凸块和第二金属凸块顶部齐平,所述塑封料正面电镀有金属层,所述金属层与第一金属凸块和第二金属凸块顶部相连接,所述基板背面设置有多个金属球。
更进一步的,所述塑封料侧面露出多个第一金属凸块。
更进一步的,所述第一金属凸块和第二金属凸块的横截面形状为方形、圆形、六边形或八角形。
与现有技术相比,本发明具有以下有益效果:
本发明一种芯片正装BGA封装结构,它在不增加BGA封装厚度的情况下,通过封装工艺将金属凸块集成于BGA 塑封体上,凸块底面与基板表面或芯片表面相接触,凸块顶面通过电镀工艺使其与塑封料表面电镀金属层构成一个整体散热装置,由于金属凸块直接与基板表面或芯片表面相连,热量可以直接传导至电镀金属层表面,并通过电镀金属层表面与空气的对流辐射作用,提高了整体散热效果;金属凸块可采用一些固定尺寸规格,方便批量生产,并且与基板、芯片表面的连接位置、接触面积可根据内部的结构、内部热点位置以及模流成型的需要进行灵活布置,有利于大批量生产,也克服了采用整块散热金属块因芯片大小不同、封装尺寸大小不同需要特制的现象。
附图说明
图1为以往常见的散热型BGA的结构示意图。
图2~图9为本发明一种芯片正装BGA封装结构制造方法的各工序示意图。
图10为本发明一种芯片正装BGA封装结构的示意图。
图11为本发明一种芯片正装BGA封装结构另一实施例的示意图。
其中:
基板1
芯片2
导电或不导电粘结物质3
第一金属凸块4
第二金属凸块5
塑封料6
金属层7
金属球8
金属线9。
具体实施方式
参见图10,本发明一种芯片正装BGA封装结构,它包括基板1,所述基板1正面通过导电或不导电粘结物质3正装有芯片2,所述芯片2正面与基板1正面之间通过金属线9相连接,所述芯片2正面通过导热胶设置有多个第二金属凸块5,所述芯片2周围的基板1正面通过导热胶设置多个第一金属凸块4,所述第一金属凸块4与第二金属凸块5顶部齐平,所述芯片2、第一金属凸块4和第二金属凸块5外围的区域包封有塑封料6,所述塑封料6与第一金属凸块4和第二金属凸块5顶部齐平,所述塑封料6正面电镀有金属层7,所述金属层7与第一金属凸块4和第二金属凸块5顶部相连接,所述基板1背面设置有多个金属球8。
所述第一金属凸块4和第二金属凸块5的横截面形状可以是方形、圆形、六边形、八角形等,金属凸块可以在SMT工序或装片工序进行安装。
其制造方法如下:
步骤一、取一片基板
参见图2,取一片基板,基板上含有印刷电路,基板厚度的选择可依据产品特性进行选择;
步骤二、装片
参见图3,在基板的正面通过导电或不导电粘结物质正装上芯片;
步骤三、金属线键合
参见图4,在芯片正面与基板正面之间进行键合金属线作业;
步骤四、安装金属凸块
参见图5,在完成装片打线的芯片周围的基板正面通过导热胶安装上多个第一金属块,在芯片正面通过导热胶安装上多个第二金属块;
步骤五、塑封
参加图6,在步骤四完成金属凸块安装的基板正面进行环氧树脂塑封保护,环氧树脂材料可以依据产品特性选择有填料或是没有填料的种类;
步骤六、研磨
参见图7,在步骤五完成环氧树脂塑封后进行表面研磨,使第一金属凸块和第二金属凸块顶部露出塑封料表面;
步骤七、电镀金属层
参见图8,在步骤六完成研磨后的塑封料表面电镀上一层金属层;
步骤八、植球
参见图9,在步骤七完成电镀金属层后的基板背面植入多个金属球。
本发明一种芯片正装BGA封装结构的另一实施如图11所示,它是在电镀金属层工序后通过对边角多余塑封料进行切割,使塑封料侧面露出多个第一金属凸块,从而增加其与空气的接触面积,提升与空气对流辐射的散热效率。

Claims (3)

1.一种芯片正装BGA封装结构,其特征在于:它包括基板(1),所述基板(1)正面通过导电或不导电粘结物质(3)正装有芯片(2),所述芯片(2)正面与基板(1)正面之间通过金属线(9)相连接,所述芯片(2)正面设置有多个第二金属凸块(5),所述芯片(2)周围的基板(1)正面设置多个第一金属凸块(4),所述芯片(2)、第一金属凸块(4)和第二金属凸块(5)外围的区域包封有塑封料(6),所述塑封料(6)与第一金属凸块(4)和第二金属凸块(5)顶部齐平,所述塑封料(6)正面电镀有金属层(7),所述金属层(7)与第一金属凸块(4)和第二金属凸块(5)顶部通过电镀相连接构成一整体散热装置,所述基板(1)背面设置有多个金属球(8)。
2.根据权利要求1所述的一种芯片正装BGA封装结构,其特征在于:所述塑封料(6)侧面露出多个第一金属凸块(4)。
3.根据权利要求1或2所述的一种芯片正装BGA封装结构,其特征在于:所述第一金属凸块(4)和第二金属凸块(5)的横截面形状为方形、圆形、六边形或八角形。
CN2013103808097A 2013-08-28 2013-08-28 一种芯片正装bga封装结构 Pending CN103441108A (zh)

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CN107785329A (zh) * 2016-08-30 2018-03-09 矽品精密工业股份有限公司 电子封装结构及其制法
CN117393517A (zh) * 2023-12-08 2024-01-12 成都智多晶科技有限公司 一种有效增强散热效率的打线类封装结构及基板

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785329A (zh) * 2016-08-30 2018-03-09 矽品精密工业股份有限公司 电子封装结构及其制法
CN117393517A (zh) * 2023-12-08 2024-01-12 成都智多晶科技有限公司 一种有效增强散热效率的打线类封装结构及基板

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Application publication date: 20131211