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CN103414483B - Receiver phase adjustment circuit and method - Google Patents

Receiver phase adjustment circuit and method Download PDF

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CN103414483B
CN103414483B CN201310129866.8A CN201310129866A CN103414483B CN 103414483 B CN103414483 B CN 103414483B CN 201310129866 A CN201310129866 A CN 201310129866A CN 103414483 B CN103414483 B CN 103414483B
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CN103414483A (en
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谭君璋
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WUXI ZETAI MICROELECTRONICS CO Ltd
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WUXI ZETAI MICROELECTRONICS CO Ltd
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Abstract

The invention relates to a receiver phase adjustment circuit and a method. The adjustment circuit generates I-way and Q-way baseband signals and comprises a first voltage-to-current converter, the input voltage being a voltage signal VIin of the I-way and the voltage signal VIin being converted into a first current II through the first voltage-to-current converter; a first current-to-voltage converter, an input current being a first current II which is converted into an output voltage VIout of the I-way through the first current-to-voltage converter; a second voltage-to-current converter, an input voltage being the voltage signal VIin of the I-way and the voltage signal VIin being converted into a second current I(Beta) through the second voltage-to-current converter; a third voltage-to-current converter, an input voltage being the voltage signal VQin of the Q-way and the voltage signal being converted into a third current IQ through the third voltage-to-current converter; and a second current-to-voltage converter, an input current being the second current I(Beta) plus the third current IQ and the input current IQ being converted into an output voltage VQout of the Q-way through the second current-to-voltage converter.

Description

Receiver phase adjusting circuit and method
Technical Field
The present invention relates to a phase adjustment circuit and method for a receiver, and more particularly, to a phase adjustment circuit and method for a zero-if and low-if receiver.
Background
In the currently widely used zero-if and low-if receiver systems, a quadrature down-conversion mixer is generally used, and the output I/Q analog baseband signal may have different degrees of amplitude and phase imbalance, thereby reducing the image rejection ratio (IMRR), deteriorating the signal-to-noise ratio (SNR), and improving the demodulation Bit Error Rate (BER). When the I/Q circuit design is reasonable, the amplitude imbalance is typically small, typically 20 mdB. The phase imbalance is mainly caused by delay mismatch of the I/Q LO signals input to the mixer, and its typical value varies with frequency, and the range varies with process temperature and voltage. At a frequency of 1GHz, which is typically 5 degrees, the image rejection ratio is only 25dB, and to increase above 40dB, the I/Q quadrature phase must be calibrated.
There are three main techniques for adjusting the phase.
The first technique provides a technique of adding a resistor-capacitor array to the transmission path of the I/Q LO so that the delay of the I/Q LO can be adjusted according to the degree of I/Q phase imbalance detected by the baseband signal, and making the I/Q LO signals orthogonal to each other.
The second technique, using analog method, keeps the I path unchanged, updates the Q path signal to (alpha Q + beta I), wherein the alpha and beta coefficients are related to the imbalance degree of I/Q amplitude and phase, and corrects the phase of the Q path by vector addition method. The realization method is to add a voltage addition circuit in an analog baseband signal path.
In a third technique, the analog baseband signal is converted to the digital domain by a high-precision analog-to-digital converter (ADC), and then the second technique is implemented digitally.
The phase adjustment of the I/Q signal using the first technique has the obvious disadvantages that different delay corrections are required at the I/Q LO input at different receiving frequencies, which is not suitable for wideband receivers, and it is difficult to correct the delay with high accuracy for high frequency LOs.
With the second technique, when it is necessary to design a high-precision (e.g., 0.2 degree) phase adjustment, the required α coefficient is close to 1, and the β coefficient becomes very small, so that the difficulty in designing the voltage addition circuit increases. Also, the α and β amplifiers in (α Q + β I) need to be matched, and the area becomes very large in general.
With the third technique, although high-precision adjustment can be achieved relatively easily, it has a drawback in that it cannot be applied to a receiver lacking a high-precision analog-to-digital converter (ADC).
Disclosure of Invention
The present invention is directed to a receiver phase adjustment circuit, which is configured to adjust an I/Q phase of a receiver through a current-to-voltage converter and a voltage-to-current converter, and is applicable to any receiver without increasing a circuit area, and to achieve high-precision adjustment.
Another technical problem to be solved by the present invention is to provide a method for adjusting a phase of a receiver, which is capable of implementing I/Q phase adjustment through a current-to-voltage converter and a voltage-to-current converter, and implementing high-precision adjustment while being applicable to any receiver without increasing circuit area.
The receiver phase adjusting circuit generates I and Q baseband signals, and the voltage signals of the I and Q baseband signals are VIinAnd VQinThe circuit further comprises:
the adjusting circuit generates I and Q baseband signals, and the voltage signals of the I and Q baseband signals are VIinAnd VQinWherein the circuit further comprises:
a first voltage-to-current converter having an input voltage of a voltage signal V of the I-pathIinSaid voltage signal being passed throughThe first voltage-to-current converter converts into a first current II
A first current-to-voltage converter connected in series with the first voltage-to-current converter and inputting a first current IIThe first current IIIs converted into an output voltage V of an I path through the current-to-voltage converterIout
A second voltage-to-current converter having an input voltage of the voltage signal V of the I pathIinThe voltage signal is converted into a second current I through a second voltage-to-current converterβ
A third voltage-to-current converter having an input voltage of Q-path voltage signal VQinThe voltage signal is converted into a third current I through a third voltage-to-current converterQ(ii) a And
a second current-to-voltage converter having its input terminals connected to the second voltage-to-current converter and a third voltage-to-current converter at the same time and having its input current IsIs a second current IβPlus a third current IQThe input current is converted into an output voltage V of a Q circuit through the second current-to-voltage converterQout
The phase adjustment of the receiver is realized by adjusting conversion coefficients of the first voltage-to-current converter and the second voltage-to-current converter.
The phase adjustment method comprises the following steps:
a first current conversion step: input voltage signal V of I pathIinConverted into a first current I by a first voltage-to-current converterI
I path output voltage conversion step: applying the first current IIIs converted into an output voltage V of an I path through the current-to-voltage converterIout
A second current conversion step: will I way voltage signal VIinThrough a second voltage to currentThe converter converts the second current Iβ
A third current conversion step: converting the input voltage signal V of the Q pathQinConverted into a third current I by a third voltage-to-current converterQ
Q path output voltage conversion step: adding the second current and the third current to obtain an input current IsThe input current IsIs converted into an output voltage V of a Q circuit by the second current-to-voltage converterQout(ii) a And
an adjusting step: the phase adjustment of the receiver is realized by adjusting conversion coefficients of the first voltage-to-current converter and the second voltage-to-current converter.
The invention has the beneficial effects that: a plurality of current-voltage converters and current-to-voltage converters are arranged in an I path and a Q path of the receiver to realize I/Q phase adjustment, the circuit area is not increased, meanwhile, the circuit can be applied to any receiver, and high-precision adjustment is realized.
Drawings
Fig. 1 is a block diagram of a phase adjustment circuit of a receiver according to an embodiment of the present invention.
Fig. 2 is a specific circuit diagram of a receiver phase adjustment circuit according to an embodiment of the invention.
Fig. 3 is a circuit diagram of an equivalent resistance of a voltage-to-current conversion circuit as a second voltage-to-current converter in the receiver phase adjustment circuit shown in fig. 2.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict, and the present invention is further described in detail with reference to the drawings and specific embodiments.
Fig. 1 is a block diagram of a phase adjustment circuit of a receiver according to an embodiment of the present invention. The adjusting circuit 10 generates two paths of baseband signals of an I path 10 and a Q path 11, and the voltage signals of the two paths of baseband signals of the I path 10 and the Q path 11 are VIin= cos (ω t) and VQinSin (ω t), ω being the input signal frequency and t being the time, the circuit further comprises a first voltage to current converter 12, a first current to voltage converter 13, a second voltage to current converter 14, a third voltage to current converter 15 and a second current to voltage converter 16. The input voltage of the first voltage-to-current converter 12 is the voltage signal V of the I-path 10IinSaid voltage signal VIinConverted into a first current I by a first voltage-to-current converter 12I1cos(ωt),α1Is a conversion factor with the first voltage-to-current converter 12. The first current-to-voltage converter 13 is connected in series with the first voltage-to-current converter 12, and the input current is a first current IIThe first current IIConverting to an output voltage of way I through the current-to-voltage converter: vIout=c1α1cos(ωt),c1Is a conversion factor with the first current-to-voltage converter. The input voltage of the second voltage-to-current converter 14 is the voltage signal V of the I-path 10IinSaid voltage signal VIinConverted into a second current I by a second voltage-to-current converter 14ββ cos (ω t), β is a conversion coefficient with the second voltage-to-current converter 14. The input voltage of the third voltage-to-current converter 15 is the voltage signal V of the Q path 11Qin= sin (ω t), the voltage signal VQinConverted into a third current I by a third voltage-to-current converter 15Q2sin(ωt),α2Is a conversion factor with the third voltage-to-current converter. The input terminal of the second current-to-voltage converter 16 is connected to both the second voltage-to-current converter 14 and the third voltage-to-current converter 15, the second current-to-voltage converter 16 inputs the current IsIs a second current IβPlus a third current IQI.e. Is2sin (ω t) + β cos (ω t), the input current IsConverted to a Q-path output voltage via the second current-to-voltage converter 16: vQout=c22sin(ωt)+βcos(ωt))=c2α1sin (ω t + θ), where θ = arccos (α)21)=arcsin(β/α1)=arctan(β/α2) The adjusted phase value. If α is2Is fixed, and c2=c1And calculating alpha 1 and beta according to the value of the phase theta which needs to be adjusted, so that the gain imbalance introduced by adjusting the phase can be eliminated while the phase of the Q path is adjusted.
As shown in fig. 2, in the present embodiment, the first voltage-to-current converter 12 is a resistor Rs_IThe second voltage-to-current converter 14 is a resistor RcSaid third voltage-to-current converter 15 being a resistor Rs_QThe first current-to-voltage converter 13 and the second current-to-voltage converter 16 are composed of an operational amplifier with current negative feedback (OPAMP) each including a resistor Rf and a1=1/Rs_I,β=1/Rc,α2=1/Rs_Q,c1=c2=RfAnd then:
<math> <mrow> <msub> <mi>V</mi> <mi>Iout</mi> </msub> <mo>=</mo> <mfrac> <msub> <mi>R</mi> <mi>f</mi> </msub> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> </mfrac> <mi>cos</mi> <mi>&omega;t</mi> <mo>;</mo> </mrow> </math>
<math> <mrow> <msub> <mi>V</mi> <mi>Qout</mi> </msub> <mo>=</mo> <msub> <mi>R</mi> <mi>f</mi> </msub> <mrow> <mo>(</mo> <mfrac> <mrow> <mi>sin</mi> <mi>&omega;t</mi> </mrow> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> </mfrac> <mo>+</mo> <mfrac> <mrow> <mi>cos</mi> <mi>&omega;t</mi> </mrow> <msub> <mi>R</mi> <mi>c</mi> </msub> </mfrac> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <msub> <mi>R</mi> <mi>f</mi> </msub> <mrow> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> <mi>cos</mi> <mi>&theta;</mi> </mrow> </mfrac> <mi>sin</mi> <mrow> <mo>(</mo> <mi>&omega;t</mi> <mo>+</mo> <mi>&theta;</mi> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math> wherein,
<math> <mrow> <mi>&theta;</mi> <mo>=</mo> <mi>arccos</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> </mfrac> <mo>=</mo> <mi>arcsin</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> <msub> <mi>R</mi> <mi>C</mi> </msub> </mfrac> <mo>=</mo> <mi>arctan</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>S</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> <msub> <mi>R</mi> <mi>C</mi> </msub> </mfrac> <mo>.</mo> </mrow> </math>
the implementation method shown in fig. 2 combines the most common programmable amplifier structure, and can implement high-precision phase adjustment through the design of the resistor array and the matching of the resistors. If the phase is to be adjusted by 0.2 degrees, then RcAbout is Rs_Q286.5 times. If Rc is directly replaced by a resistor as shown in fig. 2, the area becomes very large. In order to solve the above problems, the present invention realizes a high precision ratio of equivalent resistance by a voltage-to-current converter instead of Rc resistance.
As shown in FIG. 3, a specific circuit of the voltage-to-current converter is an input voltage V in the voltage-to-current converterinThe positive and negative ends of the voltage source are respectively connected with a transistor M0a and a transistor M0b, the two transistors are respectively provided with a source negative feedback resistor R1 to form a closed loop, and the input voltage Vin is converted into current Iin through a voltage-to-current converter which is provided with a resistor R1 and transistors M0a and M0 b;
<math> <mrow> <msub> <mi>I</mi> <mi>in</mi> </msub> <mo>=</mo> <mi>Vin</mi> <mfrac> <msub> <mi>g</mi> <mi>m</mi> </msub> <mrow> <mn>1</mn> <mo>+</mo> <msub> <mi>g</mi> <mi>m</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> </mrow> </mfrac> <mo>&ap;</mo> <mfrac> <mi>vin</mi> <msub> <mi>R</mi> <mn>1</mn> </msub> </mfrac> <mo>;</mo> <mrow> <mo>(</mo> <msub> <mi>g</mi> <mi>m</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> <mo>></mo> <mo>></mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </math>
the transistors M0a and M0b are connected in parallel with a resistor R2 and a resistor R3 respectively to form a shunt, and I is output from the ends of the two resistors R3outThe two resistorsA common-mode ground Vcm is connected between R2, and if R3/R2= k:
<math> <mrow> <msub> <mi>I</mi> <mi>out</mi> </msub> <mo>=</mo> <msub> <mi>I</mi> <mi>in</mi> </msub> <mfrac> <msub> <mi>R</mi> <mn>2</mn> </msub> <mrow> <msub> <mi>R</mi> <mn>2</mn> </msub> <mo>+</mo> <msub> <mi>R</mi> <mn>3</mn> </msub> </mrow> </mfrac> <mo>&ap;</mo> <mfrac> <mi>vin</mi> <msub> <mi>R</mi> <mn>1</mn> </msub> </mfrac> <mfrac> <msub> <mi>R</mi> <mn>2</mn> </msub> <mrow> <mo>(</mo> <msub> <mi>R</mi> <mn>2</mn> </msub> <mo>+</mo> <msub> <mi>R</mi> <mn>3</mn> </msub> <mo>)</mo> </mrow> </mfrac> <mo>=</mo> <mfrac> <mi>vin</mi> <msub> <mi>R</mi> <mn>1</mn> </msub> </mfrac> <mfrac> <mn>1</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>k</mi> <mo>)</mo> </mrow> </mfrac> <mo>,</mo> </mrow> </math>
said second voltage-to-current converter constitutes an equivalent resistance:
<math> <mrow> <msub> <mi>R</mi> <mi>C</mi> </msub> <mo>=</mo> <mfrac> <mi>vin</mi> <msub> <mi>i</mi> <mi>out</mi> </msub> </mfrac> <mo>&ap;</mo> <msub> <mi>R</mi> <mn>1</mn> </msub> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>k</mi> <mo>)</mo> </mrow> <mo>.</mo> </mrow> </math>
when the equivalent resistance shown in FIG. 3 is applied to the circuit shown in FIG. 2, Vin is equivalent to the input voltage V of the I-pathIin,IoutCorresponding to the second current Iβ
Since the first current-to-voltage converter 13 in fig. 2 is composed of an operational amplifier (OPAMP) with current negative feedback, and the input terminal is a low impedance point, the output current generated by the circuit shown in fig. 3 will flow entirely into the operational amplifier, and will add to the Q-path current IQ. Thereby achieving phase adjustment.
The equivalent resistance for voltage-to-current conversion implemented by the circuit in fig. 3 can be matched with the input resistance Rs of the programmable amplifier in fig. 2, and a very large resistance value can be easily implemented by configuring the proportionality coefficient k values of R3 and R2, so that the area cost is much smaller.
By adopting the analog high-precision I/Q unbalanced phase adjusting circuit in the figures 1 and 2, I/Q unbalanced phase can still be corrected in a receiver without a high-precision analog-to-digital converter (ADC), the adjusting step length can be small, and the precision is high. As long as the designed adjustable range is wide enough, it can be applied to most broadband receivers, and I/Q phase adjustment can be performed at different receiving radio frequency.
The method for adjusting the phase of the receiver, which is applied to the phase adjusting circuit of the receiver shown in fig. 1, comprises the following steps:
step S401, a first current conversion step: input voltage signal V of I pathIinConverted into a first current I by a first voltage-to-current converter 12I;
Step S402, I path output voltage conversion step: i path output voltage conversion step: applying the first current IIIs converted into an output voltage V of the I path by the first current-to-voltage converter 13Iout;
Step S403, a second current conversion step: will I way voltage signal VIinThrough a second voltage-to-current converter14 into a second current Iβ;
Step S404, a third current conversion step: converting the input voltage signal V of the Q pathQinConverted into a third current I by a third voltage-to-current converter 15Q
Step S405, Q-path output voltage conversion step: adding the second current and the third current to obtain an input current IsThe input current IsConverted into an output voltage V of Q-path by the second current-to-voltage converter 16Qout;
Step S406, an adjustment step: adjusting the conversion coefficients with the first voltage-to-current converter 12 and the second voltage-to-current converter 14 achieves phase adjustment of the receiver.
In addition, it can be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a program to instruct related hardware, where the program can be stored in a computer-readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (6)

1. The adjusting circuit generates I and Q baseband signals, and the voltage signals of the I and Q baseband signals are VIinAnd VQinWherein the circuit further comprises:
a first voltage-to-current converter having an input voltage of a voltage signal V of the I-pathIinThe voltage signal is converted into a first current I through a first voltage-to-current converterI
A first current-to-voltage converter connected in series with the first voltage-to-current converterThe input current is the first current IIThe first current IIIs converted into an output voltage V of an I path through the current-to-voltage converterIout
A second voltage-to-current converter having an input voltage of the voltage signal V of the I pathIinThe voltage signal is converted into a second current I through a second voltage-to-current converterβ
A third voltage-to-current converter having an input voltage of Q-path voltage signal VQinThe voltage signal is converted into a third current I through a third voltage-to-current converterQ(ii) a And
a second current-to-voltage converter with its input terminal connected to the output terminals of the second and third voltage-to-current converters, and an input current Is as a second current IβPlus a third current IQThe input current is converted into an output voltage V of a Q circuit through the second current-to-voltage converterQout
The phase adjustment of the receiver is realized by adjusting the conversion coefficients of the first voltage-to-current converter and the second voltage-to-current converter,
if VIin=cos(ωt),VQinSin (ω t), then II=α1cos(ωt),VIout=c1α1cos(ωt),Iβ=βcos(ωt),IQ=α2sin(ωt),Is=α2sin(ωt)+βcos(ωt),VQout=c22sin(ωt)+βcos(ωt))=c2α1sin (ω t + θ), where θ is arccos (α)21)=arcsin(β/α1)=artan(β/α2) For the adjusted phase value, ω is the input signal frequency, t is the time, α1Beta and alpha2Conversion coefficients of the first voltage-to-current converter, the second voltage-to-current converter and the third voltage-to-current converter, respectively, c1、c2The conversion coefficients of the first current-to-voltage converter and the second current-to-voltage converter are respectively.
2. The receiver phase adjustment circuit of claim 1, wherein the conversion coefficients of the first voltage-to-current converter, the second voltage-to-current converter, and the third voltage-to-current converter are α1=1/Rs_I,β=1/Rc,α2=1/Rs_QThe first voltage-to-current converter is a resistor Rs_IThe second voltage-to-current converter is a resistor RcSaid third voltage-to-current converter is a resistor Rs_QThe conversion coefficients of the first current-to-voltage converter and the second current-to-voltage converter are c1 ═ Rf,c2=RfThe first and second current-to-voltage converters comprise operational amplifiers with current negative feedback, each comprising a resistor Rf
And then:
<math> <mrow> <msub> <mi>V</mi> <mi>Iout</mi> </msub> <mo>=</mo> <mfrac> <msub> <mi>R</mi> <mi>f</mi> </msub> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> </mfrac> <mi>cos</mi> <mi>&omega;t</mi> <mo>,</mo> </mrow> </math>
<math> <mrow> <msub> <mi>V</mi> <mi>Qout</mi> </msub> <mo>=</mo> <msub> <mi>R</mi> <mi>f</mi> </msub> <mrow> <mo>(</mo> <mfrac> <mrow> <mi>sin</mi> <mi>&omega;t</mi> </mrow> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> </mfrac> <mo>+</mo> <mfrac> <mrow> <mi>cos</mi> <mi>&omega;t</mi> </mrow> <msub> <mi>R</mi> <mi>c</mi> </msub> </mfrac> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <msub> <mi>R</mi> <mi>f</mi> </msub> <mrow> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> <mi>cos</mi> <mi>&theta;</mi> </mrow> </mfrac> <mi>sin</mi> <mrow> <mo>(</mo> <mi>&omega;t</mi> <mo>+</mo> <mi>&theta;</mi> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>
wherein,
<math> <mrow> <mi>&theta;</mi> <mo>=</mo> <mi>arccos</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> </mfrac> <mo>=</mo> <mi>arcsin</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> <msub> <mi>R</mi> <mi>C</mi> </msub> </mfrac> <mo>=</mo> <mi>arctan</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>S</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> <msub> <mi>R</mi> <mi>C</mi> </msub> </mfrac> <mo>.</mo> </mrow> </math>
3. the receiver phase adjustment circuit of claim 2, wherein the input voltage V in the second voltage-to-current converterIinRespectively connected to a transistor M0a and M0b, each having a source degeneration resistor R1Then the input voltage VIinBy crystalsTubes M0a and M0b and two resistors R1Is then converted into a current IinThe transistors M0a and M0b are each connected in parallel with a resistor R2And a resistor R3Formed by two resistors R3Terminal outputs a second current IβThe two resistors R2Connected to a common ground Vcm if R is assumed3/R2K, then:
<math> <mrow> <msub> <mi>I</mi> <mi>in</mi> </msub> <mo>=</mo> <msub> <mi>V</mi> <mi>Iin</mi> </msub> <mfrac> <msub> <mi>g</mi> <mi>m</mi> </msub> <mrow> <mn>1</mn> <mo>+</mo> <msub> <mi>g</mi> <mi>m</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> </mrow> </mfrac> <mo>&ap;</mo> <mfrac> <msub> <mi>V</mi> <mi>Iin</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> </mfrac> <mo>;</mo> <mrow> <mo>(</mo> <msub> <mi>g</mi> <mi>m</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> <mo>></mo> <mo>></mo> <mn>1</mn> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>
<math> <mrow> <msub> <mi>I</mi> <mi>&beta;</mi> </msub> <mo>=</mo> <msub> <mi>I</mi> <mi>in</mi> </msub> <mfrac> <msub> <mi>R</mi> <mn>2</mn> </msub> <mrow> <msub> <mi>R</mi> <mn>2</mn> </msub> <mo>+</mo> <msub> <mi>R</mi> <mn>3</mn> </msub> </mrow> </mfrac> <mo>&ap;</mo> <mfrac> <msub> <mi>V</mi> <mi>Iin</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> </mfrac> <mfrac> <msub> <mi>R</mi> <mn>2</mn> </msub> <mrow> <mo>(</mo> <msub> <mi>R</mi> <mn>2</mn> </msub> <mo>+</mo> <msub> <mi>R</mi> <mn>3</mn> </msub> <mo>)</mo> </mrow> </mfrac> <mo>=</mo> <mfrac> <msub> <mi>V</mi> <mi>Iin</mi> </msub> <msub> <mi>R</mi> <mn>1</mn> </msub> </mfrac> <mfrac> <mn>1</mn> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>k</mi> <mo>)</mo> </mrow> </mfrac> <mo>,</mo> </mrow> </math> then said second
The voltage-to-current converter forms an equivalent resistance, ioutCorresponding to the second current Iβ
<math> <mrow> <msub> <mi>R</mi> <mi>C</mi> </msub> <mo>=</mo> <mfrac> <msub> <mi>V</mi> <mi>Iin</mi> </msub> <msub> <mi>i</mi> <mi>out</mi> </msub> </mfrac> <mo>&ap;</mo> <msub> <mi>R</mi> <mn>1</mn> </msub> <mrow> <mo>(</mo> <mn>1</mn> <mo>+</mo> <mi>k</mi> <mo>)</mo> </mrow> <mo>.</mo> </mrow> </math>
4. The receiver phase adjustment circuit of claim 1, wherein the first current-to-voltage converter and the second current-to-voltage converter are operational amplifiers with current negative feedback.
5. A phase adjustment method applied to the receiver phase adjustment circuit of claim 1, the method comprising:
a first current conversion step: input voltage signal V of I pathIinConverted into a first current I by a first voltage-to-current converterI
I path output voltage conversion step: applying the first current IIIs converted into an output voltage V of an I path through the current-to-voltage converterIout
A second current conversion step: will I way voltage signal VIinConverted into a second current I by a second voltage-to-current converterβ
A third current conversion step: converting the input voltage signal V of the Q pathQinConverted into a third current I by a third voltage-to-current converterQ
Q path output voltage conversion step: adding the second current and the third current to obtain an input current IsThe input current IsIs converted into an output voltage V of a Q circuit by the second current-to-voltage converterQout(ii) a And
an adjusting step: the phase adjustment of the receiver is realized by adjusting conversion coefficients of the first voltage-to-current converter and the second voltage-to-current converter,
if VIin=cos(ωt),VQinSin (ω t), then II=α1cos(ωt),VIout=c1α1cos(ωt),Iβ=βcos(ωt),IQ=α2sin(ωt),Is=α2sin(ωt)+βcos(ωt),VQout=c22sin(ωt)+βcos(ωt))=c2α1sin (ω t + θ), where θ is arccos (α)21)=arcsin(β/α1)=arctan(β/α2) For the adjusted phase value, ω is the input signal frequency, t is the time, α1Beta and alpha2Conversion coefficients of the first voltage-to-current converter, the second voltage-to-current converter and the third voltage-to-current converter, respectively, c1、c2The conversion coefficients of the first current-to-voltage converter and the second current-to-voltage converter are respectively.
6. The phase adjustment method according to claim 5, characterized in that the first voltage-to-current converter, the second voltage-to-current converterThe conversion coefficients of the two voltage-to-current converter and the third voltage-to-current converter are respectively alpha1=1/Rs_I,β=1/Rc,α2=1/Rs_QThe first voltage-to-current converter is a resistor Rs_IThe second voltage-to-current converter is a resistor RcSaid third voltage-to-current converter is a resistor Rs_QThe conversion coefficients of the first current-to-voltage converter and the second current-to-voltage converter are c1 ═ Rf,c2=RfThe first and second current-to-voltage converters comprise operational amplifiers with current negative feedback, each comprising a resistor RfAnd then:
<math> <mrow> <msub> <mi>V</mi> <mi>Iout</mi> </msub> <mo>=</mo> <mfrac> <msub> <mi>R</mi> <mi>f</mi> </msub> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> </mfrac> <mi>cos</mi> <mi>&omega;t</mi> <mo>,</mo> </mrow> </math>
<math> <mrow> <msub> <mi>V</mi> <mi>Qout</mi> </msub> <mo>=</mo> <msub> <mi>R</mi> <mi>f</mi> </msub> <mrow> <mo>(</mo> <mfrac> <mrow> <mi>sin</mi> <mi>&omega;t</mi> </mrow> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> </mfrac> <mo>+</mo> <mfrac> <mrow> <mi>cos</mi> <mi>&omega;t</mi> </mrow> <msub> <mi>R</mi> <mi>c</mi> </msub> </mfrac> <mo>)</mo> </mrow> <mo>=</mo> <mfrac> <msub> <mi>R</mi> <mi>f</mi> </msub> <mrow> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> <mi>cos</mi> <mi>&theta;</mi> </mrow> </mfrac> <mi>sin</mi> <mrow> <mo>(</mo> <mi>&omega;t</mi> <mo>+</mo> <mi>&theta;</mi> <mo>)</mo> </mrow> <mo>,</mo> </mrow> </math>
wherein,
<math> <mrow> <mi>&theta;</mi> <mo>=</mo> <mi>arccos</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> </mfrac> <mo>=</mo> <mi>arcsin</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>s</mi> <mo>_</mo> <mi>I</mi> </mrow> </msub> <msub> <mi>R</mi> <mi>C</mi> </msub> </mfrac> <mo>=</mo> <mi>arctan</mi> <mfrac> <msub> <mi>R</mi> <mrow> <mi>S</mi> <mo>_</mo> <mi>Q</mi> </mrow> </msub> <msub> <mi>R</mi> <mi>C</mi> </msub> </mfrac> <mo>.</mo> </mrow> </math>
CN201310129866.8A 2013-04-15 2013-04-15 Receiver phase adjustment circuit and method Expired - Fee Related CN103414483B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009268020A (en) * 2008-04-30 2009-11-12 Sony Corp Receiver, receiving method, transmitter, transmitting method, and program
CN101630977A (en) * 2009-08-19 2010-01-20 中兴通讯股份有限公司 Device and method for locking demodulator phase in differential phase shift keying (DPSK) receiver
CN101965721A (en) * 2008-01-04 2011-02-02 高通股份有限公司 I/q imbalance estimation and correction in a communication system

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US8036614B2 (en) * 2008-11-13 2011-10-11 Seiko Epson Corporation Replica DLL for phase resetting

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101965721A (en) * 2008-01-04 2011-02-02 高通股份有限公司 I/q imbalance estimation and correction in a communication system
JP2009268020A (en) * 2008-04-30 2009-11-12 Sony Corp Receiver, receiving method, transmitter, transmitting method, and program
CN101630977A (en) * 2009-08-19 2010-01-20 中兴通讯股份有限公司 Device and method for locking demodulator phase in differential phase shift keying (DPSK) receiver

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