CN103413797B - A kind of power semiconductor modular of three-dimensional structure unit assembling - Google Patents

Abstract

A power semiconductor module assembled with three-dimensional structural units, which is mechanically assembled from a plurality of three-dimensional structural units (6). The emitter of one three-dimensional structure unit is connected in series with the collector of another three-dimensional structure unit through the connection terminal to form a half-bridge unit, and multiple half-bridge units are connected in parallel. The three-dimensional structural unit (6) of each power semiconductor module is composed of a fully controlled power semiconductor chip (10a), an uncontrolled power semiconductor chip (10b), a first substrate (1), and a second substrate (5); The fully controlled power semiconductor chip (10a) and the uncontrolled power semiconductor chip (10b) are located between the first substrate (1) and the second substrate (5) and arranged side by side. The grid (10a2) of the fully controlled power semiconductor chip (10a) is located at the chip corner of the uncontrolled power semiconductor chip (10a). The power semiconductor module is cooled by passing through an insulating cooling liquid.

Description

A power semiconductor module assembled by three-dimensional structural unit

technical field

The invention relates to a three-dimensional packaged power semiconductor module.

Background technique

In recent years, with the development of new energy technology, high-power converters have been widely used. The heat dissipation capability of the inverter becomes a core issue of common concern. The junction temperature of the chip of the power semiconductor module may reach 175°C or even higher during operation. Excessively high chip junction temperature will greatly reduce the number of cycles of the power semiconductor module and further reduce the service life of the module.

In current power semiconductor modules, metal bonding wires are used for the connection between IGBTs and diodes. This method is likely to cause peeling of bonding wires due to thermal fatigue under high temperature conditions, which greatly reduces the reliability of the module. In this traditional packaging structure, bonding wires are used on the front side of the chip for electrical interconnection. Therefore, the chip as a heat source can only dissipate heat by soldering DBC and copper base plate structure on the back side, while the heat dissipation efficiency of the traditional single-sided heat dissipation structure is very limited. .

In addition, due to the uneven cooling channel structure of high heat flux power devices, the uneven temperature distribution on the surface of the heat source chip is more prominent. The current modules are generally packaged by direct soldering to the copper base plate, which causes the failure of a certain unit to cause the entire module to be scrapped, and other intact unit parts cannot be further used, which increases the cost of use.

The power semiconductor modules proposed in US patents US0138452A1 and US7005743B2 adopt the method of double-sided cooling, which improves the cooling effect of the module, but the gate of the power semiconductor chip described in this patent is drawn out by bonding wires, and the entire packaging process is still not Getting rid of the dependence on bonding wires increases the process complexity of packaging.

Contents of the invention

The purpose of the present invention is to overcome the disadvantages of the prior art, and propose a power semiconductor module assembled from three-dimensional structural units without wire bonding process. On the one hand, the invention can reduce the thermal resistance of the junction of the chip and the junction temperature of the chip, and at the same time can reduce the stray parameters of the module, thereby increasing the power density of the power semiconductor module.

The power semiconductor module of the present invention is composed of a plurality of three-dimensional structural units, and each three-dimensional structural unit is installed on the insulating base plate by means of mechanical fixing, and each three-dimensional structural unit can be loaded and unloaded flexibly, so as to avoid the failure of the whole module due to the failure of one of the units , and at the same time, the power semiconductor module can effectively improve the heat dissipation performance of the module.

In the power semiconductor module of the present invention, the emitter of one three-dimensional structural unit is connected in series with the collector of another three-dimensional structural unit as a half-bridge unit, and then a different number of half-bridge units are selected for parallel connection according to different circuit requirements. The number of three-dimensional structural units in a power semiconductor module is determined by the voltage and current level of the chip and the circuit structure to be realized.

Each three-dimensional structural unit is composed of a fully controlled power semiconductor chip, an uncontrolled power semiconductor chip, a first substrate, a second substrate, a first metal pad, a second metal pad and a third metal pad. A metal gasket is welded to the grid of the full-control power semiconductor chip, a second metal gasket is welded to the grid of the full-control power semiconductor chip, and a third metal gasket is welded to the positive electrode of the uncontrolled power semiconductor chip. The first substrate consists of three layers: a first metal layer on top, a first electrically insulating layer in the middle and a second metal layer on the bottom. The first metal layer forms two parts that are not connected to each other through an etching process: the gate side of the first metal layer and the emitter side of the first metal layer. The second metal layer is formed into two parts through an etching process: the gate side of the second metal layer and the emitter side of the second metal layer. The gate side of the first metal layer corresponds vertically to the gate side of the second metal layer, and the emitter side of the first metal layer corresponds vertically to the emitter side of the second metal layer. The first electrical insulating layer in the middle has a metallized through hole, and the gate side of the first metal layer is connected with the gate side of the second metal layer through the metallized through hole. The emitter side of the first metal layer is electrically insulated from the emitter side of the second metal layer.

The second substrate consists of three layers: a third metal layer on top, a second electrically insulating layer in the middle and a fourth metal layer on the bottom. The third metal layer forms two disconnected parts through an etching process: the collector side of the third metal layer and the emitter side of the third metal layer, and the collector side of the third metal layer and the emitter side of the third metal layer are not connected.

The first metal layer, the second metal layer and the third metal layer all have a circuit structure.

The electrical insulating layers of the two substrates are made of high thermal conductivity materials such as aluminum oxide, aluminum nitride or silicon nitride, and the metal layers of the two substrates are made of copper, aluminum or copper alloys. The fully controlled power semiconductor chip and the uncontrolled power semiconductor chip are interconnected through the circuit structure of the metal layer of the two substrates.

The first substrate is located on the top of the entire three-dimensional structural unit, and the second substrate is located at the bottom of the entire three-dimensional structural unit. The fully controlled power semiconductor chip and the uncontrolled power semiconductor chip are soldered side by side on the second metal layer of the first substrate and the second metal layer. Between the second substrate and the third metal layer, the gate of the full-control power semiconductor chip corresponds to the gate side of the second metal layer, the emitter of the full-control power semiconductor chip, the positive electrode of the uncontrolled power semiconductor chip and the second metal layer. The collector sides of the two metal layers correspond to each other.

The fully controlled power semiconductor chip is an IGBT, etc., and the uncontrolled power semiconductor chip is a silicon-based diode or a silicon carbide-based diode.

The gate of the fully-controlled power semiconductor chip is welded to the gate side of the second metal layer of the first substrate through the first metal pad, and the gate side of the second metal layer of the first substrate is metallized through an electrical insulating layer The through hole is connected to the gate side of the first metal layer of the first substrate; the emitter of the fully-controlled power semiconductor chip and the positive electrode of the uncontrolled power semiconductor chip are respectively connected to the first metal pad through the second metal pad and the third metal pad. The second metal layer of the substrate is soldered on the emitter side. The collector of the fully-controlled power semiconductor chip and the negative electrode of the uncontrolled power semiconductor chip are respectively welded to the collector side of the third metal layer; the emitter side of the second metal layer is connected to the emitter of the third metal layer through the fourth metal pad side welded.

The power semiconductor modules are cooled by direct immersion in the insulating cooling circuit liquid.

The invention enhances the heat dissipation capability of the power semiconductor module, improves the power density of the module, and at the same time realizes the flexible loading and unloading of three-dimensional structural units on the insulating base plate of the power semiconductor module, so the invention is especially suitable for high heat flux such as large-scale wind energy and solar power stations. volume occasions. The interconnection between the power semiconductor chips of the present invention is realized through metal layer circuit welding, which gets rid of the dependence on the bonding process and improves the reliability of the power semiconductor module.

Description of drawings

Figure 1a is a cross-sectional view of a three-dimensional structural unit;

Figure 1b is a left view of the three-dimensional structural unit;

Fig. 2 is the top view of the first substrate of three-dimensional structure unit;

Fig. 3 is the bottom view of the first substrate of the three-dimensional structure unit;

4 is a top view of a second substrate of a three-dimensional structure unit;

Fig. 5 is an assembly diagram of a three-dimensional structural unit;

Figure 6a is an internal assembly diagram of an embodiment of the present invention;

Fig. 6b is a housing diagram of an embodiment of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

The power semiconductor module of the present invention is composed of multiple three-dimensional structural units, and each three-dimensional structural unit is fixedly installed on the insulating base plate. The emitter of one three-dimensional structure unit is connected in series with the collector of another three-dimensional structure unit through the connection terminal to form a half-bridge unit, and multiple half-bridge units are connected in parallel.

As shown in Figure 1a, the three-dimensional structure unit 6 includes a fully controlled power semiconductor chip 10a, an uncontrolled power semiconductor chip 10b, a first substrate 1, a second substrate 5, a first metal pad 8a, a second metal pad sheet 9a, and the third metal gasket 9b. The fully controlled power semiconductor chip 10a and the uncontrolled power semiconductor chip 10b are located between the first substrate 1 and the second substrate 5 and arranged side by side.

As shown in Figure 3, the uncontrolled power semiconductor chip 10b in the three-dimensional structure unit 6 is located on the side away from the gate 10a2 of the fully controlled power semiconductor chip 10a, the fully controlled power semiconductor chip 10a, the uncontrolled power semiconductor chip 10b and the The left edge of the second substrate is aligned. The gate 10a2 of the full-control power semiconductor chip 10a is located at the corner of the full-control power semiconductor chip.

Both the first substrate 1 and the second substrate 5 are composed of a three-layer structure: the middle layer is an electrical insulating layer, and the upper and lower layers of the electrical insulating layer are metal layers.

The first substrate 1 is composed of a first metal layer, a first electrically insulating layer 1b and a second metal layer; the first metal layer located above the first electrically insulating layer 1b is divided into the emitter side 1a1 of the first metal layer and the first There are two parts on the gate side 1a2 of the metal layer, the emitter side 1a1 of the first metal layer is not connected to the gate side 1a2 of the first metal layer; the second metal layer located under the first electrical insulating layer 1b is divided into two parts: The emitter side 1c1 of the second metal layer and the gate side 1c2 of the first metal layer are two parts, the emitter side 1c1 of the second metal layer and the gate side 1c2 of the second metal layer are not conductive; the first metal layer The gate side 1a2 is connected to the gate side 1c2 of the second metal layer through a metallized via hole 7c located in the first insulating layer 1b.

The grid 10a2 of the fully-controlled power semiconductor chip 10a corresponds to the gate side 1c2 of the second metal layer, the emitter 10a1 of the fully-controlled power semiconductor chip 10a, the positive electrode 10b1 of the uncontrolled power semiconductor chip and the second metal layer. The collector side 1c1 of the metal layer corresponds. The second substrate 5 is made up of a third metal layer, a second electrical insulating layer 5b and a fourth metal layer 5c; the third metal layer and the fourth metal layer 5c are respectively located above and below the second electrical insulating layer 5b; the third The metal layer is formed by an etching process into two parts, the third metal layer collector side 5a1 and the third metal layer emitter side 5a2, and the third metal layer collector side 5a1 and the third metal layer emitter side 5a2 are not conductive.

As shown in FIG. 2 , FIG. 3 and FIG. 4 , the first metal layer, the second metal layer and the third metal layer all have a circuit structure.

As shown in Figure 1a, the emitter 10a1 of the fully-controlled power semiconductor chip 10a and the negative electrode 10b2 of the uncontrolled power semiconductor chip are welded on the emitter side 5a1 of the third metal layer; the emitter 10a1 of the fully-controlled power semiconductor chip 10a , the grid 10a2 and the positive electrode 10b1 of the uncontrolled power semiconductor chip are welded to the first metal pad 8a, the second metal pad 9a and the third metal pad 9b respectively; the first metal pad 8a is connected to the first substrate 1 The second metal layer gate side 1c2 of the second metal layer is soldered, and is connected to the first metal layer gate side 1a2 of the first substrate 1 through the metallized through hole 7c; the second metal pad 9a and the third metal pad 9b are connected to the first metal layer gate side 1a2 of the first substrate 1 The emitter side 1c1 of the second metal layer of a substrate 1 is soldered.

As shown in FIG. 1b , the emitter side 1c1 of the second metal layer of the first substrate 1 is connected to the emitter side 5a2 of the third metal layer of the second substrate 5 through a fourth metal pad 11 .

As shown in Figure 6a, the emitter e2 of the first three-dimensional structure unit and the collector e3 of the second three-dimensional structure unit are connected in series through the connection terminal 22 to form a half-bridge unit; the emitter f2 of the third three-dimensional structure unit is connected to the fourth three-dimensional structure unit The collector f3 of the unit is connected in series through the connection terminal 22 to form a half-bridge unit, and the emitter g2 of the fifth three-dimensional structure unit and the collector g3 of the sixth three-dimensional structure unit are connected in series through the connection terminal 22 as a half-bridge unit; The collectors e1, f1, g1 of the first, third, and fifth three-dimensional structure units in the unit are fixed on the positive terminal 20a of the insulating base plate 17, and the emitters e4, f4, and f4 of the second, fourth, and sixth three-dimensional structure units g4 is fixed on the negative terminal 20b of the insulating base plate 17, and the three groups of half-bridge units are connected in parallel through the positive terminal 20a and the negative terminal 20b.

The surface of the insulating bottom plate 17 has metallized patterned electrodes: positive terminal 20a, negative terminal 20b, so as to realize the circuit connection of multiple three-dimensional structural units.

The structure of the embodiment of the present invention will be described below with reference to the accompanying drawings. The fully controlled power semiconductor chip in this embodiment is an IGBT, and the uncontrolled power semiconductor chip is a silicon-based diode or a silicon carbide-based diode.

As shown in Figure 1a, the IGBT chip collector 10a3 and the diode chip cathode 10b2 are soldered to the collector side 5a1 of the third metal layer of the second substrate 5 through lead-free or lead-containing soft solder;

As shown in FIG. 1b, the bottom surface of the fourth metal pad 11 is welded to the emitter side 5a2 of the third metal layer.

As shown in Figure 1a, the gate 10a2 of the IGBT chip is welded to the first metal pad 8a; the emitter 10a1 of the IGBT chip and the anode 10b1 of the diode chip are respectively welded to the second metal pad 9a and the third metal pad 9b; The front side of a metal pad 8a is welded to the second metal layer gate side 1c of the first substrate 1, and the top surfaces of the second metal pad 9a, the third metal pad 9b, and the fourth metal pad 11 are welded to the first substrate 1. The emitter side 1c1 of the second metal layer of a substrate; the metal layer material of the first substrate 1 and the second substrate 5 is copper, aluminum or copper alloy, and the electrical insulating layer is aluminum oxide, aluminum nitride or nitride It is made of high thermal conductivity materials such as silicon, and the electrical insulation layer and the metal layer are connected by sintering.

As shown in FIG. 4 , the third metal layer 5a is divided into two parts: the collector side 5a1 of the third metal layer and the emitter side 5a2 of the third metal layer. The collector side 5a1 of the third metal layer is welded to the collector 10a3 of the IGBT chip, and the welding layer is 14a1; the emitter side 5a2 of the third metal layer is connected to the emitter 10a1 of the IGBT chip through the fourth metal pad 11; the fourth metal pad The sheet 11 is interconnected with the emitter side 5a2 of the third metal layer by soldering;

As shown in Figure 1a, the first metal pad 8a, the second metal pad 9a and the third metal pad 9b are respectively welded to the gate 10a2 of the IGBT chip, the emitter 10a1 and the anode 10b1 of the diode chip;

As shown in Figure 5, the first metal pad 8a is welded to the gate 10a2 of the IGBT chip, the first metal pad 8a is welded to the second metal layer gate side 1c2 of the first substrate 1, and the first substrate 1 The second metal layer gate side 1c2 of the bottom 1 is connected to the first metal layer gate side 1a2 through an electrically insulating layer metallized via 7c. The second metal pad 9a, the third metal pad, and the fourth metal pad 11 are welded to the emitter side 1c1 of the second metal layer of the first substrate 1, thus realizing the packaging of the three-dimensional structural unit.

As shown in FIG. 6 a , the power semiconductor module assembled with three-dimensional structural units in this embodiment is a full-bridge structure, and six three-dimensional structural units are fixed on the insulating base plate 17 through connection terminals 22 and nuts 24 . The AC output terminals 19a, 19b, 19c of the three-dimensional structural unit assembled power semiconductor module are drawn through the top outlet 24 of the shell 16 of the three-dimensional structural unit assembled power semiconductor module through the external terminal, and the top outlet 24 is connected with the AC output of the three-dimensional structural unit assembled power semiconductor module Pore sealing treatment between ends 19a, 19b, 19c.

As shown in Figure 6b, the housing 16 and the insulating base plate 17 of the three-dimensional structural unit assembled power semiconductor module are assembled and fixed through the through holes 18 on the insulating base plate 17 through rivets, and the housing 16 and the insulating base plate 17 are carried out through the contact gap in the assembly. Sealed.

In the present invention, the insulating cooling liquid is used for cooling, and the external refrigeration compression equipment can be connected with the inlet 21a and the outlet 21b of the power semiconductor module to perform immersion heat dissipation.

Claims (5)

1. A power semiconductor module assembled by a three-dimensional structural unit, characterized in that, said power semiconductor module is made up of a plurality of three-dimensional structural units, and each three-dimensional structural unit is fixedly mounted on an insulating base plate (17); a three-dimensional structural unit The emitter of the emitter is connected in series with the collector of another three-dimensional structure unit as a half-bridge unit through the connection terminal, and multiple half-bridge units are connected in parallel; Each three-dimensional structural unit consists of a fully controlled power semiconductor chip (10a), an uncontrolled power semiconductor chip (10b), a first substrate (1), a second substrate (5), and a first metal pad (8a) , the second metal pad (9a), and the third metal pad (9b), the first metal pad (8a) is welded to the grid (10a2) of the full-control type power semiconductor chip, the second metal pad ( 9a) welded on the emitter (10a1) of the fully-controlled power semiconductor chip, and the third metal pad (9b) is welded on the positive pole (10b1) of the uncontrolled power semiconductor chip (10b); the fully-controlled power semiconductor The chip (10a) and the uncontrolled power semiconductor chip (10b) are located between the first substrate (1) and the second substrate (5) and arranged side by side; The first substrate (1) is composed of a three-layer structure: the first metal layer on the top, the first electrical insulation layer (1b) in the middle and the second metal layer on the bottom; the first metal layer Layer is formed into two parts by etching process: the first metal layer gate side (1a2) and the first metal layer emitter side (1a1), the first metal layer emitter side (1a1) and the first metal layer gate There is no conduction between the pole sides (1a2); the second metal layer is formed into two parts by an etching process: the second metal layer gate side (1c2) and the second metal layer emitter side (1c1); the first The metal layer gate side (1a2) corresponds to the position of the second metal layer gate side (1c2) up and down, and the first metal layer emitter side (1a1) corresponds to the second metal layer emitter side (1c1) up and down; located in the middle The first electrical insulating layer has a metallized through hole (7c), and the first metal layer gate side (1a2) is connected to the second metal layer gate side (1c2) through the metallized through hole (7c); electrical insulation between the emitter side (1a1) of the first metal layer and the emitter side (1c1) of the second metal layer; The grid (10a2) of the fully-controlled power semiconductor chip (10a) corresponds to the gate side (1c2) of the second metal layer, the emitter (10a1) of the fully-controlled power semiconductor chip (10a), and the uncontrolled power semiconductor The positive electrode (10b1) of the chip corresponds to the collector side (1c1) of the second metal layer; The second substrate (5) is composed of three layers: the third metal layer on the top, the second electrical insulating layer (5b) in the middle and the fourth metal layer (5c) below; the third metal layer is etched The process forms two parts that are not connected: the third metal layer collector side (5a1) and the third metal layer emitter side (5a2), the third metal layer collector side (5a1) and the third metal layer emitter side (5a2 ) is not conductive. 2. The power semiconductor module according to claim 1, wherein the first metal layer, the second metal layer and the third metal layer all have a circuit structure. 3. The power semiconductor module according to claim 1, characterized in that, the emitter (10a1) of the fully-controlled power semiconductor chip (10a) and the negative electrode (10b2) of the uncontrolled power semiconductor chip are welded to the first On the emitter side (5a1) of the three metal layers; the emitter (10a1), grid (10a2) of the fully controlled power semiconductor chip (10a) and the positive pole (10b1) of the uncontrolled power semiconductor chip are respectively connected to the first metal pad sheet (8a), the second metal pad (9a), and the third metal pad (9b); the first metal pad (8a) is welded to the second metal layer gate side (1c2), and through the metallization The through hole (7c) is connected to the gate side (1a2) of the first metal layer; the second metal pad (9a) and the third metal pad (9b) are welded to the emitter side (1c1) of the second metal layer; the second The emitter side (1c1) of the metal layer is connected to the emitter side (5a2) of the third metal layer through a fourth metal pad (11). 4. The power semiconductor module according to claim 1, characterized in that, the uncontrolled power semiconductor chip (10b) is located on a side away from the gate (10a2) of the fully controlled power semiconductor chip (10a); The fully-controlled power semiconductor chip (10a) and the uncontrolled power semiconductor chip (10b) are aligned with the left edge of the second substrate, and the grid (10a2) of the fully-controlled power semiconductor chip (10a) is located at the full Controlled power semiconductor chip corner. 5. The power semiconductor module according to claim 1, characterized in that, the power semiconductor module is cooled by an insulating cooling liquid, and the external refrigeration compression equipment is connected to the inlet (21a) and outlet (21b) of the power semiconductor module Perform immersion cooling.