CN103413788B - The preparation method of non-planar metal nanocrystalline multi-bit memory device - Google Patents

Abstract

The invention discloses a method for preparing a non-planar metal nanocrystal multi-bit memory device, relating to a metal nanocrystal memory. 1) The groove array is etched on the Si substrate by electron beam lithography to form a non-planar stepped structure; 2) After the etched Si substrate is cleaned by a standard method, dry oxidation method is used to form a non-planar stepped structure; Oxidize a layer of dense SiO ₂ thin layer on the non-planar Si substrate as the electron tunneling layer of the memory; 3) sputter Au layer on the non-planar Si substrate covered with SiO ₂ thin layer obtained in step 2) , using the rapid thermal annealing method to agglomerate the Au layer to form Au nanoparticles; 4) Deposit a high-k dielectric layer on the Au nanoparticles obtained in step 3) by electron beam evaporation, and finally evaporate the upper and lower electrodes to obtain a non-planar Metal nanocrystal multi-bit memory devices. Only one-step etching technology is required, the process is simple and repeatable.

Description

Preparation method of non-planar metal nanocrystal multi-bit memory device

technical field

The invention relates to a metal nanocrystal memory, in particular to a preparation method of a non-planar metal nanocrystal multi-bit memory device.

Background technique

Conductor memory is an important branch of microelectronics. It has the function of storing and processing information, and is widely used in various microelectronic devices, such as portable electronic products such as notebook computers, mobile phones, flash memory, and tablet computers. With the popularity of portable intelligent electronic products, the market demand for large-capacity data storage is increasing day by day. In the field of contemporary semiconductor memory, non-volatile memory (NVM) plays an increasingly important role. The so-called non-volatile memory refers to a memory that can still maintain its stored data even when the external power supply is lost. Since D.Kahng and S.M.Sze of Bell Labs (BellLab) proposed a non-volatile semiconductor memory based on a floating gate structure (FG, Floating Gate) in 1967, the concept of a floating gate structure has become the focus of semiconductor non-volatile memory for more than 40 years. The main line of development ([1] D.KahngandS.M.Sze, Afloatinggate and its applicationtomemorydevices, BellSystemsTechnicalJournal.46, 1288, 1967), and is widely used in embedded memories. The memory of this structure has great advantages in cost, storage density, power consumption and thermal stability, and its performance continues to improve rapidly.

As the non-volatile memory enters the 20nm process node, the traditional memory based on the multi-product Si floating gate structure encounters many limitations in structural performance. Storage technology brings serious challenges, because the processing technology of devices is no longer a simple scale reduction, and has reached a limit. Scalability of floating gate memory is hindered mainly in the following two aspects ([2] K.Kim, Technology for sub～50nm DRAM and NAND flashmanufacturing, IEDMTech.Dig.323～326, 2005; .Eng.86,283～286,2009; [4]A.Sikora,F.P.Pesl,W.linger,etal..Technologies and reliability of mode embedded flash cells, Microelectron.Reliab.46,1980～2005,2006): First, the thickness of the tunneling oxide layer The thinning has reached the limit, and the tunnel oxide layer cannot continue to be thinned according to the principle of proportional reduction. Continued thinning will increase the leakage current of the device. When the thickness of the tunnel oxide layer is less than 7nm, the floating gate that stores charges will The charge leakage of the substrate cannot guarantee the data storage requirements for 10 years; second, as the size decreases, the paste coefficient between the floating gate and the control gate continues to decrease, and the distance between the storage cells in the array is getting smaller and smaller , the crosstalk between adjacent multi-pin floating gates is getting more and more serious. The resulting logic errors make it difficult to advance the device size below 20nm. Then someone proposed the concept of multi-tier storage.

A new generation of charge trapping memory technology (CTM: ChargeTrappingMemory) ([5] F.Masuoka, M.Assano, H.Iwahashi, AnewFlashEEPROMcellusingtriplepolysilieontechnology, TechnicalDigestontheIEEEInternationalElectronDevieesMeeting, 464, 1984) based on the trap storage principle of multilayer nanostructures, with a very small amount Electronic operation, small device size, low power consumption, multi-value storage, easy compatibility with CMOS technology, etc., especially CTM memory with multi-value storage state can obtain double storage density in the same area and technology generation Growth, which fundamentally solves the bottleneck of further size reduction faced by current floating gate memory, is considered to be an important direction for the development of next-generation memory technology. However, for multilayer nanocrystal memory, since the upper nanocrystal is far away from the channel, it is relatively difficult for the charge to tunnel directly back to the substrate; at the same time, due to the Coulomb blocking effect and energy level quantization effect, the charge The tunneling is suppressed, resulting in a larger operating voltage.

Contents of the invention

The purpose of the present invention is to introduce a non-planar stepped channel layer structure and a stepwise control oxide layer gate voltage technology to realize a multi-bit metal nanocrystal memory, and to provide a preparation method for a non-planar metal nanocrystal multi-bit memory device.

The present invention comprises the following steps:

1) A groove array is etched on the Si substrate by electron beam lithography to form a non-planar stepped structure;

2) After standard cleaning of the etched Si substrate, a dry oxidation method is used to oxidize a dense SiO ₂ thin layer on the non-planar Si substrate as the electron tunneling layer of the memory;

3) Sputter an Au layer on the non-planar Si substrate covered with a thin layer of SiO ₂ obtained in step 2), and use a rapid thermal annealing method to agglomerate the Au layer to form Au nanoparticles;

4) Deposit a high-k dielectric layer on the Au nanoparticles obtained in step 3) by electron beam evaporation, and finally evaporate the upper electrode and the lower electrode to obtain a non-planar metal nanocrystal multi-bit storage device.

In step 1), the electron beam lithography method can use a gas electron beam lithography machine for electron beam lithography; the Si substrate can be a disc-shaped Si substrate, and the diameter of the disc-shaped Si substrate can be It is 10cm, and the thickness can be 500 μm; The groove array can be a strip groove array or a cross-shaped groove array; the period length of the groove array can be 100-200nm, and the groove height can be 50- 70nm.

In step 2), the dry oxidation method can use a thermal annealing furnace filled with oxygen as a reaction gas, the oxidation temperature is 900°C, and the annealing time is 30s; the thickness of the SiO ₂ thin layer can be 3-5nm.

In step 3), the thickness of the Au layer can be 15nm; the conditions of the rapid thermal annealing method can be: annealing temperature 600°C, annealing time 60s, protective gas is nitrogen; the size of the Au nanoparticles can be 20-30nm.

In step 4), the high-k dielectric layer can be made of HfO ₂ material, the upper electrode can be made of Al electrode, and the lower electrode can be made of Al electrode.

In order to solve the problems existing in the prior art, the present invention proposes the introduction of a non-planar stepped channel layer structure, and a stepwise control oxide layer gate voltage technology to realize a multi-bit metal nanocrystal memory. The invention provides an optimized structure design of a non-planar multi-position metal nanocrystal storage device. Non-planar metal nanoparticles are on different mesas, the upper control oxide layer is distributed in steps, and the thickness of the equivalent oxide layer at the groove and the mesas is different, resulting in different internal electric field distributions. For different operating voltages, charges will be stored in different positions on the mesa, increasing the storage window and forming multi-bit storage.

The present invention realizes the multi-bit metal nanocrystal memory by adopting the non-planar stepped channel layer structure and stepwise control oxide layer gate voltage technology. The present invention only needs one-step etching technology, the process is simple, and the repeatability is good. Demonstration role.

Description of drawings

FIG. 1 is a schematic diagram of a metal nanocrystal multi-bit memory with a stepped oxide layer according to the present invention. In Figure 1, 1 is the 300nm Al electrode, 2 is the stepped control oxide layer, 3 is the nano-Au electron capture layer, 4 is the SiO ₂ tunneling oxide layer, and 5 is the P-type Si substrate; (a) no gate voltage The initial state of V gate or less than the trapping voltage Vt1 of the thin layer; (b) When the gate voltage V gate is greater than the trapping voltage Vt1 of the thin layer but smaller than the trapping voltage Vt2 of the thick layer (Vt2>V gate>Vt1), charges can tunnel into the thin control Metal nanocrystals wrapped in an oxide layer; as the gate voltage increases, the first flat band voltage drifts or the memory window increases until the thin oxide region is saturated; (c) as the gate voltage increases to Vgate>Vt2>Vt1 , the charge tunnels into the metal nanocrystalline layer wrapped by a thick control oxide layer until the second saturation region appears, and the multi-bit storage of charges is realized by controlling the gate voltage.

Fig. 2 is a schematic diagram of the structure of a non-planar metal nanocrystal memory. In Fig. 2, mark 1 is the 300nmAl positive electrode, 2 is the stepped control oxide layer, 3 is the nano-Au electron capture layer, 4 is the _SiO2 tunneling oxide layer, 5 is the P-type Si substrate, and 6 is the 300nmAl electrode under the electrode. electrode.

detailed description

The invention obtains a non-planar stepped channel layer structure by electron beam lithography technology, adopts non-planar metal nano-particles as a charge storage layer, and realizes a multi-bit metal nano-crystal memory by a step-by-step control oxide layer grid voltage technology.

1) Electron beam lithography is used to etch a strip-shaped or cross-shaped groove structure on the Si substrate, the groove period is 100-200nm, and the mesa height is 50-70nm.

2) Standard cleaning is performed on the Si substrate to obtain a clean Si surface.

In step 2), the size of the Si sheet is 4 inches and the thickness is 500 μm; the cleaning process is as follows:

(1) First wash with No. Ⅲ solution (H ₂ SO ₄ : H ₂ O ₂ =4: 1), prepare No. Ⅲ solution in a quartz cup, then put the Si wafer in the quartz boat and boil it on the electric furnace for 10 minutes ( First use the electric furnace to heat for 3 minutes, then turn off the electric furnace and heat with residual temperature for 2 minutes, then turn on the electric furnace to heat for 2 minutes and then turn it off). Take out the Si slice and put it into a quartz cup for flushing with hot deionized water for 10 times, and then rinse with cold deionized water for 5 times.

(2) Take out the Si sheet and soak it in a solution of HF:H ₂ O = 1:20 for 4 minutes. Then take out the Si sheet and rinse with hot deionized water for 15 times, and then rinse with cold deionized water for 15 times.

(3) Then wash with No. 1 solution (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1:1:4), pour deionized water first, heat the water to 85°C, then pour NH ₄ OH and H ₂ O ₂ , put Si slices in after 1 min, heat on the electric furnace for 5 min, then turn off and heat with residual temperature for 5 min. Take out the Si slice and put it into a quartz cup for flushing with hot deionized water for 10 times, and then rinse with cold deionized water for 5 times.

(4) Take out the Si sheet and soak it in a solution of HF:H ₂ O = 1:20 for 2 minutes. Then take out the Si sheet and rinse with hot deionized water for 15 times, and then rinse with cold deionized water for 15 times.

(5) Clean with No. Ⅱ solution (HCl: H ₂ O ₂ : H ₂ O = 1: 1: 4), first pour deionized water and heat to 85°C, then pour HCl and H ₂ O ₂ , after 1 min Put in Si slices, turn on the electric furnace for 3 minutes after 2 minutes, and then turn off the electric furnace and heat for 5 minutes with residual temperature. Take out the Si slice and put it into a quartz cup for flushing, flush with hot deionized water for 15 times, and then flush with cold deionized water for 15 times.

(6) Blow dry with nitrogen for later use.

3) Use dry oxidation technology to oxidize a dense SiO ₂ tunneling layer with a thickness of 3 to 5 nm on a non-planar Si substrate; use a domestic rapid annealing furnace with oxygen as a carrier gas, annealing temperature of 900 ° C, and annealing time of 30s.

4) Sputter a 15nm-thick Au layer on the non-planar Si substrate covered with a thin layer of _SiO2 obtained in step 3), and then use a domestic rapid annealing furnace to form Au nanoparticles by rapid thermal annealing. It is 20-30nm. The annealing temperature is 600°C, and the annealing time is 60s.

5) In step 4), the high-k dielectric layer is made of HfO ₂ material, the thickness of the high-k dielectric layer is 60-80nm, the thickness of the upper electrode Al material is 300nm, and the thickness of the lower electrode Al material is 300nm. The upper electrode and the lower electrode are sputtered by controlled sputtering technology.

Figure 1 shows a schematic diagram of a metal nanocrystal multi-bit memory with a stepped oxide layer. By introducing a non-planar structure, the selective storage of charges is achieved. The upper control oxide layer presents a stepped distribution, and the thickness of the equivalent oxide layer at the groove and the mesa is different, resulting in a difference in the internal electric field distribution. For different operating voltages, charges are stored in metal nanoparticles at different mesas, forming multi-bit storage. Figure 2 shows a schematic diagram of the structure of the non-planar metal nanocrystal memory. By changing the electron beam etching process, non-planar metal nanoparticle memories with different shapes and different mesa heights can be obtained, only one-step etching is required, and the operation process is simple.

Through the above steps, a non-planar multi-bit metal nanocrystal storage device structure is finally obtained. The above descriptions are only preferred examples of the present invention.

Claims (5)

1. the preparation method of non-planar metal nanocrystalline multi-bit memory device, is characterized in that comprising the following steps:

1) etch groove array on a si substrate by electronic beam photetching process, form the structure of non-planar steps shape; Described groove array adopts strip groove array or cross groove array; The Cycle Length of described groove array is 100 ~ 200nm, and the height of groove is 50 ~ 70nm; Described Si substrate selects disc Si substrate, and the diameter of disc Si substrate is 10cm, and thickness is 500 μm;

2) by the Si substrate after etching after standard cleaning, adopt dry oxidation method, nonplanar Si substrate be oxidized the SiO of one deck densification ₂thin layer is as the electron tunneling layer of memory; Described SiO ₂the thickness of thin layer is 3 ~ 5nm;

3) by step 2) surface coverage that obtains has SiO ₂the on-plane surface Si substrate of thin layer sputters Au layer, adopts quick thermal annealing method that Au layer is reunited and form Au nano particle; The thickness of described Au layer is 15nm; The condition of described quick thermal annealing method is: annealing temperature 600 DEG C, annealing time 60s, and protective gas is nitrogen; Described Au nano particle is of a size of 20 ~ 30nm;

4) electron beam evaporation process is adopted in step 3) the Au nano particle that obtains deposits high-k dielectric layer, last evaporation top electrode and bottom electrode, obtain non-planar metal nanocrystalline multi-bit memory device.

2. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, is characterized in that in step 1) in, described electronic beam photetching process adopts gas electron beam mask aligner to carry out electron beam lithography.

3. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, it is characterized in that in step 2) in, described dry oxidation method adopts thermal annealing stove, is filled with oxygen as reacting gas, oxidizing temperature is 900 DEG C, annealing time 30s.

4. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, is characterized in that in step 4) in, described high-k dielectric layer adopts HfO ₂material.

5. the preparation method of non-planar metal nanocrystalline multi-bit memory device as claimed in claim 1, is characterized in that in step 4) in, described top electrode adopts Al electrode, and bottom electrode adopts Al electrode.