CN101692463B - Capacitor structure of mixed nano-crystal memory and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, in particular to a capacitor of a nano-crystal memory and a preparation method thereof. The capacitor uses P-type single crystal silicon as a substrate, on which there are Al ₂ O ₃ tunneling layer, ruthenium and ruthenium oxide mixed nanocrystal, Al ₂ O ₃ barrier layer and palladium electrode layer. Among them, the Al ₂ O ₃ layer is prepared by atomic layer deposition method. The mixed nanocrystals are first deposited by magnetron sputtering to deposit the metal ruthenium layer, and then formed after rapid thermal annealing in a mixed atmosphere composed of nitrogen and trace oxygen. The palladium electrode Layers are formed using the lift-off method. The memory capacitance structure of the present invention has excellent characteristics such as good programming and erasing properties, long charge retention time, etc., and has good application prospects in flash memories.

Description

Capacitance structure and preparation method of a hybrid nanocrystalline memory

technical field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a capacitor structure and a preparation method of a flash memory, in particular to a hybrid nanocrystal storage capacitor structure and a preparation method. the

Background technique

With the continuous development of semiconductor process technology, the integration density of non-volatile flash memory is getting higher and higher, and the size of memory cells is reduced accordingly. After the 65nm technology node, the traditional polysilicon floating gate structure has a series of problems, which greatly It affects the performance of device storage, such as slow erasing and writing speed, high working voltage, etc. [1]. A new generation of non-volatile memory based on a discontinuous charge trapping mechanism (such as nanocrystalline memory, etc.) has recently attracted widespread attention. Compared with traditional polysilicon floating gate memory, it has many advantages, such as better data retention characteristics, more Low operating voltage and faster erasing speed, etc. [2-4]. At present, nanocrystals used in flash memory mainly include semiconductors and metals, and a small amount of metal oxide nanocrystals. Compared with semiconductor nanocrystalline memory, metal nanocrystalline memory has many advantages: it has a higher density of states near the Fermi level, a wider selection range of work function, and a stronger coupling with the channel of the substrate[4] . Research has shown that metals with larger work functions can form deeper potential wells, leading to better charge trapping and better data retention properties. the

Metal ruthenium (Ru) has a large work function (4.7eV), good conductivity, and good thermal stability with high dielectric constant media, and its metal oxides also have good charge storage properties. Therefore, metal ruthenium has a good application prospect in metal nanocrystal memory. Through research, using an effective method to prepare nanocrystals with uniform size, uniform distribution and high density will solve the key problems before the practical application of nanocrystal memory. In addition, the selection of electrodes in the preparation of capacitor storage will also greatly affect the performance of the device. Traditional polysilicon electrode materials have many problems such as high resistivity and low work function, which have great limitations in the application of nanocrystalline storage capacitors. The metal palladium electrode has a large work function (5.22eV), which can form a barrier height that is conducive to charge erasure with the capacitor medium, and palladium has good chemical stability and thermal stability, so it is used in nanocrystalline storage capacitors. It has a great application prospect in the preparation. the

references

[1] J.D.Blauwe, IEEE Trans.Nanotechnology 1, 1(2002). 

[2] J.J.Lee, and D.L.Kwong, IEEE Trans. Electron Devices 52, 507(2005). 

[3]H.L.Hanafi, S.Tiwari, and I.Khan, IEEE Trans.Electron Devices 43, 1553(1996). 

[4] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron Devices 49, 1606 (2002).

[5] B.Govoreanu, P.Blomme, M.Rosmeulen, and J.V.Houdt, IEEE Electron Device Lett.24, 99(2003).

Contents of the invention

The object of the present invention is to provide a novel ruthenium and ruthenium oxide hybrid nanocrystal memory capacitor structure with high storage charge density, good data retention characteristics, low operating voltage and fast erasing and writing speed. the

Another object of the present invention is to provide a preparation method of the above product. the

The capacitive structure of the novel nanocrystalline memory that the present invention proposes uses the P-type monocrystalline silicon chip as the substrate layer, and the Al ₂ O ₃ nanometer film grown by the method of atomic layer deposition is used as the charge tunneling layer, and the thickness is 5-10 nanometers . After the tunneling layer is formed, a layer of ruthenium film with a thickness of 1-4 nanometers is then magnetron sputtered, and in a mixed atmosphere composed of nitrogen and trace oxygen, rapid thermal annealing is performed at 600-900°C to form ruthenium, Ruthenium oxide mixed nanocrystals. Subsequently, an Al ₂ O ₃ film with a thickness of 15-40 nanometers is deposited as a barrier layer, and undergoes rapid heat treatment at high temperature and in a nitrogen atmosphere. After a standard photolithography process, a lift-off method is used to form a gate electrode, and the gate electrode is a palladium metal layer with a thickness of 50-200 nanometers.

The schematic cross-sectional structure diagram of the novel hybrid nanocrystalline storage capacitor of the present invention is shown in FIG. 1 . the

In the present invention, the thickness of the Al ₂ O ₃ film is realized by controlling the reaction cycles of atomic layer deposition, and the thickness and uniformity of the ruthenium film are realized by controlling the power, time and substrate speed of magnetron sputtering. The density and size of ruthenium and ruthenium oxide mixed nanocrystals are determined by the initial thickness of ruthenium and the temperature and time of post-annealing. Electrode palladium is formed under high vacuum by electron beam evaporation, which has good contact with the surface of the medium and high electrode quality.

On the basis of the above preparation method, in order to facilitate the measurement of device performance, clean the P-type single crystal silicon wafer with (100) crystal orientation, remove the natural oxide layer on the back of the substrate with hydrofluoric acid, and then deposit a layer of metal aluminum layer , to form a good ohmic contact. the

The preparation method of the ruthenium nanocrystal memory capacitor proposed by the present invention is as follows:

1. Using a P-type single crystal silicon wafer as the substrate, the silicon wafer is firstly cleaned in a standard manner, and the residual natural oxide layer is removed by dilute hydrofluoric acid. the

2. Formation of the tunneling layer: First, in the atomic layer deposition system, the surface of the silicon wafer is modified with trimethylaluminum gas for 30-60 minutes at a temperature of 250-350°C, in order to prevent subsequent Al ₂ The formation of the interface layer during the growth of the O ₃ film; then, the Al ₂ O ₃ film is grown by atomic layer deposition, and the substrate temperature is controlled within the range of 250-350°C during deposition. Wherein, the reaction source of Al ₂ O ₃ is selected from trimethylaluminum and water vapor, and the thickness of the Al ₂ O ₃ tunneling layer is controlled within a range of 5-10 nanometers.

3. Formation of mixed nanocrystals: Deposit ultra-thin metal ruthenium layer by magnetron sputtering deposition method, the thickness of ruthenium layer is 1-4 nanometers, and then perform rapid thermal annealing in a mixed atmosphere composed of nitrogen and trace oxygen, The mixed nanocrystals of ruthenium and ruthenium oxide can be formed. The annealing temperature is 600-900° C., and the time is 10-30 seconds. the

4. Form a high-quality barrier layer: A layer of Al ₂ O ₃ film is grown on the surface of mixed nanocrystals/Al ₂ O ₃ by atomic layer deposition, and the substrate temperature is controlled within the range of 250-350°C during deposition . Wherein, the reaction source of Al ₂ O ₃ is selected from trimethylaluminum and water vapor, and the thickness of the Al ₂ O ₃ barrier layer is 15-40 nanometers. Then, the above sample is subjected to rapid heat treatment in nitrogen gas, the heat treatment temperature is 600-800°C, and the time is 10-30 seconds, the purpose is to further obtain a dense and defect-free Al ₂ O ₃ barrier layer and suppress the leakage of charges.

5. Forming the gate electrode: the gate electrode is formed by the lift-off method, that is, the pattern is first formed by photolithography, and then the palladium metal film is grown by electron beam evaporation equipment with a film thickness of 50-200 nanometers. Finally, the remaining light is cleaned with acetone Resist, so as to complete the manufacturing process of the hybrid nanocrystalline memory capacitor. the

6. In order to facilitate the measurement of device performance, first use hydrofluoric acid to remove the natural oxide layer on the back of the substrate, and then deposit a layer of metal aluminum layer as the next electrode to form a good ohmic contact. the

The present invention has the following advantages:

1. The ultra-thin metal ruthenium film is formed by magnetron sputtering deposition. By adjusting the deposition power, time, substrate temperature, etc., the thickness and deposition rate of the film can be controlled more accurately under high vacuum to form an ultra-thin film. Thin and uniform metal film, which makes it easier to form nanocrystalline particles with small diameter, uniform distribution and high density after annealing. the

2. The mixed nanocrystals of ruthenium and ruthenium oxide are used as the charge storage center. Because of their high work function (4.7-5.2eV), they can provide a larger potential well depth, which is beneficial to improve the charge storage capacity. The coexistence of ruthenium and ruthenium oxide introduces a new interface inside the nanoparticle, thereby creating a new interface trap at the ruthenium/ruthenium oxide interface, which is beneficial to increase the charge storage density. The formation temperature of the mixed nanocrystal in the present invention is compatible with the manufacturing process temperature of the memory, and does not exceed the activation annealing temperature after source and drain ion implantation in device manufacturing. the

3. The Al ₂ O ₃ dielectric film is prepared by atomic layer deposition, which can not only precisely control the thickness of the film, but also grow a film with better quality at a temperature lower than 350°C, which is beneficial to suppress the substrate silicon and the dielectric film. chemical reaction between. In addition, the use of atomic layer deposition film formation technology can effectively fill the gaps with nanoscale spacing, so that the nanocrystals are completely isolated.

4. Using metal palladium as the gate electrode can not only form a pad barrier with the aluminum oxide medium of the barrier layer, but also the palladium is not easy to be oxidized, and has good chemical and thermal stability. The palladium thin film is grown under high vacuum by electron beam evaporation equipment, so that it can form a good contact interface with the aluminum oxide medium, thereby improving the performance of the capacitor memory. the

Description of drawings

Fig. 1 is a schematic diagram of a cross-sectional structure of a storage capacitor containing ruthenium and ruthenium oxide mixed nanocrystals. the

Figure 2 (a) Capacitance-voltage (C-V) curves obtained under different scanning voltages at 1 MHz for memory capacitors containing ruthenium and ruthenium oxide mixed nanocrystals; (b) curves of aluminum oxide dielectric capacitors without nanocrystals under different scanning voltages Capacitance-voltage curve. the

Fig. 3 is the capacitance-voltage hysteresis window obtained under different scanning voltage ranges for memory capacitors containing ruthenium and ruthenium oxide nanocrystals. the

Figure 4 contains the programming and erasing characteristics of ruthenium and ruthenium oxide hybrid nanocrystal storage capacitors: (a) programming at +8V; (b) erasing at -8V. the

Figure 5 holds characteristics of capacitors containing ruthenium and ruthenium oxide nanocrystals programmed at 8V and erased at -8V. the

Numbers in the figure: 1 is a substrate, 2 is a charge tunneling layer, 3 is a mixed nanocrystal of ruthenium and ruthenium oxide, 4 is a barrier layer, and 5 is a dummy gate electrode. the

Detailed ways

Example 1

The following is an example of preparing ruthenium and ruthenium oxide mixed nanocrystal storage capacitors by adopting the storage capacitor structure and preparation method provided by the present invention. the

A P-type single crystal silicon chip with (100) crystal orientation is used as a substrate, and the resistivity of the silicon chip is 8-12 ohm·cm. After the silicon wafer has undergone standard cleaning, it is placed in an atomic layer deposition system, and then the surface of the silicon wafer is modified with trimethylaluminum gas for 60 minutes at a temperature of 300°C. Next, Al ₂ O ₃ nanometer film was grown by atomic layer deposition as a tunneling layer, and the thickness of Al ₂ O ₃ was 9 nanometers. Next, magnetron sputtering a ruthenium metal film with a thickness of 2 nanometers on the tunneling layer, and then rapid thermal annealing at 800° C. for 30 seconds in a mixed atmosphere of nitrogen and trace oxygen to form mixed nanocrystals of ruthenium and ruthenium oxide. Next, an 18nm-thick Al ₂ O ₃ film was atomically layer deposited on the mixed nanocrystal/Al ₂ O ₃ as a barrier layer, and annealed at 800°C in nitrogen for 30 seconds. Finally, electrode patterns were formed on the Al ₂ O ₃ barrier layer by standard photolithography, and a palladium film with a thickness of 50 nm was grown by electron beam evaporation under high vacuum, and the remaining photoresist was removed with acetone to form a gate electrode. In order to facilitate the measurement of device performance, hydrofluoric acid was used to remove the natural oxide layer on the back of the substrate, and then a metal aluminum layer was deposited as the bottom electrode to form a good ohmic contact. For the convenience of comparison, in this example, a single Al ₂ O ₃ dielectric capacitor without a nanocrystalline layer was fabricated, wherein the thickness of Al ₂ O ₃ was 27 nanometers, and the electrode preparation was the same as above. In this embodiment 1, the reaction sources for depositing Al ₂ O ₃ are trimethylaluminum and water vapor, and the substrate temperature is 300°C.

Fig. 2(a) is the capacitance-voltage (CV) curve obtained when the storage capacitor in this example is in different voltage scanning ranges and scanning directions at 1 MHz. The results show that as the scanning voltage range increases, the CV hysteresis window also increases, reflecting the effective storage characteristics. The obtained CV hysteresis window is 7.8V within the scanning voltage range of +8V～-8V. On the contrary, if a single Al ₂ O ₃ dielectric layer is used, that is, without nanocrystals, basically no CV hysteresis window can be observed, as shown in Figure 2(b). This shows that the hybrid nanocrystals of ruthenium and ruthenium oxide can store charges very efficiently. As the maximum scanning voltage further increases to +/-11V, the CV hysteresis window of the hybrid nanocrystalline storage capacitor increases to 11.2V, as shown in FIG. 3 . This indicates that the hybrid nanocrystals have high charge-trapping centers and are capable of storing large amounts of charge.

Figure 4 is the C-V curve of the storage capacitor made in this example in the programming and erasing states. It can be seen that the obtained flat band voltage offset is +2V under the conditions of 8V and 100 microseconds; Erase under the condition of 100 microseconds, the obtained flat band voltage shifts by -2.2V, so the storage window reaches 4.2V. Further, if the programming and erasing time is shortened to 10 microseconds, the storage window can also reach 2.5V. This shows that the memory capacitor structure of the present invention can be effectively programmed and erased, and has a very fast erasing and writing speed. the

Figure 5 shows the charge retention characteristics of the storage capacitor fabricated in this example after being programmed at +8V for 1 millisecond and erased at -8V for 1 millisecond. The results show that the storage window of this structure is still as high as 5.5V when extrapolated to ten years, showing excellent charge retention properties. the

In a word, the storage capacitor structure proposed by the invention has excellent characteristics such as good programming and erasing characteristics, long charge retention time, etc., and has a good application prospect in flash memory. the

Claims (4)

1. the electric capacity of a mixed nano-crystal memory is substrate layer with the p type single crystal silicon sheet, it is characterized in that on it being in regular turn:

1) Al that grows by the atomic layer deposition method ₂O ₃Nano thin-film, as the electric charge tunnel layer, film thickness is 5～10 nanometers;

2) be ruthenium and the ruthenium-oxide mixed nano-crystal layer that the ruthenium layer of 1-4 nanometer forms by original depth;

3) Al that grows by the atomic layer deposition method ₂O ₃Film, film thickness are 15～40 nanometers, carry out high-temperature heat treatment after, as the barrier layer;

4) gate electrode layer that is formed by the lift-off method, gate electrode layer thickness are 50～200 nanometers, and material is a Metal Palladium.

2. the electric capacity of mixed nano-crystal memory according to claim 1, it is characterized in that: described ruthenium and ruthenium-oxide mixed nano-crystal layer are the ruthenium layers by magnetron sputtering one deck 1-4 nanometer thickness, and under 600-900 ℃ the temperature in the mixed atmosphere of nitrogen and trace oxygen rapid thermal annealing 10-30 form after second.

3. the electric capacity of mixed nano-crystal memory according to claim 1 is characterized in that: described Al ₂O ₃Film barrier layer is to adopt atomic layer deposition method deposition, carries out rapid thermal annealing 10-30 after the deposit in the nitrogen and form after second under 600-800 ℃ temperature.

4. the preparation method of the electric capacity of mixed nano-crystal memory according to claim 1 is characterized in that concrete steps are as follows:

1) adopts the p type single crystal silicon sheet as substrate, at first, silicon chip is cleaned, remove residual natural oxidizing layer with diluted hydrofluoric acid;

2) form the electric charge tunnel layer: the method growth Al that adopts atomic layer deposition ₂O ₃Film is controlled underlayer temperature in 250-350 ℃ of scope, Al during precipitation ₂O ₃Reaction source select trimethyl aluminium and water vapour, Al for use ₂O ₃Thickness is the 5-10 nanometer;

3) form the mixed nano-crystal layer: adopt the method deposit super thin metal ruthenium layer of magnetron sputtering, the thickness of ruthenium layer is the 1-4 nanometer, carries out rapid thermal annealing then in nitrogen and trace oxygen, form ruthenium, ruthenium-oxide mixed nano-crystal, wherein, annealing temperature is 600-900 ℃, and the time is 10-30 second;

4) form the barrier layer: the method that adopts atomic layer deposition is at mixed nano-crystal/Al ₂O ₃The long Al of surface regeneration ₂O ₃Film, as the barrier layer, thickness is the 15-40 nanometer; The control underlayer temperature is controlled at 250-350 ℃, Al during precipitation ₂O ₃Reaction source select trimethyl aluminium and water vapour for use;

5) form gate electrode: adopt " lift-off " method to form electrode, promptly at first on photoresist, form gate patterns by photoetching, then adopting the electron beam evaporation growth thickness is the palladium layer of 50-200 nanometer, last, cleans remaining photoresist to form gate electrode through acetone.

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