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CN103400806A - 一种基于框架采用切割道优化技术的扁平封装件的制作工艺 - Google Patents

一种基于框架采用切割道优化技术的扁平封装件的制作工艺 Download PDF

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CN103400806A
CN103400806A CN2013102756150A CN201310275615A CN103400806A CN 103400806 A CN103400806 A CN 103400806A CN 2013102756150 A CN2013102756150 A CN 2013102756150A CN 201310275615 A CN201310275615 A CN 201310275615A CN 103400806 A CN103400806 A CN 103400806A
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李万霞
李站
崔梦
魏海东
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本发明公开了一种基于框架采用切割道优化技术的扁平封装件的制作工艺，所述制作工艺：晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→蚀刻切割道→切割→检验→包装→入库。本发明在切割工序中能有效避免产品毛刺以及分层，进一步提高产品可靠性。

Description

一种基于框架采用切割道优化技术的扁平封装件的制作工艺
 
技术领域
本发明涉及集成电路封装技术领域，具体是一种基于框架采用切割道优化技术的扁平封装件的制作工艺。
背景技术
QFN（四面扁平无引脚封装）及DFN（双扁平无引脚封装）封装是在近几年随着通讯及便携式小型数码电子产品(数码相机、手机、PC、MP3)的产生而发展起来的、适用于高频、宽带、低噪声、高导热、小体积、高速度等电性要求的中小规模集成电路的封装。QFN/DFN封装有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。但目前大部分半导体封装厂商QFN/DFN的制造过程中都面临一些工艺困惑，原因是现有QFN/DFN工艺的塑封工序中，由于框架结构的局限性，使用的台阶状引线框架的防缺陷（分层）工艺措施并非完全有效，导致QFN/DFN封装存在以下不足：
QFN、DFN系列扁平封装件在切割过程中会有造成毛刺的风险，降低产品封装可靠性。框架与塑封料结合方面也容易引起分层，造成产品的不良。
发明内容
为了克服上述现有技术存在的问题，本发明的目的是提供一种基于框架采用切割道优化技术的扁平封装件的制作工艺，集成电路框架与塑封体结合更加牢固，不受外界环境影响，在切割工序中能有效避免产品毛刺以及分层，进一步提高产品可靠性。
一种基于框架的扁平封装件主要由引线框架、粘片胶、芯片、键合线和塑封体组成。所述引线框架与芯片通过粘片胶连接，键合线连接引线框架和芯片，塑封体包围了引线框架、粘片胶、芯片和键合线。塑封体对芯片和键合线起到了支撑和保护作用。芯片、键合线、塑封体、引线框架构成了电路的电源和信号通道。
一种基于框架采用切割道优化技术的扁平封装件的制作工艺如下：晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→蚀刻切割道→切割→检验→包装→入库。
一种基于框架采用切割道优化技术的扁平封装件的制作工艺，按照以下步骤进行：
第一步、晶圆减薄：晶圆减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
第二步、划片：150μm以上晶圆同普通QFN/DFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
第四步、压焊、塑封、后固化，与常规QFN/DFN工艺相同；
第五步、蚀刻切割道，产品分离：使用化学溶液将引线框架的切割道部分全部蚀刻，在引线框架的切割道部分蚀刻掉之后，再进行产品的分离；
第六步、检验、包装等均与常规QFN/DFN工艺相同。
附图说明
图1引线框架剖面图；
图2产品上芯后剖面图；
图3产品压焊后剖面图；
图4产品塑封后剖面图；
图5 产品切割道引线框架蚀刻前剖面图；
图6产品切割道引线框架蚀刻后剖面图；
图7产品分离后剖面图；
图8成品剖面图。
图中，1为引线框架，2为粘片胶，3为芯片，4为键合线，5为塑封体。
具体实施方式
以下根据附图对该发明做进一步的说明。
如图8所示，一种基于框架的扁平封装件主要由引线框架1、粘片胶2、芯片3、键合线4和塑封体5组成。所述引线框架1与芯片3通过粘片胶2连接，键合线4连接引线框架1和芯片3，塑封体5包围了引线框架1、粘片胶2、芯片3和键合线4。塑封体5对芯片3和键合线4起到了支撑和保护作用。芯片3、键合线4、塑封体5、引线框架1构成了电路的电源和信号通道。
一种基于框架采用切割道优化技术的扁平封装件的工艺流程如下：晶圆减薄→划片→上芯（粘片）→压焊→塑封→后固化→蚀刻切割道→切割→检验→包装→入库。
如图所示，一种基于框架采用切割道优化技术的扁平封装件的制作工艺，按照以下步骤进行：
第一步、晶圆减薄：晶圆减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
第二步、划片：150μm以上晶圆同普通QFN/DFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
第四步、压焊，塑封，后固化，与常规QFN/DFN工艺相同；
第五步、蚀刻切割道，产品分离：使用化学溶液将引线框架的切割道部分全部蚀刻，在引线框架的切割道部分蚀刻掉之后，再进行产品的分离；
由于切割道部分的引线框架已经被全部蚀刻，产品分离时只切割塑封体即可实现产品的分离，由于避免了切割刀和引线框架的直接接触，减小了引线框架的受力面积，降低应力，从而降低了产品切割时出现分层以及毛刺的可能性，提高了产品的可靠性，保证了产品的封装良率；
第六步、检验、包装等均与常规QFN/DFN工艺相同。

Claims (1)

1.一种基于框架采用切割道优化技术的扁平封装件的制作工艺，其特征在于：按照以下步骤进行：
第一步、晶圆减薄：晶圆减薄厚度50μm～200μm，粗糙度Ra 0.10mm～0.05mm ；
第二步、划片：150μm以上晶圆同普通QFN/DFN划片工艺，但厚度在150μm以下晶圆，使用双刀划片机及其工艺；
第三步、上芯（粘片）：既可采用粘片胶又可采用胶膜片（DAF）上芯；
第四步、压焊、塑封、后固化，与常规QFN/DFN工艺相同；
第五步、蚀刻切割道，产品分离：使用化学溶液将引线框架的切割道部分全部蚀刻，在引线框架的切割道部分蚀刻掉之后，再进行产品的分离；
第六步、检验、包装等均与常规QFN/DFN工艺相同。
CN2013102756150A 2013-07-03 2013-07-03 一种基于框架采用切割道优化技术的扁平封装件的制作工艺 Pending CN103400806A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681449A (zh) * 2013-12-02 2015-06-03 英飞凌科技股份有限公司 带有光学检查特征的无引线半导体封装
CN107079582A (zh) * 2017-01-22 2017-08-18 乐健科技（珠海）有限公司 电路基板及其制造方法、电路板及其制造方法
CN114334671A (zh) * 2021-12-31 2022-04-12 江苏芯德半导体科技有限公司 采用双刀切双排管脚的qfn封装方法
CN116387198A (zh) * 2023-04-07 2023-07-04 上海聚跃检测技术有限公司 一种qfn封装芯片的切割分离方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546718A (zh) * 2008-02-01 2009-09-30 英飞凌科技股份有限公司 半导体装置封装和制造半导体装置封装的方法
US20100224970A1 (en) * 2009-03-09 2010-09-09 Asat Ltd. Leadless integrated circuit package having standoff contacts and die attach pad
US20120205811A1 (en) * 2011-02-14 2012-08-16 Byung Tai Do Integrated circuit packaging system with terminal locks and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546718A (zh) * 2008-02-01 2009-09-30 英飞凌科技股份有限公司 半导体装置封装和制造半导体装置封装的方法
US20100224970A1 (en) * 2009-03-09 2010-09-09 Asat Ltd. Leadless integrated circuit package having standoff contacts and die attach pad
US20120205811A1 (en) * 2011-02-14 2012-08-16 Byung Tai Do Integrated circuit packaging system with terminal locks and method of manufacture thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681449A (zh) * 2013-12-02 2015-06-03 英飞凌科技股份有限公司 带有光学检查特征的无引线半导体封装
CN107079582A (zh) * 2017-01-22 2017-08-18 乐健科技（珠海）有限公司 电路基板及其制造方法、电路板及其制造方法
CN114334671A (zh) * 2021-12-31 2022-04-12 江苏芯德半导体科技有限公司 采用双刀切双排管脚的qfn封装方法
CN116387198A (zh) * 2023-04-07 2023-07-04 上海聚跃检测技术有限公司 一种qfn封装芯片的切割分离方法

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