CN103390543B - A kind of method for the surface area for increasing inductance - Google Patents
A kind of method for the surface area for increasing inductance Download PDFInfo
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- CN103390543B CN103390543B CN201310320984.7A CN201310320984A CN103390543B CN 103390543 B CN103390543 B CN 103390543B CN 201310320984 A CN201310320984 A CN 201310320984A CN 103390543 B CN103390543 B CN 103390543B
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- coating
- oxide skin
- wire lead
- lead slot
- area
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000011248 coating agent Substances 0.000 claims abstract description 36
- 238000000576 coating method Methods 0.000 claims abstract description 36
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 14
- 239000010937 tungsten Substances 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000004411 aluminium Substances 0.000 claims abstract description 6
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
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Abstract
A kind of method for the surface area for increasing inductance, including：The silicon chip with first area and second area is provided, wherein first area includes the lamination of the first oxide skin(coating) and the second oxide skin(coating), and second area includes the lamination of the first oxide skin(coating), intermediate metal layer and the second oxide skin(coating)；In the second area while etched circuit fairlead, strip wire lead slot is etched in the second oxide skin(coating) of first area；In circuit lead hole while deposits tungsten, tungsten layer is formed on the bottom of strip wire lead slot and side wall；Deposition of aluminum on the second oxide skin(coating) so that form aluminium lamination after cmp is carried out to tungsten layer, the strip wire lead slot is filled simultaneously, to cause second oxide skin(coating) separated by the strip wire lead slot to be connected due to the filling to the strip wire lead slot, wherein the gap that the strip wire lead slot is formed in second oxide skin(coating) is not completely filled.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of surface area for increasing inductance
Method.
Background technology
Kelvin effect is also known as " kelvin effect ".Specifically, as alternating current (alternatingelectric
Current, AC) when passing through conductor, because induction effect causes CURRENT DISTRIBUTION on cross-sectional area of conductor uneven, nearer conductive surface electricity
Current density is bigger；This phenomenon claims " Kelvin effect ".Kelvin effect increases the effective resistance of conductor.When the very high electric current of frequency
When passing through wire, it is believed that electric current is only flowed through in one layer very thin in conductive line surfaces, and this section for being equivalent to wire reduces,
Resistance increases.
The current density that skin depth refers under this depth is the 1/e of surface current density, that is, 0.368 times,
Increase after electric current is not without more than twice of skin depth wire thickness it is limited to increase Q values but be not it is useless,
During 1GHz, Al skin depth is 2.8um.
For the alternating current in conductor, the current density at conductive surface is more than showing for conductor current density
As.With the raising of power frequency, Kelvin effect increases the resistance of conductor, and inductance reduces.
Prior art proposes a kind of method for being called Litz coilings, and this method can effectively improve the Q values of inductance（Especially
It is at high frequencies）, prior art realize the method for Litz coilings be using photoetching and etching method realize multiply around
Line, but be limited to lithographic dimensioned and etching processing procedure ability, the distance between coiling that this method is realized can be larger, density compared with
It is low.
The content of the invention
The technical problems to be solved by the invention are to be directed to have drawbacks described above in the prior art, there is provided one kind can pass through
Simple process realizes high density Litz coilings, increases the method for the surface area of inductance.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of method of high density Litz wire-wound inductors,
It includes：
First step：The silicon chip with first area and second area is provided, wherein first area includes the first oxide
The lamination of layer and the second oxide skin(coating), second area include the folded of the first oxide skin(coating), intermediate metal layer and the second oxide skin(coating)
Layer；
Second step：In the second area while etched circuit fairlead, in the second oxide skin(coating) of first area
Etch strip wire lead slot；
Third step：In circuit lead hole while deposits tungsten, formed on the bottom of strip wire lead slot and side wall
Tungsten layer；
Four steps：Deposition of aluminum on the second oxide skin(coating) so that form aluminium after cmp is carried out to tungsten layer
Layer, while the strip wire lead slot is filled, to cause second oxidation separated by the strip wire lead slot
Nitride layer is connected due to the filling to the strip wire lead slot, wherein the strip wire lead slot is in second oxide skin(coating)
The gap of middle formation is not completely filled.
Preferably, three points of the width of the strip wire lead slot more than or equal to the thickness of the strip wire lead slot
One of.
Preferably, a plurality of parallel strip wire lead slot is formed in the second step.
Preferably, the first oxide skin(coating) and the second oxide skin(coating) are silicon dioxide layers.
In the method for the invention, by forming strip wire lead slot, single inductance can be become multiply structure
Inductance；Add effective surface area, improve the performance of inductance, at the same the structure of this multiply coiling can accomplish maximum around
Line density.
Thus, the invention provides a kind of surface area that can increase inductance by simple process and by inductance it is single around
The method that line becomes more coilings, the method can be effectively increased the Q values of inductance.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And be more easily understood its with the advantages of and feature, wherein：
Fig. 1 schematically shows the flow chart of the method for the surface area of increase inductance according to embodiments of the present invention.
Fig. 2 to Fig. 5 schematically shows each of the method for the surface area of increase inductance according to embodiments of the present invention
Individual step.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Pay attention to, represent that the accompanying drawing of structure can
It can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 1 schematically shows the flow chart of the method for the surface area of increase inductance according to embodiments of the present invention.
Specifically, as shown in figure 1, the method for the surface area of increase inductance according to embodiments of the present invention includes：
First step S1：The silicon chip with first area and second area is provided, wherein first area includes the first oxidation
The lamination of the oxide skin(coating) 10 of nitride layer 100 and second, second area include the first oxide skin(coating) 100, intermediate metal layer 200 and second
The lamination of oxide skin(coating) 10, as shown in fig. 3 in cross section, first area is belonged on the left of dotted line, belongs to second area on the right side of dotted line；
Wherein, for example, the first oxide skin(coating) 100 and the second oxide skin(coating) 10 are silicon dioxide layers.
Second step S2：In the second area while etched circuit fairlead 21, the second oxide in first area
Strip wire lead slot 20 is etched in layer 10.
Wherein, first area does not have intermediate metal layer 200 to be used as etching barrier layer, and strip wire lead slot 20 can enter described
First oxide skin(coating) 100；The intermediate metal layer 200 as etching barrier layer in second area be present, circuit lead hole 21 is in
Between metal level 200 stop, as shown in Figures 2 and 3, wherein Fig. 2 is top view, and Fig. 3 is sectional view；
In the present invention, the width of the strip wire lead slot 20 is larger.Preferably, in a preferred embodiment of the invention,
The width of the strip wire lead slot 20 is more than or equal to 1/3rd of the thickness of the strip wire lead slot 20.
Wherein it is preferred to a plurality of parallel strip wire lead slot 20 is formed in second step S2.
Preferably, the second step S2 can be integrated in the circuit lead hole of semiconductor manufacturing（Through hole）In formation process,
Without adding new processing step,
Third step S3：The deposits tungsten in circuit lead hole 21（Tungsten is fully filled with circuit lead hole 21）While, in length
Tungsten layer 31 is formed on the bottom of bar-shaped lead groove 20 and side wall.The third step S3 can be integrated in the fairlead of semiconductor manufacturing
（Through hole）Tungsten depositing operation in, without adding new processing step.
Four steps S4：Cmp is being carried out to tungsten layer 31（CMP）Deposition of aluminum is so as in the second oxide afterwards
Aluminium lamination 40 is formed on layer 10, while the strip wire lead slot 20 is filled, to cause by the strip wire lead slot 20
Second oxide skin(coating) 10 separated is connected due to the filling to the strip wire lead slot 20, wherein the strip draws
The gap that wire casing 20 is formed in second oxide skin(coating) 10 is not completely filled（That is, the technique only part of deposition of aluminum is filled out
The gap formed is filled in second oxide skin(coating) 10）.
In the fourth step s 4, because strip wire lead slot 20 is spaced apart, so the aluminium formed on the second oxide skin(coating) 10
Layer 40 forms naturally segmentation, so as to form the induction structure that the aluminium lamination 40 of inductance is formed multiply structure.
So, in the method for the above embodiment of the present invention, inductance is formed by strip wire lead slot, wherein passing through to be formed
Strip wire lead slot, single inductance can be become to the inductance of multiply structure；And due to the of strip wire lead slot both sides
Dioxide layer side wall（Referring to Fig. 5 side wall 41）Appearance, add effective surface area, improve the performance of inductance, simultaneously
The structure of this multiply coiling can accomplish maximum around line density.Moreover, all steps of the present invention are integrated in circuit and led to
In the manufacturing process in hole, new technique or cost will not be increased.
Thus, above preferred embodiment of the present invention provides a kind of surface area for increasing inductance and single coiling by inductance
Become the method for more coilings, the method can be effectively increased the Q values of inductance.
Furthermore, it is necessary to explanation, unless stated otherwise or is pointed out, the otherwise term in specification " first ", " the
Two ", the description such as " 3rd " is used only for distinguishing each component in specification, element, step etc., each without being intended to indicate that
Logical relation or ordinal relation between component, element, step etc..
It is understood that although the present invention is disclosed as above with preferred embodiment, but above-described embodiment and it is not used to
Limit the present invention.For any those skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications are all made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of change.Therefore, every content without departing from technical solution of the present invention, the technical spirit pair according to the present invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection
It is interior.
Claims (3)
- A kind of 1. method for the surface area for increasing inductance, it is characterised in that including：First step：Silicon chip with first area and second area is provided, wherein first area include the first oxide skin(coating) and The lamination of second oxide skin(coating), second area include the lamination of the first oxide skin(coating), intermediate metal layer and the second oxide skin(coating)；Second step：In the second area while etched circuit fairlead, etched in the second oxide skin(coating) of first area Strip wire lead slot；The width of the strip wire lead slot be more than or equal to the strip wire lead slot thickness three/ One；Third step：In circuit lead hole while deposits tungsten, tungsten layer is formed on the bottom of strip wire lead slot and side wall；Four steps：Deposition of aluminum is so as on the second oxide skin(coating) form aluminium lamination after cmp is carried out to tungsten layer, The strip wire lead slot is filled simultaneously, to cause second oxide skin(coating) separated by the strip wire lead slot Connected due to the filling to the strip wire lead slot, wherein strip wire lead slot shape in second oxide skin(coating) Into gap be not completely filled.
- 2. the method for the surface area of increase inductance according to claim 1, it is characterised in that formed in the second step The a plurality of parallel strip wire lead slot.
- 3. it is according to claim 1 increase inductance surface area method, it is characterised in that the first oxide skin(coating) and Second oxide skin(coating) is silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310320984.7A CN103390543B (en) | 2013-07-26 | 2013-07-26 | A kind of method for the surface area for increasing inductance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310320984.7A CN103390543B (en) | 2013-07-26 | 2013-07-26 | A kind of method for the surface area for increasing inductance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103390543A CN103390543A (en) | 2013-11-13 |
| CN103390543B true CN103390543B (en) | 2017-11-24 |
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| CN201310320984.7A Active CN103390543B (en) | 2013-07-26 | 2013-07-26 | A kind of method for the surface area for increasing inductance |
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Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667217B1 (en) * | 2001-03-01 | 2003-12-23 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process |
| US6444517B1 (en) * | 2002-01-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | High Q inductor with Cu damascene via/trench etching simultaneous module |
| US7436281B2 (en) * | 2004-07-30 | 2008-10-14 | Texas Instruments Incorporated | Method to improve inductance with a high-permeability slotted plate core in an integrated circuit |
| KR100598113B1 (en) * | 2005-01-03 | 2006-07-07 | 삼성전자주식회사 | Inductors and Inductor Formation Methods |
| KR100737155B1 (en) * | 2006-08-28 | 2007-07-06 | 동부일렉트로닉스 주식회사 | Method for manufacturing high frequency inductor of semiconductor device |
| KR100824635B1 (en) * | 2006-09-13 | 2008-04-24 | 동부일렉트로닉스 주식회사 | Inductor manufacturing method using system-in-package |
| JP5268345B2 (en) * | 2007-12-20 | 2013-08-21 | パナソニック株式会社 | Inductor |
| CN102165576B (en) * | 2008-09-26 | 2013-12-25 | 罗姆股份有限公司 | Semiconductor device and semiconductor device manufacturing method |
| US8232173B2 (en) * | 2010-11-01 | 2012-07-31 | International Business Machines Corporation | Structure and design structure for high-Q value inductor and method of manufacturing the same |
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| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140506 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140506 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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