CN103326735B - A kind of DC deviation bearing calibration of wireless intermediate frequency receiver circuit system - Google Patents
A kind of DC deviation bearing calibration of wireless intermediate frequency receiver circuit system Download PDFInfo
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Abstract
The invention discloses a kind of DC deviation bearing calibration of the wireless intermediate frequency receiver circuit system of high reliability, in wireless intermediate frequency receiver circuit system, after radio frequency signal is through antenna reception, amplified by low-noise amplifier, then low-frequency intermediate frequency signal is produced through frequency mixer and oscillator mixing, the direct current biasing part that low-noise amplifier and frequency mixer are produced is also divided into I passages and Q passages enter complex bandpass filters and amplifier, subsequently into plural band logical Δ ∑ analog-digital converter etc. module output digit signals to base band.Baseband digitized DC deviation sample averaging module calculates the mean value of the DC deviation of the I passages and Q passages of last output on the basis of many sub-samplings, and pass through DC deviation feedback compensation circuit, respectively the DC deviation of I passages and Q passages is corrected in three times, impact of the DC deviation to wireless intermediate frequency receiver circuit system is eliminated, the dynamic range of wireless system receiver signal is improve.
Description
Technical field
The present invention relates in the semiconductor technology and circuit design technique in electronic engineering, particularly radio frequency (RF) circuit
Intermediate frequency (IF) receiving circuit system, and the complex bandpass filters that included and amplifier circuit module.
Background technology
Antenna (Antenna), low-noise amplifier (LNA), frequency mixer is generally included in radio frequency (RF) receiving circuit
(Mixer) modules such as, low pass filter (LPF), signal amplifier (VGA), analog-digital converter (ADC).If take directly turned
The mode of (Direct Conversion) is changed, and signal path is received in the frequency mixer stage and oscillator (LO) clock path is easy
Intercouple leakage, so causes self mixing and produces DC deviation.In order to avoid this problem, in being much designed with
Frequently the mode of (IF) circuit, that is, be divided into two stages to isolate original signal from RF signals.First stage is made in frequency mixer
It is mixed with the frequency for being slightly less than transmitting LO clocks, at this moment will be used complex bandpass filters (BPF) and amplifier (VGA)
To replace low pass filter (LPF) and amplifier (VGA) in directly conversion (Direct Conversion) circuit；Second-order
Section digitally decodes original signal in base band.The DC deviation that the frequency mixer of so intermediate frequency I/F circuit is caused drops significantly
Low, and the main source of DC deviation is no longer self mixing of mixer module, but other factors, such as difference channel are not right
Claim, process deviation etc., the gain of particularly circuit is especially apparent when big.
The difficult point of the DC deviation correction of wireless intermediate frequency receiver circuit system is：Due to intermediate-frequency circuit process is plural number
Frequency, so I passages and Q channel circuits have interaction feedback to act on.For detached I passages or Q passages, due to not feeding back to
The presence on road, DC deviation timing need to only sample output direct current biasing then carry out disposable current compensation just can be by direct current
Biasing drops to very low level.But for I passages and the interaction feedback of Q channel circuits, even if after I channel correctings, leading in correction Q
The direct current biasing of I passages may be allowed during road to return to very poor level.Even if being followed to I passages and Q passages repeatedly
Ring is corrected, and the direct current biasing of output end may not restrained, it is difficult to be reduced to preferable level.This is outstanding in the situation of high-gain
Its substantially, due to the sensitivity of at this moment circuit bigger.
A lot of at present wireless intermediate frequency receiver circuit systems are still adopted to complex bandpass filters (BPF) and amplifier
(VGA) I passages and the recirculation correction of Q passages, till then obtaining relatively small DC deviation (80mv-100mv),
Such that rear stage plural number band logical Δ ∑ analog-digital converter (ADC) of if bandpas filter (BPF) and amplifier (VGA)
Saturation is easy to, dynamic range of signals reduces, so as to reduce the performance of system；And this mode is inclined due to cannot ensure direct current
Difference arrives minimum of a value, so great DC deviation can be caused under the worst situation of technique, so will also result in chip yield
(Yield) decline.
Although some modes interfere with each other problem, such as high pass solving the DC deviation that I passages and Q passages are caused
(Qualcomm) United States Patent (USP)s US2011/0037506A1 in 2011, add out in the path that I passages and Q passages are coupled
Close control to separate the direct current biasing of sampling I passages and Q passages and be corrected, but this method has individual it is assumed that being exactly when I is logical
When road is identical with the direct current biasing level that the amplifier of Q passages is produced, adopts and direct current biasing can be dropped to extremely low level in this way.
But bandpass filter and amp DC biasing mechanism ability precisely due to some random factors, such as technique cause several
What size deviates, and symmetry is inadequate etc., so while direct current biasing can be reduced by this mode in most of situations, but
It is not a kind of reliable method.When I passages are different with the direct current biasing level of Q passages or during even opposite polarity, which school
Positive result is just undesirable.
Content of the invention
Based at present for wireless intermediate frequency receiver circuit system, including complex bandpass filters and the direct current biasing of amplifier
The integrity problem that circuit is present, the present invention is on the basis of strict theory analysis, it is proposed that a kind of reliable and stable including multiple
Count the correcting mode of bandpass filter and amplifier in the direct current biasing of interior wireless intermediate frequency receiver circuit system.
For the situation that I passages and Q passages in complex bandpass filters and amplifier intercouple, I passages are in wave filter
DC deviation with amplifier out is：
Wherein, Δ MIWith Δ MQBe I passages and Q passages complex bandpass filters and amplifier previous stage module produce straight
Stream bias, and Δ VIWith Δ VQIt is then that complex bandpass filters and amplifier sheet are produced in I passages and Q passage amplifiers input
Dc bias.Equally, Q passages in the Dc bias of wave filter and amplifier out are：
Above-mentioned analysis is based on, present invention design takes following manner inclined to reduce and offset direct current produced by intermediate-frequency circuit
Difference：
A. design R and R0 take same resistance come so thatThe DC deviation that item is generated is zero；This condition is easy to
Realize, because complex bandpass filters and amplifier circuit gain are determined by R/Ri, if R is fixed as R0 values, only can change
Ri is reaching the purpose (VGA) of variable gain；
B. increase I channel switch SWI, when such SWI is switched off Ri equivalent to ∞ so that DC deviation itemIt is zero；
C. increase Q channel switch SWQ, when such SWQ is switched off Ri equivalent to ∞ so that DC deviation item isZero；
Be based on above-mentioned analysis, the present invention design take following steps come realize reduce output end Dc bias to close to
Zero level：
A. when medium frequency reception and complex bandpass filters and amplifier system are designed using same resistance attenuated feedback
Resistance R and coupling frequency displacement resistance R0；So cause in I passages and Q passages output DC deviationIt is straight that item is generated
Stream deviation is zero；
B. I passages and Q channel signal input end switch SWI and SWQ are disconnected so that DC deviation itemWith
All it is zero；Iq1 current sources amplitude is adjusted using direct current biasing sampling feedback compensation circuit to compensate bias current
And I passages and Q channel DCs deviation are reduced to simultaneously close to zero；
C. disconnect Q channel signal input end switch to causeIt is zero, connects I path inputs switch, by sampling
Feedback circuit adjusts Ii2 current sources amplitude to compensate bias currentAnd I passages and Q channel DCs deviation are subtracted simultaneously
Little to close to zero；
D. I passages and Q path inputs switch is connected, and Iq2 current sources amplitude is adjusted by sampling feedback circuit to compensate
Bias currentAnd I passages and Q channel DCs deviation are reduced to simultaneously close to zero；
Above-mentioned analysis is based on, due to Δ MIWith Δ MQIt is the direct current produced by I passages and Q passages are exported in frequency mixer respectively
Deviation, so the correcting mode of the present invention includes DC deviation of the correction produced by low-noise amplifier and frequency mixer；
Above-mentioned analysis is based on, due to Δ VIWith Δ VQIt is complex bandpass filters and amplifier sheet respectively in I passages and Q
The Dc bias that passage amplifier input is produced, thus the correcting mode of the present invention include correction by complex bandpass filters and
The DC deviation that amplifier is produced；
Above-mentioned analysis is based on, the present invention is at plural band logical Δ ∑ analog-digital converter (Complex Band-pass Δ ∑ ADC)
Digital output end adopts baseband digitized direct current biasing sample averaging, calculates on the basis of many sub-sampling (1000-2000 time)
Go out the mean value of the DC deviation of the I passages and Q passages of last output, and pass through DC deviation feedback compensation circuit.So this
Invention correction result be so that whole intermediate-frequency circuit output DC deviation be reduced to the level close to zero, also include by
The DC deviation that plural band logical Δ ∑ analog-digital converter (ComplexBand-pass Δ ∑ ADC) is produced；
Though being not expressly mentioned, current source compensation way of the present invention can be single-ended or differential compensation.Lead in differential compensation
The electrode input end and negative input in road has compensating current element, and its amplitude is equal but opposite polarity.
The present invention is taken less than digital to analog converter (DAC) to the precision that the DC deviation of wireless intermediate frequency receiver circuit system is corrected
Lowest order (LSB) representated by DC deviation level.So the precision of D AC is higher, the precision of final DC deviation correction
Higher.
Description of the drawings
Fig. 1 is the built-up circuit module of wireless intermediate frequency receiver circuit system and signal path；
Fig. 2 is the access way of the circuit structure and DC offset correction current source of complex bandpass filters and amplifier；
Fig. 3 is the internal module figure of DC deviation feedback compensation circuit；
Fig. 4 is wireless intermediate frequency receiver circuit system dc correction for drift step；
Fig. 5 is the output waveform of DC deviation correcting process.
Following specific embodiment will be described with reference to the drawings.
Specific embodiment
The be suitable for wireless intermediate frequency receiver circuit system of DC deviation correcting mode of the present invention is as shown in Figure 1.RF signals by
Antenna (101) is entered, through low-noise amplifier (LNA, 102) after divide two-way send into frequency mixer (Mixer, 103 and 104), point
Jin Ru not I passages and Q passages；Next I passages and Q channel signals enter complex bandpass filters and amplifier (Complex
BPF and VGA, 105), through plural band logical Δ ∑ analog-digital converter (Complex Band-pass Δ ∑ ADC, 107) after become
Baseband signal.Baseband digitized DC deviation sample averaging module is calculated on the basis of many sub-sampling (1000-2000 time)
The I passages for finally exporting and the mean value of the DC deviation of Q passages, and pass through DC deviation feedback compensation circuit, in three times so
The output for generating control electric current source afterwards enters the input of complex bandpass filters and amplifier.Due to complex bandpass filters and
Amplifier is located at centre, so its direct current biasing is also affected by above frequency mixer and low-noise amplifier.
Fig. 2 is circuit structure and the access way in DC deviation correcting current source of complex bandpass filters and amplifier.
Design of circuit system part includes：
A. when medium frequency reception and wave filter and amplifier system are designed using same resistance attenuated feedback resistance R and coupling
Sum of fundamental frequencies moves resistance R0；
B. DC deviation correcting current compensation point has at three：Ii2 was accessed before I passage input resistance Ri, to eliminate
Come from the DC deviation of previous stage frequency mixer I passages output；Iq2 was accessed before Q passage input resistance Ri, was come with eliminating
From the DC deviation exported in previous stage frequency mixer I passages；Iq1 be after passage input resistance Ri access, with eliminate from
DC deviation in Q channel operation amplifier ins；
C. why the DC deviation of I channel operation amplifier ins need not compensate for (without current source Ii1) be because
It is the attenuated feedback resistance R of same resistance used in claim 2a and coupling frequency displacement resistance R0, so putting in I channel operations
It is zero that big device DC deviation is offset in the effect that output end is produced.
The module of DC deviation feedback compensation circuit includes in figure 3：
A.I passages and the digitlization of Q channel DCs deviation average judge
B. successive approximation register algorithm logic and corresponding register (SAR)
C. multidigit high precision digital-to-analog converter (DAC)
D. controlled current source
Aligning step that medium frequency reception wave filter and amplifier circuit DC deviation are fixed as shown in figure 4, including：
A. electric on chip, system initialization, so register sets initial value 0；By the positive and negative defeated of low-noise amplifier (LNA)
Enter to hold short circuit；
B. I passages and Q channel signal input end switch is disconnected, Iq1 compensating current element width is adjusted by sampling feedback circuit
Degree；
C. adjust Iq1 compensating current element amplitudes number of times and depend on multidigit high accuracy digital-to-analogue in DC deviation feedback compensation circuit
The bit number of converter (DAC), connects until the DC deviation mean value of baseband digital parts I passages and Q passages is reduced to simultaneously
It is bordering on zero；
D. Q channel signal input end switch is disconnected, connects I path inputs switch, Ii2 is adjusted by sampling feedback circuit
Compensating current element amplitude；
E. adjust Ii2 compensating current element amplitudes number of times and depend on multidigit high accuracy digital-to-analogue in DC deviation feedback compensation circuit
The bit number of converter (DAC), connects until the DC deviation mean value of baseband digital parts I passages and Q passages is reduced to simultaneously
It is bordering on zero；
F. I passages and Q path inputs switch is connected, Iq2 is adjusted by DC deviation feedback compensation circuit and is compensated electric current
Source amplitude；
G. adjust Iq2 compensating current element amplitudes number of times and depend on multidigit high accuracy digital-to-analogue in DC deviation feedback compensation circuit
The bit number of converter (DAC), connects until the DC deviation mean value of baseband digital parts I passages and Q passages is reduced to simultaneously
It is bordering on zero；
H. the positive-negative input end short circuit of low-noise amplifier (LNA) is disconnected；Medium frequency reception wave filter and amplifier circuit
DC deviation trimming process terminates.
Fig. 5 is the oscillogram of DC deviation in continuous three trimming processes.The DC deviation of I and Q passage is corrected each time
All zero is reduced to almost simultaneously.But when switch switching, the DC deviation of I passages and Q passages is deteriorated, so school next time again
DC deviation is reduced to almost zero again just.Finally when all opening, direct current biasing is reduced to several by correcting process
When being zero, the state at this moment switching is also the state of normal circuit operation, so during normal work, corrected after circuit
DC deviation also almost nil.
Current source compensation way of the present invention can be single-ended or differential compensation.The electrode input end of passage in differential compensation
There is compensating current element with negative input, its amplitude is equal but opposite polarity.
Specific embodiment for the present invention illustrated above, but protection scope of the present invention is not limited thereto.Any ripe
The professional and technical personnel of the art is known in technical scope disclosed by the invention, the change or replacement for being readily occurred in, all
Should be included within the scope of the present invention.
Claims (4)
1. the DC deviation bearing calibration of wireless intermediate frequency receiver circuit system, the targeted circuit module of the method include：Wirelessly
Intermediate frequency receiver circuit system, baseband digitized DC deviation sample averaging module and DC deviation feedback compensation circuit；
The wireless intermediate frequency receiver circuit system includes：Antenna (101), low-noise amplifier (102), frequency mixer (103 Hes
104), complex bandpass filters and amplifier (105), plural band logical Δ ∑ analog-digital converter (107)；Wireless signal is connect by antenna
Receive and low-noise amplifier amplifies, then divide two-way to send into frequency mixer, respectively enter I passages and Q passages；Following I passages and Q
Channel signal enters complex bandpass filters and amplifier, is through the output of plural band logical Δ ∑ analog-digital converter whole wireless
The digital output signal of intermediate frequency receiver circuit system；Meanwhile, baseband digitized DC deviation sample averaging module is defeated to the numeral
Go out signal to be sampled, then through DC deviation feedback compensation circuit, feed back to the four of complex bandpass filters and amplifier
Individual input, carries out DC deviation correction；
Described complex bandpass filters and amplifier, its structure include：Two amplifiers and its input and output feedback resistance electricity
Hold and cross-couplings module；VIP and VIM is respectively the positive and negative terminal for being input into I channel signals；VQP and VQM are then input Q passage letters
Number positive and negative terminal；VIOP and VIOM is respectively the positive and negative terminal for exporting I channel signals；VQOP and VQOM are then output Q channel signals
Positive and negative terminal；When medium frequency reception and complex bandpass filters and amplifier system are designed using same resistance negative feedback resistor
R and coupling frequency displacement resistance R0；Negative feedback resistor R and coupling frequency displacement resistance R0 use the connection most commonly of wireless complex intermediate frequency circuit
Mode：Four negative feedback resistor R are connected to the input of the negative pole from the cathode output end VIOP of I channel amplifiers to amplifier
Between end；Between the cathode output end VIOM of I channel amplifiers and electrode input end；The cathode output end of Q channel amplifiers
VQOP is between negative input；Between the cathode output end VQOM of Q channel amplifiers and electrode input end；And four coupling frequencies
Move the cathode output end VQOP that resistance R0 is then cross connected to Q channel amplifiers respectively from the electrode input end of I channel amplifiers；
From the cathode output end VQOM that the negative input of I channel amplifiers is cross connected to Q channel amplifiers；From Q channel amplifiers
Electrode input end be cross connected to the cathode output end VIOM of I channel amplifiers；Hand over from the negative input of Q channel amplifiers
Fork is connected to the cathode output end VIOP of I channel amplifiers；In addition four resistance Ri are connected on the electrode input end of I passages respectively
Between VIP and the electrode input end of amplifier, between the negative input VIM and the negative input of amplifier of I passages, Q leads to
Between the electrode input end VQP and the electrode input end of amplifier in road, the negative input VQM and the negative pole of amplifier of Q passages
Between input；
The input of described plural band logical Δ ∑ analog-digital converter and output are all divided into I passages both positive and negative polarity and Q passage both positive and negative polarities, institute
With a total of four road signal；The four tunnels output of plural band logical Δ ∑ analog-digital converter is connected to the sampling of baseband digitized DC deviation
The input of averaging module, and the result of sample averaging point I passages and Q are led to by baseband digitized DC deviation sample averaging module
Road is sent to DC deviation feedback compensation circuit, and DC deviation feedback compensation circuit is then given birth to respectively according to the result of sample averaging
Control electric current into I passages and Q passages is correcting the DC deviation of system；
DC deviation correcting current compensation point has at three：Ii2 is that I negative pole input points VIM connect before I passage input resistance Ri
Enter, to eliminate the DC deviation for coming from the output of previous stage frequency mixer I passages；Iq2 is that Q bears before Q passage input resistance Ri
Pole input point VQM is accessed, to eliminate the DC deviation for coming from the output of previous stage frequency mixer Q passages；Iq1 is input in Q passages
After resistance Ri, amplifier negative input is accessed, to eliminate the DC deviation for coming from Q channel operation amplifier ins；
Why the DC deviation of I channel operation amplifier ins needs not compensate for being because in declining using same resistance
Subtract feedback resistance R and coupling frequency displacement resistance R0, supported in the effect that output end is produced in I channel operation amp DC deviations
Pin is zero；
The baseband digitized DC deviation sample averaging functions of modules includes：Continuously to plural band logical Δ ∑ analog-digital converter
The numeral output sampling of I passages and Q passages, carry out on the basis of multiple samples average, so as to obtain I passages and Q passages
The mean value of DC deviation；The mean value is digital two complemented lattices formula, and when highest order is 1 interval scale negative value, and highest order was 0 epoch
Table on the occasion of,
The DC deviation feedback compensation circuit includes：I passages and Q channel DCs deviation average digitlization determination module, by
Secondary approach type register algorithm logic and corresponding register, multidigit high precision digital-to-analog converter and controlled current source；
The internal module annexation of DC deviation feedback compensation circuit：It is inclined that input comes from baseband digitized direct current noted earlier
Difference sample averaging module, is divided into I passages and Q passages, sends into DC deviation average numbers determination module；And the determination module
The result of output sends into the input of successive approximation register algorithm logic and corresponding register module, determines register
Value；The numeral output of register is generated and is linked into plural band logical filter by multidigit high precision digital-to-analog converter and controlled current source
Ripple device and the corresponding control electric currents of three control electric current sources Ii2, Iq2 and Iq1 of amplifier；
The concrete steps of the DC deviation bearing calibration of the wireless intermediate frequency receiver circuit system include：
A. electric on chip, system initialization, all registers set initial value 0；And will be short for the positive-negative input end of low-noise amplifier
Connect；
B. I passages and Q channel signal input end switch are disconnected, by baseband digitized DC deviation sample averaging module and direct current
Deviation feedback compensation circuit adjusts Iq1 compensating current element amplitudes；
C. adjust Iq1 compensating current element amplitudes number of times and depend on multidigit high accuracy digital-to-analogue conversion in DC deviation feedback compensation circuit
The bit number of device, until the DC deviation mean value of baseband digital parts I passages and Q passages is reduced to close to zero simultaneously；
D. Q channel signal input end switch is disconnected, connects I path inputs switch, sampled by baseband digitized DC deviation
Averaging module and DC deviation feedback compensation circuit adjust Ii2 compensating current element amplitudes；
E. adjust Ii2 compensating current element amplitudes number of times and depend on multidigit high accuracy digital-to-analogue conversion in DC deviation feedback compensation circuit
The bit number of device, until the DC deviation mean value of baseband digital parts I passages and Q passages is reduced to close to zero simultaneously；
F. I passages and Q path inputs switch is connected, Iq2 compensating current element width is adjusted by DC deviation feedback compensation circuit
Degree；
G. adjust Iq2 compensating current element amplitudes number of times and depend on multidigit high accuracy digital-to-analogue conversion in DC deviation feedback compensation circuit
The bit number of device, until the DC deviation mean value of baseband digital parts I passages and Q passages is reduced to close to zero simultaneously；
H. the positive-negative input end short circuit of low-noise amplifier is disconnected；Wireless intermediate frequency receiver circuit system dc bias correction process
Terminate.
2. the DC deviation bearing calibration of wireless intermediate frequency receiver circuit system according to claim 1, it is characterised in that described
The average numbersization judgement of the DC deviation of I passages and Q passages, is output as 1 when base band DC deviation mean value is more than zero；
0 is output as when base band DC deviation mean value is less than zero.
3. the DC deviation bearing calibration of wireless intermediate frequency receiver circuit system according to claim 1, it is characterised in that described
Successive approximation register algorithm logic and corresponding register, in the following order generating the bit in control electric current source：
1) when initial, all bits are all set to zero；
2) highest order is switched to 1 from zero for the first time, then register control digital to analog converter generates corresponding compensation electric current and send
The input of complex bandpass filters and amplifier is arrived, following voltage comparator is defeated according to complex bandpass filters and amplifier
Go out to be sampled, generate comparative result；If comparator is output as 1, highest order is left 1；Else if comparator output
For 0, then highest order is reset to 0；
3) 2), successively repeat step determines the bit value from the second highest order to lowest order, after lowest order terminates, preserves this and posts
Storage bit value, uses in normal circuit operation.
4. the DC deviation bearing calibration of wireless intermediate frequency receiver circuit system according to claim 1, it is characterised in that described
Controlled current source represents the electric current generated by digital to analog converter according to the control bit position of register, is directly connected to plural band logical
The input of the I passages or Q passages of wave filter and amplifier.
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| CN108234369B (en) * | 2016-12-14 | 2020-11-03 | 奉加微电子（上海）有限公司 | Method and device for eliminating direct current offset |
| CN109274618B (en) * | 2018-10-17 | 2021-08-13 | 珠海市杰理科技股份有限公司 | Radio frequency receiver DC offset calibration method, computer device and storage medium |
| CN109361417A (en) * | 2018-11-29 | 2019-02-19 | 中电科仪器仪表有限公司 | A kind of signal processing method and system for zero intermediate frequency receiver direct current offset |
| CN114341667B (en) * | 2020-07-10 | 2023-08-04 | 深圳市速腾聚创科技有限公司 | Laser receiving circuit and laser radar |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5422889A (en) * | 1992-10-28 | 1995-06-06 | Alcatel N.V. | Offset correction circuit |
| CN1397108A (en) * | 2000-11-23 | 2003-02-12 | 皇家菲利浦电子有限公司 | DC-offset correction circuit having DC control loop and DC blocking circuit |
| CN1536770A (en) * | 2003-05-15 | 2004-10-13 | 威盛电子股份有限公司 | Direct conversion receiver with DC offset compensation function and compensation method thereof |
| CN102377707A (en) * | 2010-08-11 | 2012-03-14 | 齐凌微电子科技(上海)有限公司 | Direct current offset elimination method for zero intermediate frequency receiver |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8385863B2 (en) * | 2009-08-11 | 2013-02-26 | Qualcomm, Incorporated | DC offset calibration for complex filters |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5422889A (en) * | 1992-10-28 | 1995-06-06 | Alcatel N.V. | Offset correction circuit |
| CN1397108A (en) * | 2000-11-23 | 2003-02-12 | 皇家菲利浦电子有限公司 | DC-offset correction circuit having DC control loop and DC blocking circuit |
| CN1536770A (en) * | 2003-05-15 | 2004-10-13 | 威盛电子股份有限公司 | Direct conversion receiver with DC offset compensation function and compensation method thereof |
| CN102377707A (en) * | 2010-08-11 | 2012-03-14 | 齐凌微电子科技(上海)有限公司 | Direct current offset elimination method for zero intermediate frequency receiver |
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