CN103311280B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The application discloses a semiconductor device and a method of manufacturing the same. According to an example, a semiconductor device may include: a fin extending in a first direction, the fin including opposing first and second ends and opposing first and second sides connecting the first and second ends; a gate electrode extending in a second direction crossing the first direction and crossing the fin; a via through the fin and the gate electrode, the via between the first end and the second end and between the first side and the second side; a source region and a drain region formed at the first end and the second end of the fin, respectively; a conductive contact formed in the via, the conductive contact being electrically isolated from the fin and in electrical contact with the gate.

Description

Semiconductor device and manufacturing method thereof

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device and a manufacturing method thereof.

Background technique

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shorten, a series of effects that can be ignored in the MOSFET long-channel model become more and more significant, and even become the dominant factors affecting performance. This phenomenon is collectively referred to as short channel effect. The short channel effect is easy to deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio.

In order to control the short channel effect, a three-dimensional semiconductor device such as a fin field effect transistor (FinFET) is proposed. Compared with the planar MOSFET, the three-dimensional FinFET can better control the short channel effect. However, on the other hand, FinFETs have relatively larger parasitic resistance and parasitic capacitance than MOSFETs. As a result, the resistance-capacitance delay increases, and the AC performance of the device decreases.

Contents of the invention

The object of the present disclosure is at least partly to provide a semiconductor device and its manufacturing method, which can reduce the short channel effect, and can reduce the parasitic resistance and parasitic capacitance.

According to one aspect of the present invention, there is provided a semiconductor device, comprising: a fin extending along a first direction, the fin includes opposite first and second ends and an opposite end connecting the first and second ends a first side and a second side of the first direction; a gate electrode extending along a second direction intersecting the first direction and intersecting the fin; a through hole penetrating the fin and the gate electrode, the through hole being located between the first end and the second end and located between the first side and the second side; the source region and the drain region are respectively formed at the first end and the second end of the fin; the conductive contact part is formed in the through hole, and the conductive contact part is connected with the fin. The fins are electrically isolated and in electrical contact with the gate.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a fin on a substrate along a first direction, the fin including opposite first end portions and second end portions and connecting the first end portions and the opposite first side and second side of the second end; along the second direction intersecting with the first direction and intersecting with the fin, a gate electrode is formed; at the first end and the second end of the fin, respectively formed a source region and a drain region; through the gate electrode and the fin, a via hole is formed, the via hole is located between the first end portion and the second end portion, and is located between the first side surface and the second side surface; a dielectric side is formed in the via hole wall to cover the portion of the fin exposed in the through hole; and filling the through hole with a conductive material to form a conductive contact portion, and the conductive contact portion is in electrical contact with the gate electrode.

The semiconductor device according to the embodiments of the present disclosure can have the advantages of the three-dimensional FinFET structure and the planar MOSFET structure at the same time, that is, it can not only effectively control the short channel effect, but also reduce the parasitic resistance and parasitic capacitance.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

1-15 illustrate the manufacturing process of a semiconductor device according to an embodiment of the present invention.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

FIG. 15 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure, wherein FIG. 15( a ) is a perspective view, and FIG. 15( b ) is a cross-sectional view. As shown in FIG. 15, the semiconductor device may include fins (1002", 1002'"), gate electrodes (1007", 1008"), source and drain regions (1002"), and conductive contacts (1014).

Specifically, the fins (1002", 1002'") may extend along a first direction (in the example of FIG. 15(b), a direction perpendicular to the paper). The fin may include opposing first and second ends (in the example of FIG. 15 , two ends opposing each other along the first direction) and an opposing first end connecting the first and second ends. A side and a second side (in the example of FIG. 15, two vertical sides extending along the first direction). A source region and a drain region may be formed at the first end portion and the second end portion of the fin, respectively.

The gate electrodes ( 1007 ″, 1008 ″) may extend in a second direction (horizontal direction in the example of FIG. 15( b )) intersecting (eg, orthogonal to) the first direction and intersect the fins. The gate electrode may include a gate dielectric layer (1007") and a gate conductor layer (1008"). In the example shown in FIG. 15, the gate dielectric layer (1007″) is only formed on the first side and the second side of the fin. But the present disclosure is not limited thereto, and the gate dielectric layer can also be formed in other shapes. In FIG. 15 In the example shown, the portion of the fin that overlaps the gate electrode (1002'") acts as a channel region. Referring to FIG. 15(b), the channel region (1002'") is only a thin layer due to via holes (described below), so that the semiconductor device according to this embodiment can be used as a fully depleted device.

A conductive contact (1014) may be formed in the via through the fin and the gate electrode, the conductive contact being electrically isolated from the fin and in electrical contact with the gate. The through hole may be located between the first end and the second end, and between the first side and the second side. Referring to Fig. 15(b), due to the existence of the through hole, between the first end and the second end (that is, between the source region and the drain region), only left along the first side and the second side respectively Extended thin layer (1002'"). As mentioned above, this thin layer (1002'") acts as the channel region of the device. In the example shown in FIG. 15 , the via divides the gate electrode into two parts, and a conductive contact formed therein makes electrical contact with both parts of the gate electrode.

In order to enhance the electrical contact between the conductive contact and the gate electrode, the gate electrode may comprise a metal silicide (1011"). Similarly, the source and drain regions may also comprise a metal silicide (1011").

According to an embodiment of the present disclosure, the semiconductor device may further include a first spacer (1006') formed on the fin and extending along the first side and the second side. According to an example, in the process of manufacturing the semiconductor device, the thin layer (1002'") may be formed by transferring the shape of the first spacer (1006') to the underlying fin. In the In an example, the first spacer is only formed at a position corresponding to the channel region, that is, covered by the gate electrode, however, the present disclosure is not limited thereto.

In addition, the semiconductor device may further include a second spacer (1010). The second sidewall (1010) is formed on the side of the gate electrode extending along the second direction, and overlaps at least the first sidewall (1006'). In this manner, the first side wall (1006') and the second side wall (1010) may define the side walls of the through hole. Therefore, in the process of manufacturing the device, the first sidewall (1006') and the second sidewall (1010) can be used as masks to etch to obtain through holes.

In addition, the semiconductor device may further include a third spacer (1013) formed in the via hole to electrically isolate the conductive contact (1013) from the fin. As shown in Fig. 15(b), the third side wall (1013) covers at least the thin layer (1002'") in the vertical direction.

Features such as the thickness and material of each layer in the semiconductor device will be described below in conjunction with the description of the manufacturing process.

Hereinafter, an example manufacturing flow of a semiconductor device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, a semiconductor-on-insulator (SOI) substrate is provided. Here, FIG. 1(a) is a perspective view, and FIG. 1(b) is a cross-sectional view along line A-A' in FIG. 1(a). In each of the following figures, (b) is a sectional view along line A-A' in (a), but line A-A' is not shown for clarity. The SOI substrate may include a first semiconductor layer 1000 , an insulator layer 1001 on the first semiconductor layer 1000 and a second semiconductor layer 1002 on the insulator layer 1001 . For example, the first semiconductor layer 1000 and the second semiconductor layer 1002 may include bulk silicon, and the insulator layer 1001 is a buried oxide layer. Of course, the present disclosure is not limited to SOI substrates, and may also be other types of substrates such as bulk silicon substrates; the semiconductor material of the substrate is not limited to silicon, and may also be other suitable semiconductor materials such as SiGe. The thickness of the SOI substrate may be, for example, about 40 nm.

According to an embodiment of the present disclosure, fins may first be formed on a substrate. Specifically, on the SOI substrate, for example, a stop layer 1003, a sacrificial layer 1004, and a protection layer 1005 can be sequentially formed by deposition. For example, the stop layer 1003 may include oxide such as silicon oxide with a thickness of about 10 nm, the sacrificial layer 1004 may include amorphous silicon with a thickness of about 60 nm, and the protective layer 1005 may include a nitride such as silicon nitride with a thickness of about 30nm. It should be noted here that the materials of the stop layer 1003, the sacrificial layer 1004 and the protective layer 1005 can be selected according to the etching process, as long as they can provide appropriate etching selectivity in the corresponding etching process, and are not limited to the above materials.

Next, as shown in FIG. 2 , the sacrificial layer 1004 is patterned into a shape extending along the first direction (the direction perpendicular to the paper in FIG. 2( b )). Specifically, for example, the protective layer 1005 and the sacrificial layer 1004 may be etched by reactive ion etching (RIE), and the etching stops at the stop layer 1003 . The etched protective layer 1005' and the sacrificial layer 1004' roughly correspond to the shape of the fin to be formed, and the width thereof is, for example, about 40-200 nm. Here, it can be seen that the stop layer 1003 serves as an etch stop layer in this step. Therefore, the material of the stop layer 1003 can be selected such that it has etch selectivity relative to the material of the sacrificial layer 1004 . In addition, in the case that the material of the sacrificial layer 1004 (for example, amorphous silicon) is different from that of the second semiconductor layer 1002 (for example, SiGe), the stop layer 1003 can even be omitted.

Then, on the two sides of the patterned sacrificial layer 1004' (and the protective layer 1005') extending along the first direction, a first spacer 1006 is formed. For example, the first spacer 1006 can be formed by depositing a layer of nitride such as silicon nitride with a thickness of about 10-30 nm, and performing RIE on the deposited nitride. In this RIE process, the stop layer 1003 can also be used as an etch stop layer. For those skilled in the art, there are many ways to form such side walls 1006 . It should be pointed out here that although the first side wall 1006 is shown as extending along the first side and the second side in FIG. Side walls may also form.

Then, as shown in FIG. 3 , the second semiconductor layer 1002 is patterned by using the first spacer 1006 as a mask to form initial fins 1002 ′. Here, the second semiconductor layer 1002 can be patterned, for example, by RIE. The RIE may stop at the insulator layer 1001 . Here, it can be seen that the protective layer 1005' can protect the sacrificial layer 1004' (amorphous silicon) from being etched during the etching process of the second semiconductor layer 1002 (bulk silicon). In the case that the material of the sacrificial layer 1004 ′ (for example, amorphous silicon) is different from that of the second semiconductor layer 1002 (for example, SiGe), the protection layer 1005 can even be omitted.

After forming the initial fin 1002' as described above, a gate electrode may be formed along a second direction intersecting the first direction and intersecting the fin. Specifically, as shown in FIG. 4 , for example, a thin oxide layer 1007 may be formed on the first side and the second side of the fin by thermal oxidation. This thin oxide layer 1007 may then act as a gate dielectric layer. Subsequently, a gate conductor layer 1008 is formed on the substrate, eg by deposition. In order to facilitate etching, an auxiliary mask layer 1009 may also be formed on the gate conductor layer 1008 . For example, the gate conductor layer 1008 may include polysilicon, and its thickness is about 50-60 nm; the auxiliary mask layer 1009 may include oxide such as silicon oxide, and its thickness is about 20-30 nm.

Next, as shown in FIG. 5, the gate electrode is patterned. Here, FIG. 5(a) is a perspective view, and FIG. 5(c) is a cross-sectional view along line B-B' in FIG. 5(a). In the following figures, (c) is a sectional view along the line B-B' in (a), but for the sake of clarity, the line B-B' is not shown. Specifically, for example, the auxiliary mask layer 1009 is etched by RIE to form a shape corresponding to the gate electrode to be formed. Then, using the patterned auxiliary mask layer 1009' as a mask, the gate conductor layer 1008 is patterned to obtain a patterned gate conductor layer 1008'. Here, during the RIE process on the gate conductor layer 1008 (for example, polysilicon), selective etching is performed with respect to the oxide. Thus, the thin oxide layer 1007 (gate dielectric layer) is substantially unaffected.

In the example shown in FIGS. 4 and 5 , the gate dielectric layer includes oxide, and the gate conductor layer includes polysilicon. However, the present disclosure is not limited thereto. For example, the gate dielectric layer may include a high-K gate dielectric layer, such as HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, etc.; the gate conductor layer may include a metal gate conductor. In addition, a work function adjustment layer, such as TiN, TiAlN, TaN, TaAlN, etc., may also be included between the gate dielectric layer and the metal conductor. In this case, a gate dielectric layer, (work function adjustment layer) and metal gate conductor layer can be sequentially formed on the substrate and patterned to obtain a gate electrode. Of course, during the patterning process, the gate dielectric layer may not be etched, because the gate dielectric layer is insulating and will not affect device performance.

After the gate electrode is formed, the source region and the drain region of the device can be formed, for example, by means of ion implantation or the like. Specifically, as shown in FIG. 6 , source-drain ion implantation (shown by arrows in the figure) can be performed. In addition, in order to enhance device performance, before the source-drain ion implantation, halo implantation and extension implantation can also be performed. For example, in halo implantation, for N-type devices, B, BF ₂ or In ions can be implanted; for P-type devices, As or P ions can be implanted. In the extension region implantation, for N-type devices, As or P ions can be implanted; for P-type devices, B, BF ₂ or In ions can be implanted. In source-drain implantation, for P-type devices, P-type ions such as B can be implanted; for NMOS devices, N-type ions such as P can be implanted. Subsequently, the implanted ions can be activated by annealing, and thus form source and drain regions (and optionally halo and extension regions). In addition, the material of the sacrificial layer 1004' may be changed from amorphous silicon to polysilicon due to annealing.

After forming the source region and the drain region, as shown in FIG. 7 , the sacrificial layer 1004 ′, the first sidewall 1006 (and the protection layer 1005 ′) on the source region and the drain region can be removed. This removal can be performed by RIE, for example, to selectively etch the sacrificial layer 1004', the first spacer 1006 (and the protection layer 1005 ') to be realized.

It should be noted here that the order of operations shown in FIGS. 6 and 7 can be exchanged. For example, unnecessary portions of the sacrificial layer 1004 ′, the first sidewall 1006 (and the protection layer 1005 ′) may be removed first as shown in FIG. 7 , and then ion implantation and annealing are performed as shown in FIG. 6 . In addition, ion implantation may be performed first as shown in FIG. 6 , and then unnecessary parts of the sacrificial layer 1004 ′, first sidewall 1006 (and protection layer 1005 ′) are removed as shown in FIG. 7 , and finally annealing is performed.

In the case that the preliminary fins 1002 ′ formed along the first direction are shared by multiple devices, as shown in FIG. 8 , electrical isolation between devices can also be performed as required. Specifically, for example, a photoresist may be used to cover the device region to expose regions adjacent to other devices, and etching such as RIE may be performed to electrically isolate the device from adjacent devices. Due to etching, the preliminary fin 1002' becomes a separate fin 1002" of the device (in the example shown in FIG. dielectric layer 1007'). Of course, if the device is designed to be electrically connected to other devices, such inter-device electrical isolation operation may not be performed.

After forming the gate electrode and the source and drain regions as described above, via holes may be formed through the gate electrode and the fin. Specifically, for example, as shown in FIG. 9 , the second sidewall 1010 may be formed such that the second sidewall 1010 is formed on a side surface of the gate electrode extending along the second direction and overlaps at least the first sidewall. The second sidewall 1010 may include nitride such as silicon nitride, for example. As such, the first sidewall 1006' and the second sidewall 1010 may define the sidewalls of the via. It should be pointed out that, in the example shown in FIG. 9 , the second spacer 1010 is only formed on the side of the gate electrode. In fact, it is also possible to form side walls, for example, on the vertical end faces of the fins 1002".

In order to improve the electrical contact performance of the device, metal silicide can be formed on the gate electrode and/or the source and drain regions. Specifically, for example, the auxiliary mask 1009' on the gate electrode, the stop layer 1003" and the gate dielectric layer 1007' on the source and drain regions (in this example, both are oxides) can be removed by RIE, and then silicided by metal The process forms a metal silicide 1011 such as NiPtSi on the gate electrode and/or the source and drain regions. The metal silicide process itself is well known to those skilled in the art and will not be repeated here.

In order to facilitate the etching of via holes, a dielectric layer 1012 may be formed on the substrate as shown in FIG. 10 . The dielectric layer 1012 may include, for example, an oxide such as silicon oxide. Then, planarization such as chemical mechanical polishing (CMP) may be performed until the top of the sacrificial layer 1004″ is exposed (in the case of the protective layer 1005′, until the top of the protective layer 1005′ is exposed). In FIG. 10, for clarity For the sake of simplicity, the dielectric layer 1012 and the second spacer 1010 are both shown in dotted lines.

After the planarization process, as shown in FIG. 10, the gate conductor layer 1008", the top of the sacrificial layer 1004" (in this example, the top of the protective layer 1005') (and optional metal silicide 1011') are exposed on the outside.

Here, in order to enhance the electrical contact performance, as shown in FIG. 11 , metal silicide treatment may be performed on the exposed gate conductor layer 1008 ″ again to form a metal silicide 1011 ″ such as NiPtSi. The metal silicide 1011" can also function as an etch stop layer during the subsequent etching process of the via hole. It should be noted here that in FIG. 11(a), for the sake of clarity, the dielectric Layer 1012.

Subsequently, as shown in FIG. 12, the protective layer 1005' (eg, nitride) is selectively etched, eg, by RIE. During this process, a portion of the first sidewall 1006' (eg, nitride) may also be removed. Next, as shown in FIG. 13, the sacrificial layer 1004" (eg, polysilicon) is selectively etched, eg, by RIE, and the etching may stop at the stop layer 1003". During this etching process, due to the existence of the metal silicide 1011", the gate conductor layer 1008" will not be etched even though it contains polysilicon. Thereafter, the stop layer 1003" and the fin 1002" are further selectively etched, eg by RIE, which may stop at the insulator layer 1001, thereby forming a via hole through the gate electrode and the fin. It can be seen from FIG. 13 that due to the existence of the first sidewall 1006', a thin layer 1002'" of fins is left under it. The thin layer 1002'" can serve as a channel region of the device.

After the via holes are formed as described above, conductive contacts may be formed in the via holes by filling a conductive material such as metal. In order to electrically isolate the conductive contact portion from the fin, a third spacer 1013 may be formed in the cavity as shown in FIG. 14 . The third spacer 1013 may include, for example, a nitride such as silicon nitride, and at least cover the thin layer 1002'" in the vertical direction. Then, as shown in FIG. 15, a conductive material is filled in the via hole. Specifically, for example, TiN or Ti (not shown) is formed by physical vapor deposition (PVD), metal W is formed by chemical vapor deposition (CVD), and finally the conductive contact 1014 is obtained by planarization.

It can be seen that, according to an embodiment of the present disclosure, the gate contact 1014 is formed in a self-aligned manner.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present invention, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (21)

1. A semiconductor device, comprising: a fin extending in a first direction, the fin including opposing first and second ends and opposing first and second sides connecting the first and second ends; a gate electrode extending in a second direction intersecting the first direction and intersecting the fin; a through hole passing through the fin and the gate electrode, the through hole is located between the first end and the second end, and is located between the first side and the second side; a source region and a drain region are respectively formed at the first end portion and the second end portion of the fin; a conductive contact formed in the via, the conductive contact being electrically isolated from the fin and in electrical contact with the gate, Wherein, the semiconductor device is formed on a semiconductor-on-insulator (SOI) substrate, and the SOI substrate includes a first semiconductor layer, an insulator layer formed on the first semiconductor layer, and a second semiconductor layer formed on the insulator layer, wherein the fin is formed from the second semiconductor layer, and wherein the via penetrates the second semiconductor layer to terminate at the insulator layer. 2. The semiconductor device according to claim 1, wherein the gate electrode and source and drain regions comprise metal silicide. 3. The semiconductor device according to claim 1, wherein the via hole divides the gate electrode into two parts, and the conductive contact part is in electrical contact with both parts of the gate electrode. 4. The semiconductor device according to claim 1, wherein the gate electrode comprises a gate dielectric layer and a gate conductor layer formed on the first side and the second side of the fin. 5. The semiconductor device according to claim 4, wherein the gate dielectric layer is an oxide obtained by thermally oxidizing the first side and the second side of the fin. 6. The semiconductor device of claim 1, further comprising a first sidewall formed on the fin extending along the first side and the second side. 7. The semiconductor device according to claim 6, further comprising a second sidewall formed on a side surface of the gate electrode extending in the second direction and overlapping at least the first sidewall, Wherein, the first side wall and the second side wall define side walls of the through hole. 8. The semiconductor device according to claim 7, further comprising: a third spacer formed in the via hole, the conductive contact portion being electrically isolated from the fin by the third spacer. 9. A method of manufacturing a semiconductor device, comprising: On a semiconductor-on-insulator (SOI) substrate including a first semiconductor layer, an insulator layer formed on the first semiconductor layer, and a second semiconductor layer formed on the insulator layer, patterning is performed through the second semiconductor layer of the SOI substrate , forming a fin along a first direction, the fin includes opposite first and second ends and opposite first and second sides connecting the first and second ends; forming a gate electrode along a second direction intersecting the first direction and intersecting the fin; A source region and a drain region are respectively formed at the first end portion and the second end portion of the fin; penetrating through the gate electrode and the fin, forming a via hole between the first end and the second end, and between the first side and the second side, wherein the via penetrates through the second semiconductor layer to terminate in the insulator layer; forming a dielectric spacer in the via to cover the portion of the fin exposed in the via; and A conductive material is filled in the through hole to form a conductive contact portion, and the conductive contact portion is in electrical contact with the gate electrode. 10. The method of claim 9, wherein patterning the second semiconductor layer of the SOI substrate comprises: sequentially forming a stop layer, a sacrificial layer and a protective layer on the SOI substrate; patterning the protective layer and the sacrificial layer to form a shape extending along the first direction; forming first sidewalls on both sides of the patterned protective layer and the sacrificial layer extending along the first direction; and Patterning the second semiconductor layer of the SOI substrate by using the first sidewall as a mask to form fins. 11. The method of claim 9, wherein forming the fin along the first direction comprises: disposing a layer of fin material on the substrate; forming a sacrificial layer extending along a first direction on the fin material layer; forming first sidewalls on both sides of the sacrificial layer extending along the first direction; and Using the first side wall as a mask, the fin material layer is patterned to form fins. 12. The method of claim 11, wherein forming the gate electrode comprises: forming a gate dielectric layer on at least the first side and the second side of the fin; forming a gate conductor layer on the substrate; and Patterning the gate conductor layer or both the gate conductor layer and the gate dielectric layer to form a gate electrode. 13. The method of claim 11, wherein forming the source and drain regions comprises: performing source-drain ion implantation; and Anneal to activate the implanted ions. 14. The method according to claim 11, wherein, before source-drain ion implantation, further comprising: A halo implant and an extension implant are performed. 15. The method of claim 11, wherein forming the via comprises: forming a second sidewall such that the second sidewall is formed on a side surface of the gate electrode extending along the second direction and overlaps at least the first sidewall; forming a dielectric layer on the substrate and planarizing the dielectric layer to expose the top of the sacrificial layer; and The sacrificial layer and the fin material layer are selectively removed by using the first sidewall and the second sidewall as a mask to form the through hole. 16. The method according to claim 15, wherein after forming the second spacer and before forming the dielectric layer, the method further comprises: Metal silicide is formed on the gate conductor layer and/or the source/drain regions of the gate electrode. 17. The method of claim 10, wherein forming the gate electrode comprises: forming a gate dielectric layer on at least the first side and the second side of the fin; forming a gate conductor layer on the substrate; and Patterning the gate conductor layer or both the gate conductor layer and the gate dielectric layer to form a gate electrode. 18. The method according to claim 17, wherein forming the gate dielectric layer comprises: Thermal oxidation is performed on the first side and the second side of the fin to form a gate dielectric layer. 19. The method of claim 10, wherein forming the via comprises: forming a second sidewall such that the second sidewall is formed on a side surface of the gate electrode extending along the second direction and overlaps at least the first sidewall; forming a dielectric layer on the substrate and planarizing the dielectric layer to expose the protective layer; and Using the first side wall and the second side wall as a mask, selectively remove the protection layer, the sacrificial layer, the stop layer, and the second semiconductor layer to form the through hole. 20. The method according to claim 19, wherein after forming the second spacer and before forming the dielectric layer, the method further comprises: removing the portion of the stopper layer and the portion of the first spacer located in the source region and the drain region; Metal silicide is formed on the gate conductor layer of the gate electrode and the source and drain regions. 21. The method of claim 20, wherein, after planarization, the method further comprises: In the portion of the gate conductor layer exposed by the planarization, a metal silicide is formed.