CN103681840B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. According to an example, a semiconductor device may include: a semiconductor layer; a semiconductor base located on the semiconductor layer, the semiconductor base including a cavity extending through the semiconductor base; a source and a drain formed on the semiconductor layer and respectively connected to The gate is connected to the opposite first side and the second side of the semiconductor base; the gate is respectively connected to the opposite third side and the fourth side of the semiconductor base.

Description

Semiconductor device and manufacturing method thereof

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device and a manufacturing method thereof.

Background technique

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shorten, a series of effects that can be ignored in the MOSFET long-channel model become more and more significant, and even become the dominant factors affecting performance. This phenomenon is collectively referred to as short channel effect. The short channel effect is easy to deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio.

In order to control the short channel effect, a three-dimensional semiconductor device such as a fin field effect transistor (FinFET) is proposed. Compared with the planar MOSFET, the three-dimensional FinFET can better control the short channel effect. However, on the other hand, FinFETs have relatively larger parasitic resistance and parasitic capacitance than MOSFETs. As a result, the resistance-capacitance delay increases, and the AC performance of the device decreases. Additionally, stress engineering is relatively difficult in FinFETs compared to MOSFETs.

Contents of the invention

The purpose of the present disclosure is to provide a semiconductor device and its manufacturing method, which can reduce short channel effect, parasitic resistance and parasitic capacitance, and can also easily perform stress engineering.

According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor device, comprising: a semiconductor layer; a semiconductor substrate located on the semiconductor layer, the semiconductor substrate comprising a cavity extending through the semiconductor substrate; a source The electrode and the drain are formed on the semiconductor layer and are respectively connected to the opposite first and second sides of the semiconductor base; the gate is respectively connected to the opposite third and fourth sides of the semiconductor base.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a preliminary semiconductor base on a semiconductor layer, the preliminary semiconductor base including opposing first and second sides and an opposing third side and the fourth side; form a source and a drain on the semiconductor layer, and the source and drain are respectively connected to the first side and the second side of the prepared semiconductor base; form the third side and the fourth side of the prepared semiconductor base The side-connected gates; and forming a cavity penetrating through the prepared semiconductor body, so that the prepared semiconductor body constitutes the semiconductor body.

The semiconductor device according to the embodiment of the present disclosure can have the advantages of the three-dimensional FinFET structure and the planar MOSFET structure at the same time, that is, it can not only effectively control the short channel effect, but also reduce the parasitic resistance and parasitic capacitance, and can adjust the channel Region stress increases carrier mobility and improves device performance.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

1(a) and 1(b) are schematic top views and cross-sectional views after patterning a protective layer and a sacrificial layer in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein FIG. 1(b) is along the lines of FIG. 1 (a) The cross-sectional view of the A-A' line, in the following drawings for the sake of clarity, the A-A' line is no longer shown;

2(a) and 2(b) schematically show a top view and a cross-sectional view along line A-A' after forming a first spacer in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

3(a) and 3(b) are top views schematically illustrating the patterning of the stop layer, the semiconductor base material layer and the semiconductor layer using the first spacer as a mask in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure and a sectional view along the line A-A';

4(a) and 4(b) schematically illustrate a top view and a cross-sectional view along line A-A' after forming a gate stack in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

5(a), 5(b) and 5(c) schematically illustrate a top view, a cross-sectional view along the A-A' line and The cross-sectional view along the line B-B', for the sake of clarity in the following drawings, the line B-B' is no longer shown;

6(a), 6(b) and 6(c) schematically show a top view, a cross-sectional view along line A-A' and a cross-sectional view along line B-B after forming a second spacer in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure. sectional view of the line;

7(a), 7(b) and 7(c) schematically show a top view after exposing the semiconductor layer in the source and drain regions in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure, a cross-sectional view along line A-A' and A sectional view along the line B-B';

8 is a top view schematically illustrating a first ion implantation operation performed in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

9(a) and 9(b) are schematic top views and cross-sectional views along the line B-B' after another semiconductor layer is formed in the source and drain regions in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

10(a) and 10(b) schematically show a top view and a cross-sectional view along line B-B' after forming a first dielectric layer and performing planarization treatment in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

FIG. 11 is a top view schematically showing the formation of a gate in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

12(a), 12(b) and 12(c) are top views schematically showing the formation of a second dielectric layer and planarization in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure, along the line A-A' sectional views and sectional views along the line B-B';

13 is a schematic cross-sectional view along A-A' line after forming a cavity in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

14 is a cross-sectional view along line A-A' schematically illustrating a second ion implantation operation performed in a process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

15 is a cross-sectional view along A-A' line schematically showing a cavity filled with a dielectric material in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

16(a) and 16(b) schematically illustrate the process of removing the second dielectric layer and at least part of the first dielectric layer to expose the gate and source and drain along A-A in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure. ’ line and the sectional view along B-B’ line;

17(a), 17(b) and 17(c) are top views schematically showing the formation of metal silicide on the gate, source and drain in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure, along A-A' A cross-sectional view of the line and a cross-sectional view along the line B-B', Figure 17 (d) schematically shows a perspective view of the resulting semiconductor device; and

FIG. 18 is a perspective view schematically showing a semiconductor device according to an embodiment of the present disclosure.

detailed description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

FIG. 18 is a perspective view schematically showing a semiconductor device according to an embodiment of the present disclosure. As shown in FIG. 18, the semiconductor device may include a semiconductor layer 2002, a semiconductor body 2004, a source and a drain 2030, and a gate (2016, 2018, 2020).

The semiconductor layer 2002 may be a semiconductor layer provided on the substrate 2000 . Alternatively, the semiconductor layer 2002 can also be a semiconductor substrate. For example, the substrate 2000 may include a bulk Si substrate, and the semiconductor layer 2002 may include SiGe (eg, about 5-15 atomic percent Ge). In this case, the semiconductor layer 2002 can be formed on the substrate 2000 by epitaxial growth.

A semiconductor base 2004 is formed on the semiconductor layer 2002, and includes opposing first and second sides (in the example shown in FIG. 18 , opposing vertical sides S1 and S2) and opposing third and fourth sides ( In the example shown in Figure 18, opposite vertical sides S3 and S4). The semiconductor base 2004 may include different materials from the semiconductor layer 2002 and have etch selectivity between them. For example, in examples where semiconductor layer 2002 includes SiGe as described above, semiconductor body 2004 may include Si. In this case, the semiconductor base 2004 can be formed on the semiconductor layer 2002 by means of epitaxial growth.

In the semiconductor body 2004 a cavity may be formed, which cavity extends through the semiconductor body 2004 . According to an embodiment of the present disclosure, in order to reduce leakage current at the bottom of the channel region, the cavity may further extend into the semiconductor layer 2002 such that the bottom of the semiconductor base 2004 is at least partially separated from the semiconductor layer 2002 . In the cavity, a dielectric material 2036 may be filled. In this case, the bottom of semiconductor body 2004 may be electrically isolated from semiconductor layer 2002 by dielectric material 2036 .

The drain and the source 2030 are formed on the semiconductor layer 2002 and are respectively in contact with the first side S1 and the second side S2 of the semiconductor substrate 2004 . The source and drain 2030 may comprise a further semiconductor layer grown epitaxially on the semiconductor body 2004 . To enhance device performance, according to one embodiment of the present disclosure, the additional semiconductor layer may comprise a stressed semiconductor material. For example, for an n-type device, the stressed semiconductor material may include Si:C (e.g., about 0.2-2 atomic percent of C); for a p-type device, the stressed semiconductor material may include SiGe (for example, about an atomic percent of Ge about 15-75%). For an n-type device or a p-type device, the drain and source 2030 are doped to be n-type or p-type, respectively. Such doping can be achieved, for example, by in-situ doping during the epitaxial growth of the source and drain.

The gate is in contact with the third side S3 and the fourth side S4 of the semiconductor substrate 2004 respectively. In this way, a channel region can be formed in a portion of the semiconductor body 2004 adjacent to the gate. Specifically, channel regions may be formed at the third side S3 and the fourth side S4 of the semiconductor base 2004 . Due to the cavity, the channel region can be only a thin layer, so that the semiconductor device according to this embodiment can be used as a fully depleted device.

According to an embodiment of the present disclosure, an ultra-steep receding well may be formed at a portion of the semiconductor body 2004 used as a channel region. For n-type devices, the ultra-steep receding well can be p-type doped; for p-type devices, the ultra-steep receding well can be n-type doped.

The gate may include a gate dielectric layer 2016 and a gate conductor layer 2020 . For example, the gate dielectric layer 2016 may include silicon oxide, and the gate conductor layer 2020 may include polysilicon. Alternatively, the gate dielectric layer 2016 may include a high-K gate dielectric, such as HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, etc.; the gate conductor layer 2020 may include a metal gate conductor. In the latter case, the gate may further include a work function adjustment layer 2018 located between the gate dielectric layer 2016 and the gate conductor layer 2020, such as TiN, TiAlN, TaN, TaAlN and the like.

According to another embodiment of the present disclosure, an isolation layer (for example, oxide) may be included on the semiconductor layer 2002 , and the gate may be formed on the isolation layer, so that the gate is separated from the semiconductor layer 2002 by the isolation layer.

Hereinafter, an example manufacturing flow of a semiconductor device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, a semiconductor layer 1002 is provided. The semiconductor layer 1002 can be formed on the substrate 1000 by epitaxial growth. For example, the substrate 1000 may include a bulk Si substrate, and the semiconductor layer 1002 may include SiGe (Ge about 5-15 atomic percent). The thickness of the semiconductor layer 1002 is, for example, about 20-50 nm. It should be noted here that although Si and SiGe are described here as examples, the present disclosure is not limited thereto, and other semiconductor materials are also applicable.

According to an embodiment of the present disclosure, firstly, a preliminary semiconductor body may be formed on the semiconductor layer (the semiconductor body is made from the preliminary semiconductor body). Specifically, the semiconductor base material layer 1004 can be formed on the semiconductor layer 1002, for example, by epitaxial growth. The semiconductor base material layer 1004 may include Si, for example, with a thickness of about 50-100 nm. It should be pointed out here that the semiconductor base material layer is not limited to Si, and may also include other semiconductor materials, such as Ge.

Next, some patterning auxiliary layers may be formed on the semiconductor base material layer 1004, so as to pattern the semiconductor base material layer 1004 as a preliminary semiconductor base. Specifically, on the semiconductor base material layer 1004, for example, a stop layer 1006, a sacrificial layer 1008, and a protection layer 1010 can be sequentially formed by deposition. For example, the stop layer 1006 may include oxide such as silicon oxide with a thickness of about 5-20 nm; the sacrificial layer 1008 may include amorphous silicon with a thickness of about 30-80 nm; the protective layer 1010 may include nitride such as silicon nitride, Its thickness is about 20-50nm. It should be pointed out here that the materials of the stop layer 1006, the sacrificial layer 1008 and the protective layer 1010 can be selected according to the etching process, as long as they can provide appropriate etching selectivity in the corresponding etching process, and are not limited to the above materials.

The sacrificial layer 1008 and protective layer 1010 may be patterned into a shape corresponding to the active region of the device to be formed. Specifically, the protective layer 1010 and the sacrificial layer 1008 may be etched, for example, by reactive ion etching (RIE), and stop at the stop layer 1006 . Here, it can be seen that the stop layer 1006 serves as an etch stop layer in this step. Therefore, the material of the stop layer 1006 may be selected such that it has etch selectivity relative to the material of the sacrificial layer 1008 . In addition, in the case that the sacrificial layer 1008 (for example, amorphous silicon) and the semiconductor base material layer 1004 (for example, Ge) have etch selectivity, the stop layer 1006 can even be omitted.

Then, as shown in FIG. 2 , a first spacer 1012 is formed around the patterned sacrificial layer 1008 (and the protection layer 1010 ). For example, the first spacer 1012 can be formed by depositing a layer of nitride such as silicon nitride with a thickness of about 15-20 nm, and performing RIE on the deposited nitride. In this RIE process, the stop layer 1006 can also be utilized as an etch stop layer. For those skilled in the art, there are many ways to form such side walls 1012 .

Next, as shown in FIG. 3 , the semiconductor base material layer 1004 is patterned by using the first sidewall 1012 as a mask. Here, for example, the stop layer 1006 and the semiconductor base material layer 1004 may be sequentially patterned by RIE to obtain the patterned stop layer 1006' and the semiconductor base material layer 1004'. RIE to semiconductor base material layer 1004' (eg, Si) may stop at semiconductor layer 1002 (eg, SiGe).

Here, it can be seen that the protective layer 1010 can protect the sacrificial layer 1008 (amorphous silicon) from being etched during the etching process of the semiconductor base material layer 1004 (Si). In the case that the material of the sacrificial layer 1008 (for example, amorphous silicon) and the semiconductor base material layer 1004 (for example, Ge) has etch selectivity, the protection layer 1010 may even be omitted.

As will be described below, in the example shown in FIG. 3, both left and right sides of the semiconductor base material layer 1004' are used as channel regions. By making the materials of the semiconductor base material layer 1004 and the semiconductor layer 1002 different (with etching selectivity), the width of the channel (the vertical height of the semiconductor base material layer 1004' in FIG. 3 ) can be better controlled.

Here, the semiconductor layer 1002 may also be partially patterned. For example, RIE can be used to etch the semiconductor layer 1002 with a certain thickness. Through this partial patterning of the semiconductor layer 1002, the surface of the patterned semiconductor layer 1002' outside the active region can be lower than the bottom surface of the semiconductor base material layer 1004'. In this way, the gate formed subsequently on said surface of the semiconductor layer 1002' can cover the entire height of the semiconductor base material layer 1004'.

In order to form better electrical isolation between the subsequently formed gate and the semiconductor layer 1002 , an isolation layer 1014 such as oxide may be formed on the semiconductor layer 1002 . For example, a layer of high-density plasma (HDP) oxide such as silicon oxide can be deposited over the entire structure with a thin thickness on the vertical sidewalls of the structure and a thick thickness on the horizontal The HDP oxide is etched back. In this way, the isolation layer 1014 is left on the semiconductor layer 1002 . Of course, HDP oxide may also remain on the top of the passivation layer 1010 , which has no influence on subsequent processes, and is not shown in the figure for clarity.

Preferably, the top surface of the isolation layer 1014 is lower than the bottom surface of the semiconductor base material layer 1004'. In this way, the gate formed subsequently on the isolation layer 1014 can better cover the entire height of the semiconductor base material layer 1004'.

Through the above treatment, the semiconductor base material layer 1004' basically remains on the active region of the device. Next, the source region and the drain region of the device can be determined, and the part of the semiconductor base material layer 1004 ′ in the source region and the drain region is removed, so as to obtain a preliminary semiconductor base.

Here, in order to simplify the process, the operation of determining the source and drain regions can be combined with the formation of the gate stack (because the source and drain regions are located on both sides of the gate stack). Specifically, as shown in FIG. 4 , a gate stack is formed on the entire structure, and an auxiliary mask is used to pattern the gate stack so that the gate stack remains in a region corresponding to the gate, thereby exposing the source and drain regions. Specifically, for example, an interface oxide layer (not shown) with a thickness of about 0.2-0.7 nm can be formed by thermal oxidation, and then a high-K gate dielectric layer 1016 (for example, HfO ₂ ) with a thickness of about 2-3 nm is sequentially deposited, The work function adjusting layer 1018 (eg, TiN) is about 3-10 nm thick, and the gate conductor layer 1020 (eg, polysilicon) is about 50-100 nm thick. It should be pointed out here that the materials and thicknesses of the layers in the gate stack listed above are just examples, and the present disclosure is not limited thereto. In the case that the gate conductor layer 1020 is polysilicon, it can be doped as required, for example, in-situ doping is performed while depositing. Subsequently, a planarization process such as chemical mechanical polishing (CMP) may be performed on the gate stack until the protection layer 1010 is exposed. Next, an auxiliary mask layer ( 1022 , 1024 , 1026 ) is formed over the gate stack and protective layer 1010 . The auxiliary mask layer can be stacked dielectric layers with different materials. For example, when the material of the protective layer 1010 and the first spacer 1012 is silicon nitride, the auxiliary mask layer can be a silicon oxide layer (the first auxiliary film layer 1022, for example about 2-5 nm)-silicon nitride layer (second auxiliary film layer 1024, for example about 10-20 nm)-silicon oxide layer (third auxiliary film layer 1026, for example about 10-20 nm). Subsequently, the auxiliary mask layer is patterned into a shape corresponding to the gate to be formed, for example by RIE, and the gate stack is patterned by using the patterned auxiliary mask layer as a mask, for example by RIE. When patterning the gate stack, the gate dielectric layer 1016 may not be etched. In the example shown in FIG. 4, the gate dielectric layer 1016 is not patterned.

In this way, the portion of the semiconductor base material layer 1004' corresponding to the source and drain regions is not covered by the auxiliary mask layer. This part of the layer of semiconductor body material 1004' can then be removed and thus a preliminary semiconductor body is obtained. Specifically, as shown in FIG. 5 , for example, the gate dielectric layer 1016 (for example, HfO ₂ ) not covered by the auxiliary mask layer, the protective layer 1010 and the first sidewall (for example, nitride) can be sequentially removed by RIE, Sacrificial layer 100g. RIE may stop at stop layer 1006'. In this way, the portion of the semiconductor base material layer 1004' corresponding to the source and drain regions is exposed.

Here, in order to better define the source and drain in the subsequent steps of forming the source and drain, as shown in FIG. The side of the base material layer 1004 ′) forms the second sidewall 1028 . For example, the second spacer 1028 can be formed by depositing a layer of nitride such as silicon nitride with a thickness of about 7-20 nm, and performing RIE on the deposited nitride. The second sidewall 1028 defines a source region and a drain region (in the example of FIG. 6( a ), a region located on the upper and lower sides of the auxiliary mask layer and surrounded by the second sidewall).

Subsequently, as shown in FIG. 7 , for example, the exposed stop layer 1006 ′ and the semiconductor base material layer 1004 ′ can be sequentially removed by RIE, and the RIE can stop at the semiconductor layer 1002 ′. It can be seen that the semiconductor layer 1002' is exposed in the source and drain regions for subsequent formation of source and drain electrodes thereon. The remaining semiconductor base material layer 1004' constitutes a preliminary semiconductor base. In this example, during the RIE process on the stop layer 1006' (eg, silicon oxide), the third auxiliary film layer 1026 (eg, silicon oxide) in the auxiliary mask layer is also removed.

In order to enhance the performance of the device, as shown in FIG. 8, a first ion implantation operation may be performed along the direction facing the first side and the second side (the direction indicated by the arrow in the figure), so as to form an extension region in the prepared semiconductor substrate 1004' and halo regions to suppress short channel effects. For example, for an n-type device, n-type doping such as As or P ion doping can be performed; for a p-type device, p-type doping such as B, BF ₂ or In ion doping can be performed to form an extension region. In addition, for n-type devices, p-type implantation such as B, BF ₂ or In ion implantation can be performed; for p-type devices, n-type implantation such as As or P ion implantation can be performed, followed by spike annealing activation at 900-1100°C Impurities form source and drain halo regions. Compared with performing this ion implantation operation in the direction facing the third side and the fourth side in the prior art, it is more convenient for practical operation, and also helps to reduce the distance between semiconductor substrates of adjacent devices, reduce the occupied area, and further reduce the manufacturing cost. The specific process of the first ion implantation operation, such as implantation energy, implantation dose, implantation times and doped particles, etc., can be flexibly adjusted according to product design, and will not be repeated here.

Next, as shown in FIG. 9 , another semiconductor layer 1030 can be epitaxially grown in the source and drain regions defined by the second spacer to form the source and drain. Here, in order to enhance device performance, the epitaxially grown semiconductor layer 1030 may include a stressed semiconductor material. For example, for a p-type device, the semiconductor layer 1030 can include SiGe, and the atomic percentage of Ge can be between about 15%-75%; for an n-type device, the semiconductor layer 1030 can include Si:C, and the atomic percentage of C is about 0.2 %-2%. Preferably, in-situ doping can be performed on the semiconductor layer 1030 during the epitaxial growth. For example, for p-type devices, in-situ p-type ion doping, such as B, the doping dose can be 1×10 ¹⁹ /cm ³ -1×10 ²¹ /cm ³ ; for n-type devices, in-situ n-type For ion doping, such as P, the doping dose can be 1×10 ¹⁹ /cm ³ -1×10 ²¹ /cm ³ . The epitaxial source and drain stress material can place the channel region under stress. For example, in p-type devices, compressive stress can be generated, and in n-type devices, tensile stress can be generated. In this way, the stress in the channel region of the device can be adjusted, thereby further improving the mobility of carriers in the channel region.

What needs to be pointed out here is that the source and the drain can also remove the semiconductor base material layer 1004' after removing the stop layer 1006' located in the source and drain regions, but instead use the method of carrying out ionization into the semiconductor base material layer 1004'. Formed after the injection operation. In this case, the portion of the semiconductor base material layer 1004' located in the source and drain regions directly serves as the source and drain.

Next, gates and cavities can be formed. Specifically, first, as shown in FIG. 10 , a first dielectric layer 1032 such as oxide (for example, silicon oxide) is formed on the entire structure, and planarization treatment such as CMP is performed on it. The CMP stops at the second auxiliary mask layer 1024 (eg, silicon nitride) in the auxiliary mask layer. Then, as shown in FIG. 11 , the auxiliary mask layer on the top of the gate stack is removed to expose the gate stack, and the gate stack may be trimmed to form a gate. Specifically, for example, the second auxiliary film layer 1024 (for example, silicon nitride) and the first auxiliary film layer 1022 (for example, silicon oxide) can be removed by RIE, and part of the height of the gate stack can be removed to form the gate 1020′ . In the vertical direction, the gate 1020' is at least higher than the preliminary semiconductor base 1004' (for forming the channel region), which is beneficial to increase the effective area of the channel region in the device, thereby increasing the mobility of carriers in the channel region .

Next, as shown in FIG. 12 , a second dielectric layer 1034 (for example, silicon oxide) is formed and planarized such as CMP to expose the protection layer 1010 (for example, silicon nitride). The second dielectric layer 1034 can reduce damage to existing structures when the protection layer 1010 is removed to form a cavity. Then, as shown in FIG. 13 , using the second dielectric layer 1034 as a mask, the protection layer 1010 , the sacrificial layer 1008 , the stop layer 1006 ′ and the preliminary semiconductor base layer 1004 ′ are removed to form a cavity.

In fact, the side walls of the cavity 300 are defined by the first side wall 1012 and the second side wall 1028 . The opening exposed in the second dielectric layer 1034 (see FIG. 12( a )) corresponds to the area defined by the first sidewall 1012 and the second sidewall 1028 . Even if the second dielectric layer 1034 is not used, the cavity can be formed by using the first sidewall 1012 and the second sidewall 1028 as a mask.

After the cavity is formed, the semiconductor body 1004' is prepared to become the semiconductor body 1004".

Here, in order to reduce the current leakage at the bottom of the channel region, when forming the cavity, a part of the semiconductor layer 1002' can be further removed, so that the bottom of the semiconductor base 1004" is at least partially separated from the semiconductor layer 1002', and can even be completely separated. On, this situation is shown in Figure 12.

In addition, in order to enhance the performance of the device, as shown in FIG. 14, a second ion implantation operation (as shown by the arrow in the figure) can be performed into the cavity 300 to form a Ultrasteep receding well. For example, for n-type devices, p-type ultra-steep receding wells can be formed; for p-type devices, n-type ultra-steep receding wells can be formed. This ultra-steep receding well can thin the depletion layer and further Small short channel effect. The specific process of the second ion implantation operation, such as implantation energy, implantation dose, implantation times and doped particles, etc., can be flexibly adjusted according to product design, and will not be repeated here.

Optionally, as shown in FIG. 15 , a dielectric material 1036 may be filled in the cavity. For example, a thin layer of oxide (not shown) may be deposited first, followed by nitride, and etched back so that they remain within the cavity. So far, the fabrication of the semiconductor device according to this embodiment has been basically completed.

In order to improve the electrical contact performance of the device, metal silicide can be formed on the gate and/or the source and drain. For example, as shown in FIG. 16 , the second dielectric layer 1034 and at least a part of the first dielectric layer 1032 can be removed to expose the gate, source and drain. Then, as shown in FIG. 17 , a metal silicide 1038 such as NiPtSi is formed on the gate and/or the source and drain through a metal silicide process. The metal silicidation process itself is well known to those skilled in the art and will not be repeated here.

Fig. 17(d) shows a perspective view of a semiconductor device manufactured according to the above-mentioned flow. In FIG. 17( d ), for the sake of clarity, the first spacer, the second spacer and the remaining first dielectric layer are not shown.

According to another embodiment of the present invention, for example, the structure shown in FIG. 17 may be planarized to obtain a semiconductor device as shown in FIG. 18 . In addition, in the device shown in FIG. 18, the above-mentioned isolation layer was not formed.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present invention, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (19)

1. a kind of semiconductor devices, including：

Semiconductor layer；

Semiconductor substrate, on semiconductor layer, the semiconductor substrate includes extending through the cavity of the semiconductor substrate；

Source electrode and drain electrode, form and connect with semiconductor layer, and be connected to the relative of semiconductor substrate respectively on the semiconductor layer First side and second side, wherein the semiconductor layer is different from the material of the semiconductor substrate；

Grid, is connected to relative the 3rd side and the 4th side of semiconductor substrate respectively,

Wherein, during cavity also extends into semiconductor layer, cavity be included in the part of the subjacent of semiconductor substrate so that Semiconductor substrate is obtained to separate at least in part with semiconductor layer.

2. semiconductor devices according to claim 1, wherein, dielectric substance is filled with cavity.

3. semiconductor devices according to claim 1, also includes：Super steep retrogressing trap, is formed at semiconductor substrate and grid In adjacent part, wherein, for n-type device, super steep retrogressing trap adulterates for p-type；For p-type device, super steep retrogressing trap is N-shaped Doping.

4. semiconductor devices according to claim 1, wherein, source electrode and drain electrode are included in semiconductor layer Epitaxial growth Other semiconductor layer.

5. semiconductor devices according to claim 4, wherein, the other semiconductor layer of epitaxial growth includes that band stress is partly led Body material.

6. semiconductor devices according to claim 1, wherein, grid is separated by separation layer with semiconductor layer, wherein, every Bottom surface of the top surface of absciss layer less than semiconductor substrate.

7. semiconductor devices according to claim 1, wherein, semiconductor layer includes different materials from semiconductor substrate, And possess Etch selectivity each other.

8. semiconductor devices according to claim 1, wherein, outside part of the semiconductor layer below source electrode and drain electrode Bottom surface of the top surface of remainder less than semiconductor substrate.

9. it is a kind of manufacture semiconductor devices method, including：

The prepared semiconductor substrate connected with semiconductor layer is formed on the semiconductor layer, and the prepared semiconductor substrate includes relative First side and second side and relative the 3rd side and the 4th side, wherein the semiconductor layer and the preparation half The material of conductor matrix is different；

Source electrode and the drain electrode connected with semiconductor layer are formed on the semiconductor layer, and the source electrode and drain electrode are connected to preparation and partly lead respectively The first side and second side of body matrix；

Form the grid connected with the 3rd side and the 4th side of preparation semiconductor substrate；And

Formed through preparation semiconductor substrate and extend into the cavity in semiconductor layer, so that preparation semiconductor substrate constitutes half Conductor matrix,

Wherein, when cavity is formed, the part that semiconductor layer is located at the subjacent of preparation semiconductor substrate is eliminated so that Semiconductor substrate separates at least in part with semiconductor layer.

10. method according to claim 9, wherein, forming preparation semiconductor substrate includes：

Semiconductor matrix material layer, stop-layer, framed sacrifice layer and protective layer are formed on the semiconductor layer and around The sacrifice layer of composition and the first side wall of protective layer；

It is mask with the first side wall, stop-layer, semiconductor matrix material layer is patterned, and semiconductor layer is carried out partly Composition so that the remainder outside part below semiconductor layer after composition semiconductor matrix material layer after patterning Bottom surface of the top surface less than semiconductor matrix material layer；

It is determined that the region corresponding with source electrode and drain electrode, and remove cover first side wall in the region, protective layer, sacrifice layer, Stop-layer and semiconductor matrix material layer, expose semiconductor layer,

Wherein, the remainder of semiconductor matrix material layer turns into preparation semiconductor substrate.

11. methods according to claim 10, wherein,

It is determined that the operation in the region corresponding with source electrode and drain electrode includes：

The grid connected with the 3rd side and the 4th side of preparation semiconductor substrate are formed on the semiconductor layer to stack；

In the stacked on mask layer for forming composition of grid heap, the mask layer of the composition corresponds to the shape of grid；

Mask layer with composition is patterned as mask to grid stacking,

Removal covers the first side wall, protective layer, sacrifice layer, stop-layer and the semiconductor matrix material layer in the region, exposes half The operation of conductor layer includes：

Removal is not masked the first side wall, protective layer, the sacrifice layer of layer covering, until exposing stop-layer；

Around the grid stacking side of composition and the side of the semiconductor matrix material layer of composition, the second side wall is formed；And

Stop-layer and semiconductor matrix material layer that removal is exposed, expose semiconductor layer.

12. methods according to claim 11, wherein, source electrode and drain electrode are formed on the semiconductor layer to be included：

In the other semiconductor layer of the semiconductor layer Epitaxial growth for exposing.

13. methods according to claim 11, wherein, forming cavity includes：

It is mask with the first side wall and the second side wall, removal protective layer, sacrifice layer, stop-layer, preparation semiconductor substrate layer are gone forward side by side One step removes a part of semiconductor layer.

14. methods according to claim 9, also include：

Filling dielectric material in the cavities.

15. methods according to claim 12, wherein, before the other semiconductor layer of epitaxial growth, the method is also wrapped Include：Ion implanting is performed along towards the direction of first side and second side, to form halo region and extension area.

16. methods according to claim 9, wherein, after the formation of the cavity, the method also includes：

Ion implanting is carried out via cavity, to form super steep retrogressing trap in the semiconductor substrate part adjacent with grid.

17. methods according to claim 9, wherein, forming preparation semiconductor substrate includes：

Semiconductor matrix material layer, framed sacrifice layer and around framed sacrifice layer the are formed on the semiconductor layer One side wall；

It is mask with the first side wall, semiconductor substrate material layer is patterned, and partly composition is carried out to semiconductor layer, makes Remainder outside part below semiconductor layer after composition semiconductor matrix material layer after patterning top surface it is low In the bottom surface of semiconductor matrix material layer；

It is determined that the region corresponding with source electrode and drain electrode, and remove the first side wall, sacrifice layer and the semiconductor for covering the region Base material layer, exposes semiconductor layer,

Wherein, the remainder of semiconductor matrix material layer turns into preparation semiconductor substrate.

18. methods according to claim 17, wherein,

It is determined that the operation in the region corresponding with source electrode and drain electrode includes：

The grid connected with the 3rd side and the 4th side of preparation semiconductor substrate are formed on the semiconductor layer to stack；

In the stacked on mask layer for forming composition of grid heap, the mask layer of the composition corresponds to the shape of grid；

Mask layer with composition is patterned as mask to grid stacking,

Removal covers the first side wall, sacrifice layer and the semiconductor matrix material layer in the region, exposes the operation bag of semiconductor layer Include：

Removal is not masked the first side wall, the sacrifice layer of layer covering, until exposing semiconductor matrix material layer；

Around the grid stacking side of composition and the side of the semiconductor matrix material layer of composition, the second side wall is formed；And

The semiconductor matrix material layer that removal is exposed, exposes semiconductor layer.

19. method according to claim 11 or 18, wherein, before grid stacking is formed, the method also includes：Partly leading Separation layer is formed on body layer, wherein, the bottom surface of the top surface less than semiconductor matrix material layer of separation layer.