CN103296138A - Low-cost solar cells and methods for their production - Google Patents

Abstract

The present invention relates to low cost solar cells and methods of production thereof which do not require the gasification of metallurgical grade silicon to manufacture solar cells, thus avoiding the costs and health and environmental hazards involved in the manufacture of solar grade or silicon grade silicon. The method of producing solar cells comprises: obtaining a polycrystalline silicon wafer consisting essentially of metallurgical grade silicon doped p-type or n-type; texturing the front side of the wafer; directly on the front side of the wafer and with the wafer depositing an intrinsic layer in contact with the front side of the intrinsic layer; depositing a doped layer of opposite polarity to the wafer on and in contact with the intrinsic layer; forming a top conductive contact on the doped layer; and Bottom conductive contacts are formed on the bottom surface of the wafer.

Description

Low-cost solar cells and methods for their production

This application is a divisional application of the Chinese patent application with the filing date of the original application being November 7, 2008, the application number being 200880115434.9, and the invention title being "low-cost solar cell and its production method". related application

This application claims priority to US Provisional Application Serial No. 60/986,996, filed November 9, 2007, the disclosure of which is incorporated herein in its entirety.

technical field

The present invention relates to solar photovoltaic cells, and more particularly to methods of manufacturing low cost base materials for use in such cells and methods for manufacturing low cost cells and resulting cell device structures.

Background technique

Conventional energy generation from fossil fuels poses the greatest threat to the peace of the planet since the last ice age. Of all the alternative energy sources, solar photovoltaic cells are arguably the cleanest, ubiquitous and probably the most reliable option compared to other sources such as ethanol, hydropower and wind energy, in addition to energy savings. The principle is a simple solid-state p-n junction that converts light into a small DC voltage. Batteries can be stacked to charge a car battery or feed into the grid through DC/AC conversion. Among the various semiconductor materials that can be used for this purpose, silicon accounts for 99% of the production of photovoltaic solar cells. Compared to other compound semiconductor-based solar cells, despite its high conversion efficiency, especially in small-area cells, silicon is much more abundant in the Earth's crust and is weathered in all climates around the world. Hit roofs offer up to 30 years of proven reliability. Furthermore, large-scale commercial fabrication techniques utilizing silicon have been in use for decades and are well developed and well understood. Therefore, silicon is likely to remain the predominant basic material for solar cells.

However, despite three decades of development, silicon-based solar cells have yet to realize their potential for large-scale power generation. The main obstacle to its acceptance is the cost associated with manufacturing solar cells, especially the cost of the raw material, the base material (substrate) used to manufacture solar cells. The material accounts for more than half of the total cost of solar cell manufacturing, compared to only about 10% in the case of semiconductor microchips. Ironically, the price of silicon, the material used in solar cells, has actually risen in tandem with the price of oil because of huge demand and high production costs. For example, the cost per kg of polysilicon material used to produce solar silicon wafers has increased significantly over the past few years, and for thin-film solar cells, the cost of silane gas to deposit the film and _NF gas to clean the reactor after deposition The cost also increases. In contrast, semiconductor chip prices (ie, per unit of memory or logic function) have decreased exponentially over the past three decades in accordance with Moore's Law. This difference in learning curves may involve major differences in technology and the weighting of materials versus cost (compared to process and design for increasing device density per unit area).

According to the current state of the art, the production of solar cells based on polycrystalline silicon proceeds in three main stages. First, a relatively modest 25MW capacity plant produces large quantities of silicon wafers for substrates - typically millions of wafers per month. Second, these wafers are processed into solar cells by forming p-n junctions and metallizing them. Third, these chips are then "packaged" into modules for installation in the user's facility.

Ultra-high-purity polysilicon, usually referred to as nine nines, or 99.9999999% pure, is produced by thermally decomposing hazardous gases containing Si-H-Cl such as dichlorosilane and trichlorosilane, making the basic silicon wafers used in solar cells. These gases are extremely flammable and toxic. However, due to environmental and health hazards in the gasification of silicon, only a few factories are operating in the world, causing bottlenecks in the semiconductor and solar cell industries. Newly planned silicon gasification plants face resistance from local communities based on environmental and safety concerns. These plants also require significant capital investment and long construction periods. Therefore, there is always an imbalance between the demand and supply of bare silicon wafers.

Pure silicon (called polysilicon, after gasification and decomposition of silane-based compounds) is usually supplied in granular form suitable for semiconductor and solar cell applications. The pellets are then melted and the single crystal rods or polycrystalline ribbons are pulled using the seed crystals. Alternatively, the polysilicon is cast into pillars. The pulled cylinder is sawn, shaped and polished into 5-6 inch circular wafers which can then be cut into square wafers. Wet chemical etching is then performed in alkaline chemicals such as KOH to texture. Use POC1 ₃ furnace diffusion to form pn junction. The antireflective film passivation is then performed using PECVD SiON. Screen printed silver paste was applied to the n-type side and aluminum paste was applied to the p-type side. The paste is then sintered to form electrical contacts. Finally, the cells are tested and sorted according to their characteristics such as their IV curves.

The above process is well known in the industry and has been practiced for many years. However, while in semiconductors most of the cost (i.e., value) lies in the process of converting polished silicon wafers into functional integrated circuits, in solar cell manufacturing the process of converting polished wafers into functional solar cells is less expensive than The process of producing the polished wafer itself is low cost. That said, the process of turning silicon wafers into solar cells is not a high value-added step in the overall solar panel manufacturing chain in a commercial sense. So, in contrast to cell manufacturing technology - any improvement or reduction in the cost of making the initial wafer will enable a substantial reduction in the price of the final solar panel.

In order to overcome the problem of silicon feedstock for solar cells, there have been active efforts to reduce the amount of silicon consumed per watt by solar cells along two main avenues. these are:

1. Reduce wafer thickness from standard 500 μm to ~300 μm. This approach is limited by the strength of the wafer, which tends to crack during passage through the processing equipment at high speeds.

2. Using thin films of various solar cell materials such as silicon, CdTe, CuInGaSe, typically on glass and on other less expensive substrates. To allow light to impinge on the solar cell, one of the electrodes consists of a conductive transparent oxide (CTO) such as InSnO _x or ZnO ₂ .

Among various thin-film solar cell materials, silicon is also the most cost-effective material. In this solar structure, the wafer thickness is reduced from 300-500 μm to about 1-10 μm. Within this 1-10 μm, most of the deposited film thickness typically consists of an intrinsic amorphous layer of undoped Si-H polymer, abbreviated as ia-Si:H layer. This i aSi:H layer, sandwiched between doped n-type a-Si:H and p-type a-Si:H films, provides the volume needed to absorb incident sunlight, generating electron-hole pairs therein. These carriers then diffuse to the n- and p-electrodes of the solar cell to generate photovoltaic voltage and current for power generation. However, because the infrared wavelengths of the solar spectrum have a long transmission depth through silicon, a large amount of solar radiation is lost, reducing the efficiency of photovoltaic conversion. That is, the quantum efficiency of the conversion is lost, especially for longer wavelengths in the infrared range. Another inherent limitation of thin-film structures is that the minority carrier diffusion length is limited by the thickness of the film to much less than 10 μm. This is the figure of merit that predicts the efficiency of a finished solar cell. For pure crystalline silicon-based solar cells, the diffusion length is typically around 80 μm.

There are other fundamental limitations to thin-film solar cell construction that have so far limited thin-film solar cell production to about 5%, compared with silicon wafer-based solar cells, which account for more than 80% of the total solar panel market. Some of these limitations are as follows:

1. Due to the same reason as the price of polysilicon, that is, insufficient production of silane gas for depositing a-Si:H films, the cost of this highly flammable gas is rapidly rising. In addition to silane, plasma-enhanced CVD reactors for the production of solar thin films require large quantities of specialized _NF3 gases to perform in-situ plasma cleaning of PECVD reactors to ensure high production equipment uptime.

2. The photovoltaic conversion efficiency of thin-film silicon solar cells is low, sometimes less than half that of silicon wafer-based solar cells.

3. The capital equipment required to set up a thin film solar cell factory, typically at about $50M, is nearly 10 times that for a comparable energy output silicon wafer based solar cell factory. Base costs are mainly driven by vacuum-based plasma CVD reactors for deposition of a-Si:H and SiN passivation films, and vacuum-based PVD reactors for deposition of CTO films.

As can be understood from the above, the solar cell industry has been divided into two camps: the camp of silicon wafer-based solar cells that seek to utilize high-purity silicon wafers to obtain high cell efficiencies, and those that eschew the use of silicon wafers in order to reduce costs. film camp. Thus, the silicon wafer-based camp is limited by the availability of pure silicon wafers, while the thin-film camp is limited by conversion efficiencies mainly due to insufficient absorption of light in glass substrates, and by the production of thicker intrinsic hydrogenated silicon absorber layers The cost of the required SiH ₄ gas is constrained.

Contents of the invention

The following Summary of the Invention is included to provide a basic understanding and characterization of some aspects of the invention. This summary is not an extensive overview of the invention and as such it is not intended to particularly identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some principles of the invention in a simplified form as a prelude to the more detailed description that is presented below.

Various embodiments of the present invention provide methods for fabricating silicon substrates without the need for gasification of silicon. Thus, the costs and health and environmental hazards involved in manufacturing nine-nine-grade silicon are avoided. The substrate can be used to fabricate solar cells with efficiencies that match or exceed those of thin-film solar cells.

The features of the present invention solve one or more important problems faced by the solar cell industry as follows:

a) Availability and cost of "solar capable" silicon materials for wafers and thin films

b) Investment costs for solar cell factories

c) Cost per watt required for future solar cells.

d) Scalability for large volume production processes

e) Environmental adaptability and 25-year reliability

The features of the present invention make it possible to obtain a production-worthy solution to the above-mentioned problems, in particular by manufacturing solar cell structures investing in the conversion efficiency of bulk silicon wafers and the benefits of thin-film cell structures. According to aspects of the invention, solar cells are fabricated by utilizing silicon wafers made of very low cost metallurgical grade silicon as substrates and fabricating thin film solar cells on the substrates. According to a feature of the invention, the cell is fabricated by depositing a much thinner (eg 10%) film than conventional thin film solar cells. In addition to reducing the cost of substrate and membrane materials, the proposed structure allows for improved conversion efficiencies over conventional thin film solar cells. That is, by utilizing metallurgical grade silicon wafers, the manufacture of the substrate becomes less hazardous and more environmentally friendly, while also reducing the cost of the substrate. In addition, utilizing metallurgical-grade silicon wafers as substrates improves conversion efficiency compared to thin-film structures formed on glass.

Description of drawings

Other aspects and features of the present invention will become apparent from the detailed description with reference to the following drawings. It should be understood that the detailed description and drawings provide various non-limiting examples of various embodiments of the invention as defined by the appended claims.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain and illustrate the principles of the invention. The drawings are intended to illustrate features of the exemplary embodiments by way of illustration. The drawings are not intended to depict every feature of actual implementations or relative dimensions of the depicted elements, and are not drawn to scale.

Figure 1 is a flow diagram illustrating a process according to one embodiment of the present invention.

Figure 2 illustrates a process according to one embodiment of the invention.

Figure 3 illustrates a process according to another embodiment of the invention.

Figure 4 illustrates a process according to one embodiment of the invention.

Figure 5 illustrates another embodiment of the invention.

Figure 6 illustrates another embodiment of the present invention.

Figure 7 illustrates another embodiment of the present invention.

Figure 8 illustrates another embodiment of the invention which is similar to the embodiment of Figure 7 except that the dopants are reversed.

Figure 9A illustrates an embodiment of a process for fabricating a solar-cell ready substrate, generally referred to herein as SmartSi ^™ .

Figure 9B illustrates an embodiment of a process that may be used to convert SmartSi wafers to SmartSi PV solar cells.

Figure 10 illustrates a complete solar cell fabricated in accordance with an embodiment of the invention.

11A and 11B illustrate an embodiment of a multi-junction SmartSi solar cell.

12A and 12B illustrate an embodiment of a multi-junction SmartSi solar cell with diffused junctions.

13A and 13B illustrate an embodiment of a symmetrical configuration of a metallurgical silicon substrate sandwiched on both sides between i-Si/doped Si:H thin films.

Detailed ways

Embodiments of the present invention provide methods for low-cost fabrication of solar cells while reducing health and environmental hazards involved in conventional solar cell fabrication. As noted on the U.S. Department of Energy's Solar Energy website: "To be used as a semiconductor material in solar cells, silicon must be purified to a purity of 99.9999 percent." (Available at http://wwwl.eere.energy.gov/ available at solar/silicon.html ). This is commonly referred to as 6N or solar grade silicon, SoG Si. Contrary to conventional wisdom, the present invention provides a method for producing substrates and solar cells utilizing metallurgical grade silicon MG Si of purity 3N-5N. Various embodiments disclose combining the benefits of silicon-based solar cells and thin-film based solar cells to provide cells with conversion efficiencies of about 14%.

Figure 1 is a flow diagram illustrating a process according to one embodiment of the present invention. In FIG. 1 , the process begins at step 100 with the production of metallurgical silicon particulate feedstock by reducing quartz with graphite. The resulting purity level may be 99.9% or 99.999% pure, ie, about three nines to about five nines. Notably, quartz is readily and inexpensively available. In addition, the process omits the gasification step, thereby avoiding the hazardous process of gasification and silane production.

In a next step 200, the powder is melted into a 5 inch, 6 inch, 8 inch, etc. square or circular mold and the liquid is allowed to slowly solidify into cylinders with large silicon grains. Optionally, the solidified cylinder is remelted and then partially solidified to move impurities to one side of the cylinder. The cooling rate and temperature gradient are controlled horizontally during this process to move the impurities to the surface of the cylinder and vertically to concentrate them at the silicon grain boundaries. In step 200, the molten silicon is optionally doped with a small amount of boron to produce p-Si containing 1E17-1E18 cm ^-3 boron. Alternatively p-type single crystals can be pulled from the melt using the conventional Czochralsky process. In step 300, the surface of the solidified cylinder is machined to a polished state. In step 400, the cylinder is cut into approximately 20 mil, ie, 0.020 inch thick Si wafers using, for example, a diamond or wire saw, and the surface is then polished on one side while the other side is chemically etched to a smooth finish. Scrap can be collected for reuse in melting. Once solar cell fabrication is complete (full process described below), the wafer can be further thinned, if desired, so that the p-layer is about 0.007 inches.

Figure 2 illustrates a process according to one embodiment of the invention. The process starts with a wafer DSi 200 made of "dirty" silicon, ie metallurgical silicon of 3-5 nines, eg obtained by the process of the embodiment of FIG. 1 . Wafer 200 was exposed to POCl ₃ using a conventional furnace at about 900° C. to provide an n-layer on top of wafer 210 with a concentration of 1.0e16 atoms/cm ³ . A SiN layer 220 is then provided on the n-type layer 210 using a plasma chamber. Impurities are then extracted from the DSi layer 200 into the molten glass layer 230 using a _POC13 treatment at a temperature above 900°C. This improves the purity of the p-type layer 200, especially around previously formed junctions. However, the lift-off layer 230 is processed by etching after chemical mechanical polishing (CMP), for example. This removes layer 230 containing impurities extracted from layer 200 . Finally a silver contact 240 is provided on the n-doped layer 220 and an aluminum electrode 250 is provided on the layer 200 . The entire structure is then annealed at about 700° C. to make low-resistance ohmic contacts between the silver electrode to the n-type layer 210 and the aluminum electrode 250 to the p-type layer 200 .

Figure 3 illustrates a process according to another embodiment of the invention. The process begins at step 100 with the sublimation of a 2 μm thick layer of amorphous silicon from a crucible containing metallurgical silicon. This will be done at 1000-1200°C below the melting point of silicon with an Ar background vacuum of about 10E-6 Torr. This step identifies a purer active junction layer since any carbon and metal impurities do not sublime at 1200°C. In addition, the small amount of residual oxygen in the argon background environment helps to promote sublimation by forming a small amount of silicon monoxide on the crucible surface. In step 200, the wafer is exposed to a P-containing gas such as POCl ₃ or PBr ₃ in an atmosphere of O ₂ plus N ₂ or Ar. This step creates a pn junction by doping the n-type face and allowing B to outdiffuse from the "dirty" substrate into the clean sublimated silicon layer.

However in step 300 the backside of the wafer is etched or CMP (Chemical Mechanical Polishing) to remove any phosphorous doped glass. Next, in step 400, plasma is used to deposit a SiN anti-reflective coating on the front side (n-type) of the wafer. Contacts are formed in step 500, eg, a laser may be used to drill holes for the contacts. At step 600, conductive electrodes are fabricated, for example, a metal paste may be deposited on the front and back sides using a screen or other method to define the electrodes. The crystalline flakes are then fired at 600°C to 700°C to form contacts. In the case where the silver is deposited on the SiN anti-reflection film through a screen without any laser drilled contact holes through the layer, the higher temperature is used to allow the silver to penetrate the entire SiN layer.

Figure 4 illustrates a process according to one embodiment of the invention. The process starts with a dirty p-type silicon wafer 400 . An evaporated SiOx layer 410 is then produced on the wafer 400 using an evaporation process. An n-type layer 420 is provided on the SiOx layer 410 (this may be done by depositing a phosphorous doped Si layer or partially diffusing into this layer 410 by other acceptable methods). Layer 410 is then sealed with layer 430 , using gettering to draw impurities toward bottom 440 of wafer 400 to provide layer 400 with increased purity. The bottom 440 can then be removed prior to depositing the wires.

According to yet another embodiment, the dirty silicon wafer is first etched to provide texture on its top surface. The wafer was then processed in a POCl ₃ furnace to form the pn junction of the wafer. The top surface of the wafer was covered with a plasma deposited SiN layer. The wafer is then exposed again to POC1 ₃ to getter all metal impurities on the backside and harden the junction from leakage. The glass on the backside of the wafer is then removed by, for example, backside etching. Contact holes are then formed using, for example, laser drilling or contact etching. Metal contacts are then formed using conventional techniques. Otherwise, a screened silver paste is formed directly on the plasma deposited nitride layer and then annealed at ~700°C to diffuse the silver into the phosphorous doped layer near the top of the wafer without using any contact holes.

It is worth noting that once a metallurgical Si pn junction is formed, it is very easy to leak out due to metal impurities in the junction interface. One effect of _POCl3 is to form an n-layer that pulls impurities near the surface where the junction is formed. Therefore, in order to move metal impurities from the junction on the front side to the back side of the wafer, a second POC1 ₃ step is performed in this embodiment while protecting the active front side with SiN. The metal can be concentrated in the low temperature molten glass on the backside of the wafer and then removed by chemical etching or CMP.

Instead of a silicon substrate, one can use a substrate made of stainless steel or glass coated with sublimated Si and form a p-n junction in this substrate by diffusion from centrifugally cast B, P glass. This differs from amorphous PECVD silicon deposited for thin film transistor flat panel applications, as the sublimated film does not have any trapped hydrogen. Therefore, they do not decompose during the subsequent high temperature diffusion step. PECVD films fail over time, probably because of compositional changes related to H desorption.

Figure 5 illustrates another embodiment of the invention. The feedstock for the embodiment of FIG. 5 is low cost polycrystalline metallurgical silicon wafers of about four nines to five nines or 99.99% to 99.999% purity manufactured by casting followed by slow cooling. Metallurgical silicon is simply produced by the furnace-based chemical reaction of quartz (SiO ₂ ) and graphite (C), both found in mines around the world. These two materials are basically the purer forms of sand and coal. Graphite can be replaced with other petroleum by-products or organic plant matter containing pure C. Metallurgical silicon powder was melted and measured amounts of B were added to the melt as needed to produce a p-type dopant concentration of about 5E17 atoms*cm ⁻³ . The melt was cooled slowly to produce a cylindrical ingot of polycrystalline grains containing silicon with about 10 ppm of impurities such as Cr, Fe, Ni, Mn and C. The cooling process is adjusted so that the impurities are distributed in atomic clusters called precipitates. They tend to be less electroactive than the uniform distribution of atoms that typically occupy substituted electroactive sites on the silicon crystal lattice. The substituted impurities act as traps or centers for electron-hole recombination, which is believed to reduce the photovoltaic conversion efficiency of solar cells by reducing the diffusion length of carriers in the light-absorbing layer. The diffusion length can be estimated by the well-known physical method of measuring the quantum efficiency of the conversion of light to charge carriers as a function of the wavelength of the light. The cast material, the ingot, is machined into smaller cylinders, sawn into wafers, etched to remove surface damage, and then polished on one or both sides according to standard industry practice. The resulting metallurgical-grade wafers are used as substrates for the production of solar cells. Unlike the silicon substrates used for conventional polysilicon solar cells, this embodiment does not require the use of seven nines or higher purity polysilicon typically produced by reduction of gas _{phase SiHxCly} compounds.

）的本征、未掺杂的非晶Si:H层505，典型地低于。接下来，通过沉积n-掺杂的a-Si:H层510形成结的有源部件，这可以方便地在相同装置中进行，但利用含SiH₄和H₂以及PH₃的等离子。这随后是透明的导电氧化物520例如ZnO₂或InSnO以及如果需要由SiO_xN_y构成的抗反射膜515的连续层。这些形成顶电极，通过该电极能够将日光传输到硅吸收层本体。为了额外的电荷收集效率，可以在该透明的导电氧化物层520上形成典型地由银糊构成的一系列电极。对于电池结构背面的低电阻接触，通过PVD工艺沉积或丝网印刷含Al的糊在晶片的底面涂覆Al层525，然后烧结以形成低电阻接触。Substrate 500 is subjected to a pre _- deposition clean typically involving 100:1 HF to remove any native oxides, _NH4OH / _H2O2 to remove organic contaminants, and HCl to remove any metal impurities. _The extremely _thin (

), an intrinsic, undoped amorphous Si:H layer 505, typically lower than . Next, the active part of the junction is formed by depositing an n-doped a-Si:H layer 510, which can conveniently be done in the same setup, but with a plasma containing _SiH4 and _H2 and _PH3 . This is followed by a continuous layer of a transparent conducting oxide ₅₂₀ such as ZnO ₂ or InSnO and if desired an anti-reflection film 515 composed of _SiOxNy . These form the top electrode through which sunlight can be transmitted to the silicon absorber body. A series of electrodes, typically composed of silver paste, can be formed on the transparent conductive oxide layer 520 for additional charge collection efficiency. For low resistance contacts on the backside of the cell structure, an Al layer 525 is coated on the bottom side of the wafer by depositing or screen printing an Al-containing paste by PVD process and then sintered to form the low resistance contacts.

The solar cell thus obtained contains at least the following new features. The p-n is formed by depositing an n-layer of amorphous Si:H thin film on an absorber wafer made of p-type polycrystalline metallurgical grade silicon wafers that cost about ten times less than conventional silicon wafers made with solar or semiconductor grade polysilicon Knot. The 250-500 μm thick metallurgical p-type polysilicon light absorbing layer produced by casting metallurgical silicon powder containing B dopant replaces the much more expensive solar-grade polysilicon. An optional intrinsic (undoped) Si:H film interlayer is inserted between the p-type metallurgical substrate and the n-Si:H film to typically have fracture (hanging) due to the polycrystalline nature and impurities in the material. ) bond to the surface passivation of metallurgical silicon, thereby improving photovoltaic conversion efficiency. The ARC layer 515 can be omitted for cost savings and instead the surface of the metallurgical grade silicon is roughened by etching in KOH to expose the (111) planes in the generally (100) oriented grains. This roughening minimizes light reflection so that an ARC layer may be unnecessary.

Figure 6 illustrates another embodiment of the present invention. The embodiment of Fig. 6 is similar to Fig. 5 except that the doping is reversed. That is, absorber layer 600 is fabricated as n-type metallurgical silicon. The deposited amorphous layer 610 is of reverse polarity, ie p-type for the junction.

Figure 7 illustrates another embodiment of the present invention. The embodiment of FIG. 7 is similar to FIG. 5 . However, in the embodiment of FIG. 7, the optional structure consisting of a-i Si:H film 730 followed by a-n Si:H film 735 is fabricated before fabricating the backside-contacting aluminum layer 725 in order to take advantage of the heterojunction to increase the higher than absorption The conversion efficiency of the substrate, the heterojunction has an intrinsic passivation layer structure with a deposited very thin intrinsic Si-H layer, followed by a thin electrically active Si-H layer of opposite polarity. In this regard, for the embodiments described in FIGS. 5-8 , bracketed letters indicate the suggested order of fabrication for each illustrated layer. Figure 8 illustrates another embodiment of the invention which is similar to the embodiment of Figure 7 except that the dopants are reversed. That is, the substrate is designated as n-type metallurgical grade silicon, junction layer 810 is p-type, and layer 835 is n-type.

As can be appreciated, the embodiments of Figures 5-8 provide solar cells by building thin film junctions on metallurgical grade silicon substrates. Due to the properties of metallurgical silicon, this has the advantage of better light absorption compared to conventional thin-film cells with extremely thin absorber layers. Therefore, conversion efficiency is improved. On the other hand, the use of metallurgical silicon wafers offers lower cost than conventional solar or semiconductor grade silicon wafers. Furthermore, by using metallurgical grade silicon wafers as described herein, health and environmental hazards are reduced.

The intent of the embodiments referring to Figures 5-8 is to distinguish three functions associated with the PV process, which first absorbs light in silicon to generate electron-hole pairs, and then generates minority carriers by exploiting the bandgap of the p-n junction ( Electron) flow, which converts light into electric current. Usually, in polycrystalline or monocrystalline silicon with a diffused p-n junction structure, both processes occur simultaneously. The minority carrier diffusion length can vary from 50 μm to 100 μm to 300 μm when going from conventional polysilicon to Czochralsky single crystal silicon to zone fused single crystal silicon. The corresponding PV conversion efficiencies are about 18%, 22% and 25%. At the other end, deposited amorphous single-junction thin-film solar cells rely on an intermediate aSi:H layer typically about 1 μm thick as the absorber layer. The diffusion length is limited to about 1 μm by the thickness of the thin film layer. The corresponding PV conversion efficiency is reduced to about 6%. In this embodiment of the invention, the minority carrier diffusion length is not limited by the thin film, but is determined by the properties of the metallurgical silicon substrate.

Example 1

Three nines of metallurgical grade silicon was produced by induction melting two nines of silicon pellets in an approximately 1.5 m x 1.5 m graphite crucible, followed by slow cooling into a cylindrical shape over 24 hours. The carbon-rich surface shell is removed and the cylinders are crushed into grains or granules. The resulting material contains B and P, but is usually p-type with a resistivity in the range of 0.1-1 ohm·cm. The resulting material was then cast into approximately 0.5m x 1m ingots of metallurgical grade silicon with controlled cooling and dopant adjustment. A 6-inch core is machined from the ingot, the surface of the cylinder is flattened, and a 500 μm thick wafer is sawn from the cylinder to produce metallurgical-grade silicon wafers. One side is mechanically polished and both sides are lightly etched to reveal the polygonal large grain structure on the backside of the wafer. This yielded approximately 500 wafers of metallurgical-grade silicon of four-nine and five-nine purity. The wafers were divided into two groups using 4-point probe measurements, the main group having a resistivity of 0.3-0.5 ohm·cm and the remainder at ~1 ohm·cm. The SIMS composition profiles of the 4N and 5N materials are similar, with transition metal impurity concentrations of IE14 atoms cm ⁻³ . Metallic impurities are typically those associated with metallurgical silicon, ie Fe, Cr, Mn, Co, Ni, Cu. In addition, there is a carbon concentration of IE15 atom cm ⁻³ .

的In_xSn_yO_z，用作用于顶电极和底电极的透明导电氧化物。采用蚀刻设备蚀刻约10μm深的硅台地（silicon mesas）以产生与晶片其余部分隔离的二极管。利用该工艺，从0.1Ω·cm p-型(100)冶金级硅晶片开始，产生具有含扩散的p+背接触的本征钝化层结构的单异质结，并测量该结的二极管I-V和穿过该光谱范围的量子效率。利用1/QE对照λ波长的曲线，斜率按μm提供扩散长度L。长度L和I_Dsat是众所周知的PV转换效率的预测因子。该结构提供400mA的I_Dsat和80μm的长度L，对应于约20%的PV转换效率。在0.4Ω·cm p-型冶金级硅晶片上形成的结构也工作得很好，具有7μm的少数载流子（电子）扩散长度L_e，对应于12～13%的PV转换效率，假定结构具有良好控制的串联电阻。在1.0Ω·cm p-型冶金级硅晶片上形成的结构也工作得很好，具有8μm的少数载流子（电子）扩散长度L_e，对应于14%的PV转换效率，假定结构具有良好控制的串联电阻。A sample of the wafer is used to fabricate solar cells. Using rf plasma in SiH ₄ and H ₂ containing appropriate dopant gas PH ₃ and B ₂ H ₆ , use PECVD (plasma enhanced chemical vapor deposition) equipment to deposit i-type a-Si:H film, p-type a- Si:H and n-type a-Si:H films. Using PVD (Plasma Vapor Deposition) sputtering equipment to deposit about

In _{x Sny} O _z , used as the transparent conductive oxide for the top and bottom electrodes. Silicon mesas are etched approximately 10 μm deep using an etch tool to create diodes isolated from the rest of the wafer. Using this process, starting from a 0.1 Ω cm p-type (100) metallurgical grade silicon wafer, a single heterojunction with an intrinsic passivation layer structure with a diffused p+ back contact was produced and the diode IV and Quantum efficiency across this spectral range. Using a plot of 1/QE versus lambda wavelength, the slope provides the diffusion length L in μm. The lengths L and I _Dsat are well known predictors of PV conversion efficiency. This structure provides an I _Dsat of 400 mA and a length L of 80 μm, corresponding to a PV conversion efficiency of about 20%. Structures formed on 0.4Ω·cm p-type metallurgical grade silicon wafers also work well, with a minority carrier (electron) diffusion length L _e of 7 μm, corresponding to a PV conversion efficiency of 12-13%, assuming the structure with well-controlled series resistance. The structure formed on a 1.0 Ω cm p-type metallurgical grade silicon wafer also works well, with a minority carrier (electron) diffusion length L _e of 8 μm, corresponding to a PV conversion efficiency of 14%, assuming the structure has a good controlled series resistance.

Example 2

Formation of intrinsic passivation layers on low-cost metallurgical-grade substrates by depositing nanoscale Si:H film stacks on the front, “device” side and oppositely doped a-Si:H films on the back, “contact” side Single heterojunction for device structures. Metallurgical grade substrates do not have to specifically thin the substrate from 500 μm to 250 μm as is done for crystalline Si substrates, eliminating losses. Thicker wafers provide more robust handling in automated production lines. The material also avoids the cost, cycle, and complexity of polysilicon-based gasification, solidification, melting, and pulling processes, as it passes just outside the metallurgical-grade substrate face passivated by nanoscale intrinsic a-Si:H films thin Si:H films to create the active device.

Metallurgical grade substrates can be formed in standard sizes such as 6 inches, 8 inches, and 12 inches, and can be processed in standard semiconductor PECVD processing equipment. In contrast, conventional thin-film based solar cells are produced on large areas (typically, 4×6ft or 6×7ft) of glass, which requires specialized chambers with large internal volumes, making it difficult to pump low pressures and resulting in Layers of reactive gas are wasted. Consequently, these PECVD reactors are expensive to purchase and expensive to operate due to the high cost of consumables (ie, spent reactive gases). The high internal volume of these specialized chambers also creates depreciation difficulties and costs. Conversely, thin film formation on standard sized wafers can be performed in standard reactors with small internal volumes so that handling and depreciation problems are minimized. Due to the order of magnitude longer minority carrier diffusion lengths in metallurgical silicon substrates, the resulting thin film device structures on metallurgical silicon substrates have PV efficiencies approximately twice greater than conventional thin film solar cells.

Example 3

Figure 9A illustrates one embodiment of a process for fabricating a prepared solar cell substrate, generally referred to herein as SmartSi ^™ . In step 900, metallurgical grade quartz is melted and reduced in an electrolytic cell containing graphite electrodes, then allowed to cool and solidify to provide a metallurgical silicon ingot of about two nines. The ingot is broken into pellets, treated in chemicals to leach surface impurities, and cast into ingots. The ingot is then peeled off and broken into metallurgical silicon blocks of three to four nines. The resulting blocks are sorted according to their resistivity.

In step 915 the sorted MG silicon ingots are cast. The melt is solidified into an ingot, processed in step 920, sliced into wafers, and the wafers are polished. In step 925, a PECVD chamber is used to form an intrinsic amorphous silicon thin layer i-a-Si:H to passivate the surface of the MG-Si substrate. In step 930, an n-type layer n-a-Si:H is formed on the passivation layer using a PECVD chamber. At this point, the "SmartSi" wafer 935 has been produced, enabling the virtually formation of a PV solar cell industry anywhere in the world with little investment, a small amount of simple machinery and very little technical knowledge. That is, as can be understood, all that is needed in order to convert a SmartSi wafer into a solar cell is to make front and back contacts, and perhaps anti-reflective and protective layers. This can be easily done using existing screen printing or printing techniques. Furthermore, as indicated by the callout, another step 930' of PECVD can be performed to form a p-type later 935' on the backside of the substrate in order to improve access to subsequent conductive layers.

Figure 9B illustrates one embodiment of a process that can be used to convert SmartSi wafers to SmartSi PV solar cells. As mentioned above, all that is required is to form contacts in the back and front sides of the SmartSi substrate. As for the front side, a conventional method is to form a conductive metal grid. The usual approach is to design a grid with many thin conductive contacts scattered to every part of the battery's surface. The mesh's contacts must be wide enough to conduct electricity well (with low resistance), but narrow enough not to block much of the incoming light. This mesh maintains low resistive losses while shading only about 3 to 5 percent of the cell's surface. The top grid can be made of eg aluminum, silver or molybdenum metal by depositing metal vapors through a mask on the cell, painting them on the cell by screen printing, or by photolithography which offers the highest performance but the highest cost.

An alternative to the metal grid contact is a transparent conductive oxide (TCO) layer such as tin oxide (SnO ₂ ) or indium tin oxide, commonly known as ITO. The advantage of TCOs is that they are nearly invisible to incident light, and they form a good bridge from the semiconductor material to the external circuitry. The embodiment shown in Figure 9B utilizes a TCO as the contact to the front side of the cell. In step 940, a TCO layer is formed using a CVD process. The front side contacts are metallized in step 945 with, for example, trace traced metal paste on the front side using screen, printing or the like. In step 950, the backside contact is metallized using, for example, a metal paste (eg, silver paste) drawn on the backside using screen, printing, etc., or by sputtering aluminum or other metal on the backside of the substrate to form a collector. When metallizing the front contacts with paste, as shown in step 955, it is desirable to sinter the wafer in order to form good ohmic contacts. In step 960, the wafers are cut into the desired shape, for example, if round wafers are being processed, they may be cut into squares at this step. The wafers are then sorted according to conversion efficiency to produce SmartSi PV cells 970 .

In all of the embodiments described above, one or both faces of the MG Si substrate may be textured by, for example, etching in an alkaline solution such as potassium hydroxide solution, before any layers are formed. The substrate can then be rinsed and dried, for example by heating the substrate. In addition, a plasma discharge of hydrogen can be used to reduce the amount of carbon on the substrate surface. The intrinsic amorphous silicon thin film layer can be formed using silane gas (SiH ₄ ) mixed with hydrogen gas (H ₂ ) in a PECVD chamber. A thin n-type amorphous silicon layer can be formed using silane, hydrogen and phosphine gas (PH ₃ ) in a PECVD chamber. A thin layer of p-type amorphous silicon can be formed using silane, hydrogen, and boroethane gas (B ₂ H ₆ ) in a PECVD chamber.

Figure 10 illustrates a complete solar cell fabricated in accordance with an embodiment of the invention. The solar cell is formed on a metallurgical grade silicon substrate 1000, which in this example is doped p-type. An intrinsic amorphous silicon layer 1005 is then formed on the top surface, followed by an n-type amorphous silicon layer 1010 . A TCO layer 1020 is formed on the n-type layer, and a contact such as a silver contact 1025 is formed on the TCO to form a good ohmic contact. The back contact can be formed with, for example, aluminum. At this point the cell was complete and ready for use; however, to protect it from the elements, the following further processing was performed. The front side is protected by an optional resin film layer 1015 , such as ethylene vinyl acetate, followed by glass 1045 . The backside can also be protected with a resin film 1035 followed by a glass or other protective layer 1040 .

As shown in Figures 9A and 9B, the embodiments discussed above can be used to fabricate SmartSi wafers, which can be further processed to fabricate SmartSi solar cells. According to another aspect of the present invention, in order to improve the photovoltaic conversion efficiency, the SmartSi solar cell can be further processed to manufacture a multi-junction SmartSi solar cell with multiple bandgaps. One embodiment of a multi-junction SmartSi solar cell is illustrated in FIG. 11A . In FIG. 11A , the metallurgical grade silicon substrate 1100 is doped p-type. The top surface of the p-type substrate is passivated by a thin layer 1105 of intrinsic amorphous silicon with hydrogen atoms dispersed therein occupying silicon dangling bonds. This is sometimes called silicon hydride. As shown in the SmartSi solar cell embodiment above, a thin layer 1110 of n-type amorphous hydrogenated silicon is formed on the intrinsic layer 1105 to form a first p-i-n junction. Intrinsic and n-type layers 1105 and 1110 are relatively much thinner than the thin-film layers of typical conventional thin-film solar cells. In this embodiment, the first thin-film structure does not absorb light.

In order to improve the conversion efficiency of SmartSi solar cells, a conventional thin-film solar cell p-i-n structure is now formed on top of SmartSi solar cells. First, a thin p-type amorphous hydrogenated silicon layer 1120 is formed on the SmartSi solar cell. A thin-film intrinsic amorphous hydrogenated silicon layer 1125 is then formed on the p-type layer 1120 and a thin-film n-type amorphous hydrogenated silicon layer 1130 is formed on the intrinsic layer 1125 . The intrinsic layer 1125 acts as another light absorber and generates electron-hole pairs, thereby converting light into electrical energy. In order to collect electrical energy, a top transparent electrode ITO 1135 is formed on the n-type layer 1130 , and then a metal contact 1140 is formed on the ITO 1135 . Here the metal contact 1140 is made of silver, for example using a silver paste, and the structure is then sintered to form a good ohmic contact. In addition, a metal electrode 1145 is formed on the bottom of the substrate 1100 . Here the contact 1145 is made of aluminum. Figure 1 IB illustrates a similar multi-junction structure, except that the polarity of the layers is reversed.

12A and 12B illustrate an embodiment of a multi-junction SmartSi solar cell with diffused junctions. The embodiments of Figures 12A and 12B are essentially the same except that the polarity of the layers is reversed. Therefore, only one of them, the embodiment of Fig. 12A, will be described. In Fig. 12A, a metallurgical silicon substrate 1200 is fabricated according to an embodiment as described above, and is doped n-type. Then, the top layer of the substrate is diffused to form a p-type diffusion layer 1260 . This forms a p-n junction in the metallurgical silicon substrate and provides the conversion region of the solar cell, similar to standard silicon-based solar cells. A thin passivation layer 1205 of intrinsic amorphous hydrogenated silicon is then formed on the diffused p-type layer. An n-type amorphous hydrogenated silicon layer 1215 is formed on this intrinsic layer 1205 such that layers 1215, 1205 and 1260 form a p-i-n junction with a different bandgap than the p-n junction in substrate 1200 and thus absorb light at a different frequency. A conventional thin film p-i-n junction is then formed on layer 1215 by forming p-type amorphous hydrogenated silicon layer 1220 , intrinsic amorphous hydrogenated silicon layer 1225 and n-type amorphous hydrogenated silicon layer 1230 . In this structure, when the intrinsic layer 1225 functions as a light absorber, it has a thickness much higher than that of the intrinsic layer 1205 . In addition, this thin-film p-i-n structure has a different bandgap than the underlying structure and thus absorbs light at a different frequency. Thus, by carefully choosing the thickness of the layers, one can "tune" the structure to absorb light over a broad frequency range.

13A and 13B illustrate an embodiment of a symmetrical configuration of a metallurgical silicon substrate sandwiched on both sides between intrinsic Si/doped Si:H thin films. Figures 13A and 13B are antipodes of each other, except that the polarity of the layers is reversed. Therefore only FIG. 13A is explained. In FIG. 13A, a p-type metallurgical silicon substrate 700 has an upper intrinsic layer 705 and a lower intrinsic layer 730 that act as passivation layers rather than absorbers. A thin layer 710 of n-type amorphous hydrogenated silicon is then formed on the intrinsic layer 705 and another n-type layer 735 is formed on the intrinsic layer 730 . Contacts 720 and 725 are then formed as described with respect to the other embodiments.

It should be understood that the processes and techniques described herein are not inherently related to any device, and may be implemented by any suitable combination of components. In addition, various types of general-purpose devices may be employed in accordance with the teachings described herein. It may also prove advantageous to construct dedicated apparatus for carrying out the method steps described herein. The present invention has been described with respect to specific embodiments, which are intended in all respects to be illustrative and not restrictive. Those skilled in the art will appreciate that many different combinations of hardware, software, and firmware will be suitable for implementing the invention.

The invention has been described with respect to particular embodiments, which are intended in all respects to be illustrative and not restrictive. Those skilled in the art will appreciate that many different combinations of hardware, software, and firmware will be suitable for implementing the invention. Furthermore, other implementations of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered exemplary only, with a true scope and spirit of the invention indicated by the following claims.

Claims (20)

1. A method of manufacturing a solar cell, comprising: obtaining polysilicon wafers consisting essentially of metallurgical grade silicon doped p-type or n-type; texturing the front side of the wafer; depositing an intrinsic layer directly on and in contact with the front side of the wafer; depositing a doped layer of opposite polarity to the wafer on and in contact with the intrinsic layer; forming a top conductive contact on the doped layer; and Bottom conductive contacts are formed on the bottom surface of the wafer. 2. The method of claim 1, wherein at least one of forming the intrinsic layer and forming the doped layer comprises forming an amorphous layer. 3. The method of claim 1, wherein at least one of forming the intrinsic layer and forming the doped layer comprises forming a hydrogenated layer. 4. The method according to claim 1, wherein forming a bottom conductive contact comprises forming a doped conductive layer having the same polarity as the wafer on the bottom surface of the wafer and forming a metal layer on the doped conductive layer . 5. The method of claim 1, wherein forming a top conductive contact comprises forming a transparent conductor on the doped layer. 6. The method of claim 4, further comprising forming an amorphous intrinsic layer between the bottom surface of the wafer and the doped conductive layer. 7. The method of claim 4, wherein forming the metal layer comprises sputtering an aluminum layer. 8. The method of claim 1, wherein the wafer is p-type and the doped layer is n-type. 9. The method of claim 8, wherein forming the transparent conductor comprises forming an indium tin oxide (ITO) layer. 10. The method of claim 9, further comprising fabricating a top electrode on the ITO. 11. The method of claim 10, wherein fabricating the top electrode comprises screen printing silver paste. 12. The method of claim 1, wherein texturing the front side comprises etching the front side. 13. The method of claim 1, wherein the wafer is p-type and has a resistivity of 0.1-1 ohm·cm. 14. The method of claim 1, wherein forming the intrinsic layer comprises processing the wafer in a plasma enhanced chemical vapor deposition (PECVD) chamber and using silane gas (SiH ₄ ) mixed with hydrogen gas (H ₂ ) to maintain the plasma. 15. The method of claim 1, wherein forming a doped layer comprises processing the wafer in a plasma enhanced chemical vapor deposition (PECVD) chamber and maintaining a plasma using silane, hydrogen, and phosphine gases. 16. The method of claim 4, wherein forming the doped conductive layer comprises processing the wafer in a plasma enhanced chemical vapor deposition (PECVD) chamber and maintaining a plasma using silane, hydrogen and diborane gases. 17. The method of claim 1, wherein: forming the intrinsic layer includes forming an amorphous, hydrogenated intrinsic layer; forming the doped layer includes forming an amorphous, hydrogenated n-type layer; forming a bottom conductive contact includes forming a p-type layer on the bottom surface of the wafer and forming a metal layer on the doped conductive layer; and Forming the top conductive contact includes forming a transparent conductor layer on the doped layer and forming a top electrode on the transparent conductor layer. 18. The method of claim 17, wherein fabricating the top electrode comprises screen printing silver paste. 19. The method of claim 17, wherein forming the metal layer comprises sputtering an aluminum layer. 20. The method of claim 17, wherein texturing the front side comprises etching the front side.

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