CN103280439B - Ultrathin high-density multilayer circuit flip-chip encapsulation structure and manufacture method - Google Patents
Ultrathin high-density multilayer circuit flip-chip encapsulation structure and manufacture method Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 40
- 238000005538 encapsulation Methods 0.000 title claims description 7
- 239000002184 metal Substances 0.000 claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052802 copper Inorganic materials 0.000 claims abstract description 40
- 239000010949 copper Substances 0.000 claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 claims abstract description 23
- 239000004033 plastic Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 179
- 229920002120 photoresistant polymer Polymers 0.000 claims description 83
- 239000011810 insulating material Substances 0.000 claims description 35
- 238000009713 electroplating Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 17
- 238000007747 plating Methods 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 239000012044 organic layer Substances 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910021578 Iron(III) chloride Inorganic materials 0.000 claims description 3
- PQJKKINZCUWVKL-UHFFFAOYSA-N [Ni].[Cu].[Ag] Chemical compound [Ni].[Cu].[Ag] PQJKKINZCUWVKL-UHFFFAOYSA-N 0.000 claims description 3
- ZBTDWLVGWJNPQM-UHFFFAOYSA-N [Ni].[Cu].[Au] Chemical compound [Ni].[Cu].[Au] ZBTDWLVGWJNPQM-UHFFFAOYSA-N 0.000 claims description 3
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229910052742 iron Inorganic materials 0.000 claims description 3
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 claims description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 claims description 3
- KFZAUHNPPZCSCR-UHFFFAOYSA-N iron zinc Chemical compound [Fe].[Zn] KFZAUHNPPZCSCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000047 product Substances 0.000 claims description 3
- 239000011265 semifinished product Substances 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 238000003466 welding Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000012858 packaging process Methods 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000008393 encapsulating agent Substances 0.000 abstract description 2
- 239000003365 glass fiber Substances 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 238000005553 drilling Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 238000003912 environmental pollution Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000005187 foaming Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229940126214 compound 3 Drugs 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
本发明涉及一种超薄高密度多层线路芯片倒装封装结构及制作方法，所述结构包括一层线路层（9）、芯片（2）和二层线路层（1），所述二层线路层（1）正面设置有内引脚（8），所述芯片（2）倒装于内引脚（8）上，所述芯片（2）与二层线路层（1）外围包封有塑封料（3），所述二层线路层（1）与一层线路层（9）之间通过铜柱层（4）相连接，所述一层线路层（9）背面设置有外引脚（6），所述外引脚（6）背面设置有金属球（7）。本发明的有益效果是：降低了芯片封装载板的厚度，实现超薄高密度封装；可靠性的等级提高；真正地做到高密度线路的技术能力；可彻底解决传统基板在封装工艺中的翘曲问题。
The invention relates to an ultra-thin high-density multi-layer circuit chip flip-chip packaging structure and a manufacturing method, the structure includes a circuit layer (9), a chip (2) and a circuit layer (1), the second layer The front of the circuit layer (1) is provided with inner pins (8), the chip (2) is flip-chip mounted on the inner pins (8), and the chip (2) and the second layer of circuit layer (1) are encapsulated with A plastic encapsulant (3), the second circuit layer (1) and the first circuit layer (9) are connected through a copper column layer (4), and an external pin is provided on the back of the first circuit layer (9) (6), the back of the outer pin (6) is provided with a metal ball (7). The beneficial effects of the present invention are: reducing the thickness of the chip packaging carrier board, realizing ultra-thin high-density packaging; improving the level of reliability; truly achieving the technical capability of high-density circuits; completely solving the problem of traditional substrates in the packaging process warping problem.
Description
技术领域 technical field
本发明涉及一种超薄高密度多层线路芯片倒装封装结构及制作方法，属于半导体封装技术领域。 The invention relates to an ultra-thin high-density multilayer circuit chip flip-chip packaging structure and a manufacturing method, belonging to the technical field of semiconductor packaging.
背景技术 Background technique
当前高密度基板封装结构如图31所示，其制作工艺主要是在玻璃纤维板核心材料的基础上通过积成材料积成的方式叠加形成多层线路板，线路层之间通过激光钻孔的方式开孔，再镀孔完成电性连接。 The current high-density substrate packaging structure is shown in Figure 31. Its manufacturing process is mainly based on the core material of glass fiber boards, which are stacked to form multi-layer circuit boards by means of integrated materials, and laser drilling is used between the circuit layers. Holes are drilled and then plated to complete the electrical connection.
上述高密度基板封装结构存在以下不足和缺陷： The above-mentioned high-density substrate packaging structure has the following deficiencies and defects:
1、多了一层的玻璃纤维材料，同样的也多了一层玻璃纤维的成本； 1. There is an extra layer of glass fiber material, and also the cost of an extra layer of glass fiber;
2、因为多了一层玻璃纤维板核心层，厚度约为100~150μm，所以无法做到超薄封装设计； 2. Because there is an extra layer of glass fiber board core layer, the thickness is about 100~150μm, so it is impossible to achieve ultra-thin packaging design;
3、玻璃纤维本身就是一种发泡物质，所以容易因为放置的时间与环境吸入水分以及湿气，直接影响到可靠性的安全能力或是可靠性等级； 3. Glass fiber itself is a kind of foaming material, so it is easy to absorb moisture and moisture due to the storage time and environment, which directly affects the safety capability or reliability level of reliability;
4、线路层之间的连接是用激光钻孔方式进行开孔，再进行镀铜，通过激光钻孔形成的孔径大，难以做到高密度的设计与制造。 4. The connection between the circuit layers is made by laser drilling, and then copper plating is performed. The aperture formed by laser drilling is large, and it is difficult to achieve high-density design and manufacture.
发明内容 Contents of the invention
本发明的目的在于克服上述不足，提供一种超薄高密度倒装封装结构及制作方法，其工艺简单，不需使用玻璃纤维层，减薄了封装体厚度，提高了封装体的安全性和可靠性，减少了玻璃纤维材料带来的环境污染，而且线路层之间的电性连接采用的是电镀方法，能够真正做到超薄高密度线路的设计和制造；同时采用先封装后蚀刻方式，在封装过程中带有坚硬的金属载体，可确保在装片高温过程中不发生热变形，可彻底解决传统基板在封装工艺中的翘曲问题。 The purpose of the present invention is to overcome the above disadvantages, to provide an ultra-thin high-density flip-chip packaging structure and manufacturing method, which has a simple process, does not need to use a glass fiber layer, reduces the thickness of the package, and improves the safety and security of the package. Reliability, reducing the environmental pollution caused by glass fiber materials, and the electrical connection between the circuit layers adopts the electroplating method, which can truly achieve the design and manufacture of ultra-thin and high-density circuits; at the same time, it adopts the method of encapsulation first and then etching , with a hard metal carrier in the packaging process, which can ensure that no thermal deformation occurs during the high temperature process of chip loading, and can completely solve the warping problem of traditional substrates in the packaging process.
本发明的目的是这样实现的：一种超薄高密度多层线路芯片倒装封装结构，它包括一层线路层、芯片和二层线路层，所述二层线路层正面设置有内引脚，所述芯片倒装于内引脚上，所述芯片与二层线路层外围包封有塑封料，所述二层线路层与一层线路层之间通过铜柱层相连接，所述一层线路层背面设置有外引脚，所述外引脚与外引脚之间、一层线路层与一层线路层之间以及铜柱层与铜柱层之间均填充有绝缘材料，所述外引脚背面设置有金属球。 The purpose of the present invention is achieved in this way: an ultra-thin high-density multi-layer circuit chip flip-chip package structure, which includes a circuit layer, a chip and a second circuit layer, the front of the second circuit layer is provided with inner pins , the chip is flip-chip on the inner pins, the chip and the second layer of circuit layer are encapsulated with plastic compound, the second layer of circuit layer and the first layer of circuit layer are connected through a copper pillar layer, and the first layer of circuit layer Outer pins are arranged on the back of the layer circuit layer, and insulating materials are filled between the outer pins and the outer pins, between one layer of circuit layers and one layer of circuit layers, and between the copper column layer and the copper column layer. Metal balls are arranged on the back of the external pins.
一种超薄高密度多层线路芯片倒装封装结构的制造方法，所述方法包括以下工艺步骤： A method for manufacturing an ultra-thin high-density multilayer circuit chip flip-chip packaging structure, the method comprising the following process steps:
步骤一、取金属载板 Step 1. Take the metal carrier
步骤二、金属载板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal carrier
在金属载板表面电镀一层铜材薄膜， Electroplate a layer of copper film on the surface of the metal carrier,
步骤三、贴光阻膜显影开窗 Step 3: Paste the photoresist film, develop and open the window
在步骤二完成预镀铜材薄膜的金属载板的正面及背面分别贴上可进行曝光显影的光阻膜，利用曝光显影设备将金属载板正面进行图形曝光、显影与去除部分图形光阻膜，以露出金属载板正面后续需要进行外引脚电镀的区域图形， In step 2, the front and back of the metal carrier with the pre-plated copper film are pasted with a photoresist film that can be exposed and developed, and the exposure and development equipment is used to expose, develop and remove part of the graphic photoresist film on the front of the metal carrier. , to expose the pattern of the area on the front of the metal carrier that needs to be electroplated for the outer pins,
步骤四、电镀外引脚线路层 Step 4. Electroplating the outer pin circuit layer
在步骤三中金属载板正面去除部分光阻膜的区域内电镀上金属线路层作为外引脚线路层； In step 3, in the area where part of the photoresist film is removed from the front of the metal carrier board, a metal circuit layer is electroplated as an outer pin circuit layer;
步骤五、去除光阻膜 Step 5. Remove the photoresist film
去除金属载板表面的光阻膜， Remove the photoresist film on the surface of the metal carrier,
步骤六，覆盖绝缘材料层 Step 6, cover the insulating material layer
在线路板表面覆盖一层绝缘材料， A layer of insulating material is covered on the surface of the circuit board,
步骤七，绝缘材料表面减薄 Step 7, thinning the surface of the insulating material
对绝缘材料的表面进行机械减薄，减薄到露出外引脚为止， Mechanically thin the surface of the insulating material until the outer pins are exposed,
步骤八、绝缘材料表面金属化 Step 8. Metallization of insulating material surface
对绝缘材料表面进行金属化处理，使其表面后续能进行电镀线路层； Carry out metallization treatment on the surface of the insulating material, so that the surface can be subsequently electroplated circuit layer;
步骤九、贴光阻膜显影开窗 Step 9: Paste the photoresist film, develop and open the window
在步骤八完成金属化的线路板的正面及背面分别贴上可进行曝光显影的光阻膜，利用曝光显影设备将线路板正面进行图形曝光、显影与去除部分图形光阻膜，以露出线路板正面后续需要进行一层线路层电镀的区域图形； In step 8, the front and back of the metallized circuit board are respectively pasted with a photoresist film that can be exposed and developed, and the front of the circuit board is subjected to pattern exposure, development and removal of part of the pattern photoresist film using the exposure and development equipment to expose the circuit board. The area pattern that needs to be electroplated with a layer of circuit layer on the front side;
步骤十、电镀一层线路层 Step 10. Plating a circuit layer
在步骤九中线路板正面去除部分光阻膜的区域内电镀上金属线路层作为一层线路层； Electroplate a metal circuit layer as a layer of circuit layer in the area where part of the photoresist film is removed from the front of the circuit board in step 9;
步骤十一、去除光阻膜 Step 11. Remove the photoresist film
去除线路板表面的光阻膜， Remove the photoresist film on the surface of the circuit board,
步骤十二、快速蚀刻 Step 12. Fast etching
对线路板正面进行快速蚀刻，去除一层线路层以外的金属； Perform rapid etching on the front of the circuit board to remove the metal other than the circuit layer;
步骤十三、贴光阻膜显影开窗 Step 13: Paste the photoresist film, develop and open the window
在步骤十二完成快速蚀刻的线路板的正面及背面分别贴上可进行曝光显影的光阻膜，利用曝光显影设备将线路板正面进行图形曝光、显影与去除部分图形光阻膜，以露出线路板正面后续需要进行铜柱层电镀的区域图形； In step 12, a photoresist film that can be exposed and developed is attached to the front and back of the circuit board that has been rapidly etched, and the front of the circuit board is exposed, developed, and part of the pattern photoresist film is removed using the exposure and development equipment to expose the circuit. The area pattern that needs to be electroplated on the copper pillar layer on the front of the board;
步骤十四、电镀铜柱层 Step 14, electroplating copper column layer
在步骤十三中线路板正面去除部分光阻膜的区域内电镀上金属线路层作为铜柱层； Electroplating a metal circuit layer as a copper pillar layer in the area where part of the photoresist film is removed from the front of the circuit board in step 13;
步骤十五、去除光阻膜 Step 15. Remove the photoresist film
去除线路板表面的光阻膜， Remove the photoresist film on the surface of the circuit board,
步骤十六、覆盖第二层绝缘材料 Step 16. Cover the second layer of insulation
在线路板表面覆盖第二层绝缘材料， Cover the surface of the circuit board with a second layer of insulating material,
步骤十七、绝缘材料表面减薄 Step 17. Thinning of insulating material surface
将绝缘材料表面进行机械减薄，直到露出铜柱层为止， Mechanically thin the surface of the insulating material until the copper pillar layer is exposed,
步骤十八、绝缘材料表面金属化 Step 18. Metallization of insulating material surface
对绝缘材料表面进行金属化处理，使其表面后续能进行电镀； Metallize the surface of the insulating material so that the surface can be subsequently electroplated;
步骤十九、贴光阻膜显影开窗 Step 19: Paste the photoresist film, develop and open the window
在步骤十八完成金属化的线路板正面及背面分别贴上可进行曝光显影的光阻膜；利用曝光显影设备将线路板正面进行图形曝光、显影与去除部分图形光阻膜，以露出线路板正面后续需要进行二层线路层电镀的区域图形； In step 18, the front and back of the metallized circuit board are respectively pasted with a photoresist film that can be exposed and developed; the front of the circuit board is subjected to pattern exposure, development and removal of part of the pattern photoresist film to expose the circuit board by using the exposure and development equipment The area pattern that needs to be electroplated on the second layer of the circuit layer on the front side;
步骤二十、电镀二层线路层 Step 20: Electroplating the second circuit layer
在步骤十九中线路板正面去除部分光阻膜的区域内电镀上金属线路层作为二层线路层； Electroplate a metal circuit layer in the area where part of the photoresist film is removed from the front of the circuit board in step 19 as a second circuit layer;
步骤二十一、去除光阻膜 Step 21. Remove the photoresist film
去除线路板表面的光阻膜， Remove the photoresist film on the surface of the circuit board,
步骤二十二、快速蚀刻 Step 22, fast etching
对线路板正面进行快速蚀刻，去除二层线路层以外的金属； Perform rapid etching on the front of the circuit board to remove the metal other than the second layer of circuit layer;
步骤二十三、进行单层或多层金属电镀 Step 23: Carry out single-layer or multi-layer metal plating
在二层线路层正面倒装焊区进行单层或多层金属电镀，形成内引脚， Single-layer or multi-layer metal plating is performed on the front flip-chip welding area of the second-layer circuit layer to form inner pins.
步骤二十四、装片 Step 24, loading film
将芯片倒装于二层线路层正面芯片贴装区， Flip-chip the chip on the front chip mounting area of the second layer circuit layer,
步骤二十五、包封 Step 25. Encapsulation
在线路板正面采用塑封料进行塑封， The front of the circuit board is plastic-sealed with plastic sealing compound,
步骤二十六、去除金属载板 Step 26. Remove the metal carrier
将塑封好的线路板背面进行蚀刻，去除金属载板，露出外引脚， Etch the back of the plastic-encapsulated circuit board, remove the metal carrier, and expose the outer pins.
步骤二十七、有机层保护 Step 27, organic layer protection
在露出的外引脚处进行金属有机层保护； Metal-organic layer protection at the exposed outer pins;
步骤二十八、植球 Step twenty-eight, planting the ball
在去除金属载板后的线路板背面植球处植入金属球，使金属球与外引脚背面相接触， Implant metal balls at the ball planting place on the back of the circuit board after removing the metal carrier board, so that the metal balls are in contact with the back of the outer pins,
步骤二十九、切割成品 Step 29. Cut the finished product
将步骤二十八完成植球的半成品进行切割作业，使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来。 Cutting the semi-finished products that have been ball-planted in step 28, so that the plastic package modules that are originally integrated in an array form and contain chips are cut and separated one by one.
所述金属载板的材质为铜材、铁材、镍铁材或锌铁材。 The material of the metal carrier is copper, iron, nickel-iron or zinc-iron.
所述光阻膜采用湿式光阻膜或干式光阻膜。 The photoresist film adopts a wet photoresist film or a dry photoresist film.
所述光阻膜去除方法采用化学药水软化并采用高压水喷除。 The method for removing the photoresist film is softened by chemical liquid and sprayed with high-pressure water.
所述内引脚镀层种类为铜镍金、铜镍银、钯金、金或铜。 The plating layer of the inner pin is copper-nickel-gold, copper-nickel-silver, palladium-gold, gold or copper.
所述步骤二十五中塑封方式采用模具灌胶方式、喷涂设备的喷涂方式或是用贴膜方式。 The method of plastic sealing in step 25 adopts the method of pouring glue into the mold, the method of spraying by spraying equipment, or the method of sticking a film.
所述步骤二十六中的蚀刻药水采用氯化铜或是氯化铁。 The etching potion in the step 26 is copper chloride or ferric chloride.
所述步骤二十八中植球方式采用植球机或是采用金属膏印刷再经高温溶解之后形成球状体，所述金属球的材料是纯锡或锡合金。 In the step 28, the ball planting method adopts a ball planting machine or uses metal paste printing and then dissolves at high temperature to form a spherical body. The material of the metal ball is pure tin or tin alloy.
与现有技术相比，本发明的有益效果是： Compared with prior art, the beneficial effect of the present invention is:
1、本发明不需要使用玻璃纤维层作为核心材料层，所以可以显著降低芯片封装载板的厚度，实现超薄高密度封装； 1. The present invention does not need to use the glass fiber layer as the core material layer, so the thickness of the chip packaging carrier can be significantly reduced to achieve ultra-thin and high-density packaging;
2、本发明没有使用玻璃纤维层的发泡物质，所以可靠性的等级可以再提高，相对封装体的安全性就会提高； 2. The present invention does not use the foaming material of the glass fiber layer, so the level of reliability can be further improved, and the safety of the package will be improved;
3、本发明不需要使用玻璃纤维层物质，所以就可以减少玻璃纤维材料所带来的环境污染； 3. The present invention does not need to use glass fiber material, so the environmental pollution caused by glass fiber material can be reduced;
4、本发明高密度多层线路板线路层所采用的是电镀方法，而电镀层的总厚度约在10~15μm，而线路与线路之间的间隙可以轻松的达到15μm以下的间隙，同时线路层间的铜柱也是电镀形成，直径比传统钻孔小，所以可以真正地做到高密度线路的技术能力； 4. The circuit layer of the high-density multilayer circuit board of the present invention adopts the electroplating method, and the total thickness of the electroplating layer is about 10-15 μm, and the gap between the circuit and the circuit can easily reach a gap below 15 μm. At the same time, the circuit The copper pillars between the layers are also formed by electroplating, and the diameter is smaller than that of traditional drilling, so it can truly achieve the technical capability of high-density circuits;
5、本发明采用先封装后蚀刻的方式，由于封装过程中带有的金属载体具有热膨胀系数小，强度大等特点，可确保在装片高温过程中不发生热变形，可彻底解决传统基板在封装工艺中的翘曲问题。 5. The present invention adopts the method of encapsulation first and then etching. Since the metal carrier in the encapsulation process has the characteristics of small thermal expansion coefficient and high strength, it can ensure that no thermal deformation occurs during the high temperature process of chip loading, and it can completely solve the problem of traditional substrates. Warpage problem in packaging process.
附图说明 Description of drawings
图1~图29为本发明一种超薄高密度多层线路芯片倒装封装结构的制作方法各工序示意图。 1 to 29 are schematic diagrams of each process of a manufacturing method of an ultra-thin high-density multilayer circuit chip flip-chip packaging structure according to the present invention.
图30本发明一种超薄高密度多层线路芯片倒装封装结构的示意图。 FIG. 30 is a schematic diagram of an ultra-thin high-density multilayer circuit chip flip-chip packaging structure according to the present invention.
图31为当前高密度基板封装结构的示意图。 FIG. 31 is a schematic diagram of a current high-density substrate packaging structure.
其中： in:
二层线路层1 Layer 2 Line Layer 1
芯片2 Chip 2
塑封料3 Plastic compound 3
铜柱层4 Copper Pillar Layer 4
绝缘材料5 Insulation material 5
外引脚6 External pin 6
金属球7 metal ball 7
内引脚8 inner pin 8
一层线路层9。 One layer of circuit layer 9.
具体实施方式 Detailed ways
参见图30，本发明一种超薄高密度多层线路芯片倒装封装结构，它包括一层线路层9、芯片2和二层线路层1，所述二层线路层1正面设置有内引脚8，所述芯片2倒装于内引脚8上，所述芯片2与内引脚8正面之间通过金属凸点连接，所述芯片2与二层线路层1外围包封有塑封料3，所述二层线路层1与一层线路层9之间通过铜柱层4相连接，所述一层线路层9背面设置有外引脚6，所述外引脚6与外引脚6之间、一层线路层9与一层线路层9之间以及铜柱层4与铜柱层4之间均填充有绝缘材料5，所述外引脚6背面设置有金属球7。 Referring to Fig. 30, an ultra-thin and high-density multi-layer circuit chip flip-chip packaging structure of the present invention includes a circuit layer 9, a chip 2 and a circuit layer 1. The front of the circuit layer 1 is provided with an inner lead pin 8, the chip 2 is flip-mounted on the inner pin 8, the front of the chip 2 and the inner pin 8 are connected by metal bumps, and the outer periphery of the chip 2 and the second layer of circuit layer 1 is encapsulated with a plastic encapsulant 3. The second circuit layer 1 and the first circuit layer 9 are connected through the copper column layer 4, and the outer pin 6 is arranged on the back of the first circuit layer 9, and the outer pin 6 is connected to the outer pin 6, between a circuit layer 9 and a circuit layer 9, and between the copper column layer 4 and the copper column layer 4 are all filled with insulating material 5, and the outer pin 6 is provided with a metal ball 7 on the back.
其制造方法如下： Its manufacturing method is as follows:
步骤一、取金属载板 Step 1. Take the metal carrier
参见图1，取一片厚度合适的金属载板，金属载板的材质可以依据芯片的功能与特性进行变换，例如：铜材、铁材、镍铁材或锌铁材等； Referring to Figure 1, take a metal carrier with a suitable thickness. The material of the metal carrier can be changed according to the function and characteristics of the chip, for example: copper, iron, nickel-iron or zinc-iron;
步骤二、金属载板表面预镀铜材 Step 2. Pre-plating copper on the surface of the metal carrier
参见图2，在金属载板表面电镀一层铜材薄膜，目的是为后续电镀作基础，所述电镀的方式可以采用化学镀或是电解电镀； Referring to Figure 2, a layer of copper film is electroplated on the surface of the metal carrier to serve as the basis for subsequent electroplating. The electroplating method can be electroless plating or electrolytic plating;
步骤三、贴光阻膜显影开窗 Step 3: Paste the photoresist film, develop and open the window
参见图3，在步骤二完成预镀铜材薄膜的金属载板的正面及背面分别贴上可进行曝光显影的光阻膜，利用曝光显影设备将金属载板正面进行图形曝光、显影与去除部分图形光阻膜，以露出金属载板正面后续需要进行外引脚电镀的区域图形，所述光阻膜可以采用湿式光阻膜或干式光阻膜； Referring to Figure 3, in step 2, the front and back of the metal carrier of the pre-plated copper film are pasted with a photoresist film that can be exposed and developed, and the front of the metal carrier is exposed, developed and removed using the exposure and development equipment. Graphical photoresist film to expose the pattern of the area on the front of the metal carrier that needs to be electroplated for the outer pins. The photoresist film can be a wet photoresist film or a dry photoresist film;
步骤四、电镀外引脚线路层 Step 4. Electroplating the outer pin circuit layer
参见图4，在步骤三中金属载板正面去除部分光阻膜的区域内电镀上金属线路层作为外引脚线路层； Referring to Figure 4, in step 3, in the area where part of the photoresist film is removed from the front of the metal carrier board, a metal circuit layer is electroplated as the outer pin circuit layer;
步骤五、去除光阻膜 Step 5. Remove the photoresist film
参见图5，去除金属载板表面的光阻膜，去除方法采用化学药水软化并采用高压水喷除； See Figure 5, to remove the photoresist film on the surface of the metal carrier, the removal method is softened with chemical potion and sprayed with high-pressure water;
步骤六，覆盖绝缘材料层 Step 6, cover the insulating material layer
参见图6，在线路板表面覆盖一层绝缘材料，目的是为了作为外引脚和一层线路层的绝缘层，同时作后续电镀一层线路层的基础； Referring to Figure 6, a layer of insulating material is covered on the surface of the circuit board, the purpose is to serve as an insulating layer for the outer pins and a layer of circuit layer, and at the same time serve as the basis for subsequent electroplating of a layer of circuit layer;
步骤七，绝缘材料表面减薄 Step 7, thinning the surface of the insulating material
参见图7，对绝缘材料的表面进行机械减薄，减薄到露出外引脚为止，目的是为了使外引脚与后续的一层线路层连接，同时能增加后续化学铜的结合力； Referring to Figure 7, the surface of the insulating material is mechanically thinned until the outer pins are exposed, the purpose is to connect the outer pins to the subsequent layer of wiring, and at the same time increase the bonding force of the subsequent chemical copper;
步骤八、绝缘材料表面金属化 Step 8. Metallization of insulating material surface
参见图8，对绝缘材料表面进行金属化处理，使其表面后续能进行电镀线路层； Referring to Figure 8, the surface of the insulating material is metallized so that the surface can be subsequently plated with a circuit layer;
步骤九、贴光阻膜显影开窗 Step 9: Paste the photoresist film, develop and open the window
参见图9，在步骤八完成金属化的线路板的正面及背面分别贴上可进行曝光显影的光阻膜，利用曝光显影设备将线路板正面进行图形曝光、显影与去除部分图形光阻膜，以露出线路板正面后续需要进行一层线路层电镀的区域图形； Referring to Figure 9, the front and back of the metallized circuit board in step 8 are respectively pasted with a photoresist film that can be exposed and developed, and the front of the circuit board is subjected to graphic exposure, development and removal of part of the graphic photoresist film using the exposure and development equipment. To expose the pattern of the area on the front of the circuit board that needs to be electroplated with a layer of circuit layer;
步骤十、电镀金属线路层（一层线路层） Step 10. Plating metal circuit layer (one circuit layer)
参见图10，在步骤九中线路板正面去除部分光阻膜的区域内电镀上金属线路层作为一层线路层； Referring to Fig. 10, in the area where part of the photoresist film is removed from the front of the circuit board in step 9, a metal circuit layer is electroplated as a layer of circuit layer;
步骤十一、去除光阻膜 Step 11. Remove the photoresist film
参见图11，去除线路板表面的光阻膜，去除方法采用化学药水软化并采用高压水喷除； See Figure 11, to remove the photoresist film on the surface of the circuit board, the removal method is softened by chemical potion and sprayed with high-pressure water;
步骤十二、快速蚀刻 Step 12. Fast etching
参见图12，对线路板正面进行快速蚀刻，去除一层线路层以外的金属； Referring to Figure 12, perform rapid etching on the front of the circuit board to remove a layer of metal other than the circuit layer;
步骤十三、贴光阻膜显影开窗 Step 13: Paste the photoresist film, develop and open the window
参见图13，在步骤十二完成快速蚀刻的线路板的正面及背面分别贴上可进行曝光显影的光阻膜，利用曝光显影设备将线路板正面进行图形曝光、显影与去除部分图形光阻膜，以露出线路板正面后续需要进行铜柱层电镀的区域图形； Referring to Figure 13, the front and back of the circuit board that has been rapidly etched in step 12 are respectively pasted with a photoresist film that can be exposed and developed, and the front of the circuit board is subjected to pattern exposure, development and removal of part of the pattern photoresist film using the exposure and development equipment , to expose the pattern of the area on the front of the circuit board that needs to be electroplated on the copper column layer;
步骤十四、电镀铜柱层 Step 14, electroplating copper column layer
参见图14，在步骤十三中线路板正面去除部分光阻膜的区域内电镀上金属线路层作为连接一层线路层和二层线路层的铜柱层； Referring to Fig. 14, in step 13, in the area where part of the photoresist film is removed from the front of the circuit board, a metal circuit layer is electroplated as a copper column layer connecting the first circuit layer and the second circuit layer;
步骤十五、去除光阻膜 Step 15. Remove the photoresist film
参见图15，去除线路板表面的光阻膜，去除方法采用化学药水软化并采用高压水喷除； See Figure 15, remove the photoresist film on the surface of the circuit board, the removal method is softened by chemical potion and sprayed with high-pressure water;
步骤十六、覆盖第二层绝缘材料 Step 16. Cover the second layer of insulation
参见图16，在线路板表面覆盖第二层绝缘材料，目的是为了做铜柱层与二层线路层之间的绝缘层，同时为后续电镀二层线路层做基础； Referring to Figure 16, the second layer of insulating material is covered on the surface of the circuit board, the purpose is to make an insulating layer between the copper column layer and the second layer of circuit layer, and at the same time lay the foundation for the subsequent electroplating of the second layer of circuit layer;
步骤十七、绝缘材料表面减薄 Step 17. Thinning of insulating material surface
参见图17，将绝缘材料表面进行机械减薄，直到露出铜柱层为止，目的是为了使铜柱层与后续的二层线路层连接，同时能增加后续化学铜的结合力； Referring to Figure 17, the surface of the insulating material is mechanically thinned until the copper column layer is exposed, the purpose is to connect the copper column layer with the subsequent second-layer circuit layer, and at the same time increase the bonding force of the subsequent chemical copper;
步骤十八、绝缘材料表面金属化 Step 18. Metallization of insulating material surface
参见图18，对绝缘材料表面进行金属化处理，使其表面后续能进行电镀； Referring to Figure 18, the surface of the insulating material is metallized so that the surface can be subsequently electroplated;
步骤十九、贴光阻膜显影开窗 Step 19: Paste the photoresist film, develop and open the window
参见图19，在步骤十八完成金属化的线路板正面及背面分别贴上可进行曝光显影的光阻膜；利用曝光显影设备将线路板正面进行图形曝光、显影与去除部分图形光阻膜，以露出线路板正面后续需要进行二层线路层电镀的区域图形； Referring to Figure 19, the front and back of the metallized circuit board in step 18 are respectively pasted with a photoresist film that can be exposed and developed; the front of the circuit board is subjected to pattern exposure, development and removal of part of the pattern photoresist film by using the exposure and development equipment, To expose the area pattern on the front of the circuit board that needs to be electroplated on the second layer of the circuit layer;
步骤二十、电镀金属线路层（二层线路层） Step 20, electroplating metal circuit layer (two-layer circuit layer)
参见图20，在步骤十九中线路板正面去除部分光阻膜的区域内电镀上金属线路层作为二层线路层； Referring to FIG. 20 , in the area where part of the photoresist film is removed from the front of the circuit board in step 19, a metal circuit layer is electroplated as a second circuit layer;
步骤二十一、去除光阻膜 Step 21. Remove the photoresist film
参见图21，去除线路板表面的光阻膜，去除方法采用化学药水软化并采用高压水喷除； See Figure 21, to remove the photoresist film on the surface of the circuit board, the removal method is softened by chemical potion and sprayed with high-pressure water;
步骤二十二、快速蚀刻 Step 22, fast etching
参见图22，对线路板正面进行快速蚀刻，去除二层线路层以外的金属； Referring to Figure 22, perform rapid etching on the front of the circuit board to remove the metal other than the second circuit layer;
步骤二十三、进行单层或多层金属电镀 Step 23: Carry out single-layer or multi-layer metal plating
参见图23，在二层线路层正面倒装焊区进行单层或多层金属电镀，形成内引脚，镀层种类可以是铜镍金、铜镍银、钯金、金或铜等，电镀方法可以是化学电镀或是电解电镀； Referring to Figure 23, single-layer or multi-layer metal electroplating is performed on the front flip-chip soldering area of the second-layer circuit layer to form inner pins. The type of plating can be copper-nickel-gold, copper-nickel-silver, palladium-gold, gold or copper, etc. It can be chemical plating or electrolytic plating;
步骤二十四、装片 Step 24, loading film
参见图24，将芯片倒装于二层线路层正面芯片贴装区，芯片与二层线路层倒装焊区之间通过金属凸点连接； Referring to Figure 24, the chip is flip-chip mounted on the front chip mounting area of the second-layer circuit layer, and the chip and the flip-chip soldering area of the second-layer circuit layer are connected by metal bumps;
步骤二十五、包封 Step 25. Encapsulation
参见图25，在线路板正面采用塑封料进行塑封，塑封方式可以采用模具灌胶方式、喷涂设备的喷涂方式或是用贴膜方式，所述塑封料可以采用有填料物质或是无填料物质的环氧树脂； Referring to Figure 25, plastic sealing compound is used for plastic sealing on the front of the circuit board. The plastic sealing method can be mold filling, spraying equipment spraying or film sticking. The plastic sealing compound can be a ring with filler or no filler. oxygen resin;
步骤二十六、去除金属载板 Step 26. Remove the metal carrier
参见图26，将塑封好的线路板背面进行蚀刻，去除金属载板，露出外引脚，蚀刻药水可以采用氯化铜或是氯化铁； Referring to Figure 26, etch the back of the plastic-encapsulated circuit board, remove the metal carrier, and expose the outer pins. The etching solution can be copper chloride or ferric chloride;
步骤二十七、有机层保护 Step 27, organic layer protection
参见图27，在露出的外引脚处进行金属有机层保护； Referring to Figure 27, metal-organic layer protection is performed at the exposed outer pins;
步骤二十八、植球 Step twenty-eight, planting the ball
参见图28，在去除金属载板后的线路板背面植球处植入金属球，使金属球与外引脚背面相接触，植球方式可以采用常规的植球机或是采用金属膏印刷再经高温溶解之后即可形成球状体，金属球的材料可以是纯锡或锡合金； Referring to Figure 28, metal balls are implanted at the ball planting place on the back of the circuit board after the metal carrier is removed, so that the metal balls are in contact with the back of the outer pins. The ball planting method can be a conventional ball planting machine or metal paste printing. Spheroids can be formed after high temperature dissolution, and the material of metal balls can be pure tin or tin alloy;
步骤二十九、切割成品 Step 29. Cut the finished product
参见图29，将步骤二十八完成植球的半成品进行切割作业，使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来。 Referring to FIG. 29 , the semi-finished products that have been ball-planted in step 28 are cut, so that the plastic package modules that are originally integrated in the form of an array assembly and contain chips are cut and separated one by one.
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| CN102856212A (en) * | 2012-06-09 | 2013-01-02 | 江苏长电科技股份有限公司 | Flip etching-after-packaging manufacture method and packaging structure for chips with two sides and three-dimensional lines |
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| CN102856212A (en) * | 2012-06-09 | 2013-01-02 | 江苏长电科技股份有限公司 | Flip etching-after-packaging manufacture method and packaging structure for chips with two sides and three-dimensional lines |
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Effective date of registration: 20160429 Address after: 214434 Jiangyin, Jiangsu, Chengjiang city street, Long Hill Road, No. 78 Patentee after: Jiangsu Changjiang Electronics Technology Co., Ltd. Address before: 214434 Jiangyin, Jiangsu Province, the development of mountain road, No. 78, No. Patentee before: Jiangsu Changjiang Electronics Technology Co., Ltd. |