CN103247266A - Bistable displays associated with cholesteric liquid crystals - Google Patents

Abstract

The invention provides a bistable display related to a cholesteric liquid crystal, which resets (updates) all pixels in a cholesteric liquid crystal display panel in a reset stage through a reset module existing outside a source driver, and drives all pixels in the cholesteric liquid crystal display panel in a driving stage through the source driver (namely, gray scales are switched through analog voltages provided by the source driver). Therefore, the time for displaying the picture can be shortened besides the better gray scale display effect, thereby realizing the effect of playing the dynamic picture.

Description

Bistable displays associated with cholesteric liquid crystals

technical field

The invention relates to a plane display technology, in particular to a bistable display associated with cholesteric liquid crystals.

Background technique

A bistable display is a display that uses a bistable medium for display, and technologies to achieve a bistable display include electronic ink (E-Ink) display, cholesteric liquid crystal display (cholesteric liquid crystal display (ChLCD), electro-phoretic display (EPD), electrowetting display (EWD) or quick response-liquid powder display (quick response-liquid powder display, QR-LPD) and other display technologies.

In terms of cholesteric liquid crystal display technology, since the driving voltage of cholesteric liquid crystal (ChLC) is relatively high, most of its driving methods adopt passive driving method, and the same power supply voltage is used together to control the duty cycle. The way to switch the gray level (gray level). In this case, the time for displaying the picture is expected to be prolonged, so that the effect of playing a dynamic picture cannot be realized.

On the other hand, if you want to use an active driving method to drive cholesteric liquid crystal (ChLC), because the driving ability of the source driver (source driver) of the current general liquid crystal display (LCD) cannot be reset (updated) smoothly For cholesteric liquid crystal (ChLC), the reason is that the upper limit of the driving voltage that the source driver can provide/generate does not reach the standard for resetting (renewing) cholesteric liquid crystal (ChLC). In this case, in order to achieve the purpose of driving cholesteric liquid crystal (ChLC) in an active driving manner, it is expected that the upper limit of the driving voltage that the source driver can provide/generate must be increased, but this will lead to a cost increase. Increase.

Contents of the invention

In view of this, in order to effectively solve/improve the problems mentioned in the prior art, an exemplary embodiment of the present invention provides a bistable display, which includes: a bistable display panel, a reset module, an active Driver modules, and switching modules. Wherein, the reset module is used for resetting the bistable display panel in a reset phase. The active driving module is used for driving the bistable display panel in a driving stage. The switching module is coupled to the bistable display panel, the active driving module and the reset module, and is used to respond to the first and a second switching signal so that the reset module and the active driving module are respectively in the The reset phase and the driving phase are connected with the bistable display panel.

In an exemplary embodiment of the present invention, the bistable display may further include: a common voltage generator coupled to the bistable display panel for generating a common voltage for the bistable display panel.

In an exemplary embodiment of the present invention, the bistable display panel may include M data lines, N scan lines and a plurality of pixels arranged in a matrix, where M and N are positive integers, and the switching module includes: M first switches and N second switches. The first terminals of the M first switches are used to receive a reset signal from the reset module, the second terminals of the M first switches are respectively coupled to the M data lines, and the The control ends of the M first switches are used to receive the first switching signal. The first ends of the N second switches are used to receive a gate control signal from the reset module, the second ends of the N second switches are respectively coupled to the N scanning lines, and the N The control terminal of the second switch is used to receive the first switching signal.

In an exemplary embodiment of the present invention, the switching module may further include: M third switches and N fourth switches. Wherein, the first ends of the M third switches are used to respectively receive a plurality of display data signals from the active driving module, and the second ends of the M third switches are respectively coupled to the M data lines , and the control ends of the M third switches are used to receive the second switching signal. The first ends of the N fourth switches are used to sequentially receive a plurality of scanning signals from the active driving module, the second ends of the N fourth switches are respectively coupled to the N scanning lines, and The control ends of the N fourth switches are used to receive the second switching signal.

In an exemplary embodiment of the present invention, the active driving module may include: a gate driver and a source driver. Wherein, the gate driver is used to generate the plurality of scanning signals in sequence; and the source driver is used to generate the plurality of display data signals.

In an exemplary embodiment of the present invention, the first switching signal is enabled during the reset phase and disabled during the driving phase; in addition, the second switching signal is disabled during the reset phase enabled and enabled during the drive phase. Under this condition, the M first switches and the N second switches are simultaneously turned on in the reset phase, and are simultaneously turned off in the driving phase; in addition, the M third switches and the N second switches are The N fourth switches are simultaneously turned off during the reset phase and simultaneously turned on during the driving phase.

In an exemplary embodiment of the present invention, in the reset phase, the reset module provides the gate control signal to turn on all pixels at the same time, and provides the reset signal to form a voltage difference with the common voltage to reset all pixels simultaneously.

In an exemplary embodiment of the present invention, the driving phase may include a writing sub-phase, and in the writing sub-phase, the source driver cooperates with a plurality of scanning signals sequentially generated by the gate driver to generate The plurality of display data signals are used to drive all the pixels.

In an exemplary embodiment of the present invention, the driving phase may further include a display sub-phase, and in the display sub-phase, the source driver and the gate driver stop generating the plurality of display data signals and the display data signals respectively. The plurality of scanning signals are used to stop driving all the pixels; at the same time, the bistable display panel displays images.

In an exemplary embodiment of the present invention, the M first switches, the N second switches, the M third switches, and the N fourth switches can be fabricated on dual On the steady state display panel; alternatively, can be set/configured outside the bistable display panel.

In an exemplary embodiment of the present invention, the M first switches and the M third switches may be respectively arranged on the upper and lower sides of the bistable display panel, so as to respectively couple the M data lines . Under this condition, the N second switches and the N fourth switches may be respectively arranged on the left and right sides of the bistable display panel, so as to be respectively coupled to the N scan lines.

In another exemplary embodiment of the present invention, the M first switches and the M third switches can be arranged on the upper side or the lower side of the bistable display panel at the same time, so as to be respectively coupled to the M data lines. Under this condition, the N second switches and the N fourth switches can be arranged on the left side or the right side of the bistable display panel at the same time, so as to be respectively coupled to the N scanning lines.

In an exemplary embodiment of the present invention, the proposed bistable display may further include: a timing controller coupled to the active driving module, the common voltage generator, the reset module and the switching module, for To control the operation of the active driving module, the common voltage generator, the reset module and the switching module.

In an exemplary embodiment of the present invention, the bistable display is at least a cholesteric liquid crystal display, and the bistable display panel is at least a cholesteric liquid crystal display panel.

Based on the above, the present invention provides a bistable display associated with cholesteric liquid crystals and adopts an active driving method, which uses a reset module outside the source driver to reset the cholesteric liquid crystal display panel in the reset phase. All the pixels are reset (updated), and all the pixels in the cholesteric liquid crystal display panel are driven in the driving phase by the source driver (that is, the gray scale is switched by the analog voltage provided by the source driver). In this way, in addition to obtaining a better grayscale display effect, the time for displaying the image can also be shortened, thereby achieving the effect of playing a dynamic image.

It should be understood that the above general description and the following specific embodiments are only illustrative and explanatory, and cannot limit the scope of the present invention.

Description of drawings

The accompanying drawings, which form a part of the specification of this invention, illustrate example embodiments of the invention and together with the description explain the principles of the invention.

FIG. 1 shows a system architecture diagram of a bistable display (bistable display) 10 according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of the bistable display panel (bistable display panel) 101 shown in FIG. 1;

FIG. 3 is a schematic diagram showing the implementation of a bistable display 10 according to an exemplary embodiment of the present invention;

FIG. 4 shows a schematic diagram of the operation of a bistable display 10 according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic diagram of a modified implementation of the bistable display 10 shown in FIG. 3 .

Reference signs:

10: bistable display;

101: bistable display panel;

103: reset the module;

105: active drive module;

107: switch modules;

109: common voltage generator;

111: timing controller;

301: gate driver;

303: source driver;

DL1～DLM: data line;

SL1～SLN: scanning line;

SW1～SW4: switch;

P: pixel;

S1, S2: switching signal;

RS: reset signal;

GS: gate control signal;

DS1～DSM: display data signal;

SS1～SSN: scanning signal;

Vcom: common voltage;

FP: picture period;

PR: reset phase;

PD: driving phase;

PW: write subphase;

PS: Subphases are shown.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In addition, wherever possible, elements/components using the same reference numerals in the drawings and embodiments represent the same or similar parts.

FIG. 1 shows a system architecture diagram of a bistable display (bistable display) 10 according to an exemplary embodiment of the present invention. Please refer to FIG. 1, the bistable display 10 can be a cholesteric liquid crystal display (cholesteric liquid crystal display, ChLCD), but it is not limited thereto, and it includes: the resolution is M*N (M, N are positive integers) Bistable display panel (ie, cholesteric liquid crystal display panel) 101, reset module (reset module) 103, active driving module (active driving module) 105, switching module (switching module) 107, common voltage generator (common voltage generator) 109, and timing controller (timing controller, T-con) 111.

In this exemplary embodiment, as shown in FIG. 2, the bistable display panel 101 includes: M data lines (data lines) DL1-DLM, N scan lines (scan lines) SL1-SLN, and a plurality of the following Pixels (pixels) P arranged in a matrix. Wherein, each pixel P is coupled and disposed at the intersection of the corresponding data line DLi (i=1˜M) and the scan line SLj (j=1˜N).

The reset module 103 is used for resetting (refreshing) the bistable display panel 101 in a reset phase. The active driving module 105 is used for driving the bistable display panel 101 in a driving phase. The switching module 107 is coupled to the bistable display panel 101 , the reset module 103 and the active driving module 105 to respond to the first and second switching signals (switching) from the timing controller (T-con) 111 signals) S1, S2 to cause the reset module 103 and the active driving module 105 to be connected to the bistable display panel 101 in the reset phase and the driving phase, respectively.

The common voltage generator 109 is coupled to the bistable display panel 101 for generating a common voltage (common voltage) Vcom to the bistable display panel 101 . The timing controller 111 is coupled to the reset module 103 , the active driving module 105 , the switching module 107 and the common voltage generator 109 to control the reset module 103 , the active driving module 105 and the switching module 107 operation with the common voltage generator 109 .

Based on this, FIG. 3 shows a schematic diagram of the implementation of the bistable display 10 according to an exemplary embodiment of the present invention. Please refer to FIGS. 1-3 together. In this exemplary embodiment, the reset module 103 generates a reset signal (reset signal) RS and a gate-control signal (gate-control signal) in response to the control of the timing controller 111. )GS.

The active driving module 105 includes: a gate driver 301 and a source driver 303 . Wherein, the gate driver 301 responds to the control of the timing controller 111 and sequentially generates scan signals (scan signals) SS1˜SSN; in addition, the source driver 303 responds to the control of the timing controller 111 to generate display data signals (display data signal) DS1 ~ DSM.

The switching module 107 includes: M first switches SW1 (M*SW1), N second switches SW2 (N*SW2), M third switches SW3 (M*SW3), and N fourth switches SW4 ( N*SW4). The first ends of the M first switches SW1 are used to receive the reset signal RS from the reset module 103, and the second ends of the M first switches SW1 are respectively coupled to the bistable display panel 101. The data lines DL1˜DLM, and the control terminals of the M first switches SW1 are used to receive the first switching signal S1 from the timing controller (T-con) 111 .

The first ends of the N second switches SW2 are used to receive the gate control signal GS from the reset module 103, and the second ends of the N second switches SW2 are respectively coupled to the bistable display panel 101. The scanning lines SL1˜SLN, and the control terminals of the N second switches SW2 are used to receive the first switching signal S1 from the timing controller (T-con) 111 .

The first ends of the M third switches SW3 are used to respectively receive the display data signals DS1˜DSM generated by the source driver 303 of the active driving module 105, and the second ends of the M third switches SW3 They are respectively coupled to the data lines DL1 ˜ DLM in the bistable display panel 101 , and the control terminals of the M third switches SW3 are used to receive the second switching signal S2 from the timing controller (T-con) 111 .

The first ends of the N fourth switches SW4 are used to sequentially receive the scan signals SS1˜SSN generated by the gate driver 301 of the active driving module 105, and the second ends of the N fourth switches SW4 They are respectively coupled to the scan lines SL1 - SLN in the bistable display panel 101 , and the control terminal in the bistable display panel 101 is used to receive the second switching signal S2 from the timing controller (T-con) 111 .

In this exemplary embodiment, all switches SW1-SW4 can be manufactured on the bistable display panel 101 simultaneously with all pixels P, so all switches SW1-SW4 can be implemented by thin film transistors (Thin Film Transistor, TFT), but Not limited to. In other words, all the switches SW1 - SW4 can also be arranged/configured outside the bistable display panel 101 , all aspects depend on actual design/application requirements.

On the other hand, FIG. 4 shows a schematic diagram of the operation of the bistable display 10 according to an exemplary embodiment of the present invention. Please refer to FIGS. 1-4 together. The first switching signal S1 generated by the timing controller (T-con) 111 will be enabled in the reset phase PR and disabled in the driving phase PD; in addition, the timing controller (T-con) The second switching signal S2 generated by - con) 111 is disabled in the reset phase PR and enabled in the driving phase PD. In this way, the M first switches SW1 and the N second switches SW2 will be turned on (turned-on) in the reset phase PR and simultaneously turned off (turned-off) in the driving phase PD; In addition, the M third switches SW3 and the N fourth switches SW4 are turned off in the reset phase PR and turned on in the drive phase PD simultaneously.

In this exemplary embodiment, in the reset phase PR, the reset module 103 provides a gate control signal GS to simultaneously turn on all the pixels P in the bistable display panel 101, and provides a reset signal RS to be connected to the common voltage The common voltage Vcom generated by the generator 109 forms a voltage difference so as to simultaneously reset (refresh) all the pixels P in the bistable display panel 101 .

On the other hand, the entire driving phase PD can be divided into a writing sub-phase (writing sub-phase) PW and a displaying sub-phase (displaying sub-phase) PS. In the writing sub-phase PW, the source driver 303 will cooperate with the scan signals SS1-SSN sequentially generated by the gate driver 301 to generate display data signals DS1-DSM, so as to sequentially drive all the pixels P in the bistable display panel 101 . In addition, in the display sub-phase PS, the source driver 303 and the gate driver 301 respectively stop generating the display data signals DS1-DSM and the scan signals SS1-SSN, so as to stop driving all the pixels P in the bistable display panel 101; At the same time, the bistable display panel 101 will display images.

It is worth mentioning here that the time length of the reset phase PR and the accumulation driving phase PD can be regarded as a frame period FP of the bistable display 10 . Moreover, the bistable display 10 will first enter the reset phase PR and then enter the driving phase PD during operation. Based on this, when the bistable display 10 enters the reset phase PR, in response to the control of the timing controller 111, the reset module 103 will generate (variable) reset signal RS and gate control signal GS, and the common voltage will generate The device 109 generates a (variable) common voltage Vcom.

Under this condition, since the first and second switching signals S1 and S2 are respectively enabled and disabled during the reset phase PR, the M first switches SW1 and the N second switches SW2 will be simultaneously is turned on, and the M third switches SW3 and the N fourth switches SW4 are turned off simultaneously. In other words, in the reset phase PR, the switching module 107 will cause the reset module 103 to be connected to the bistable display panel 101 , and cause the active driving module 105 to be disconnected from the bistable display panel 101 .

In addition, in the reset phase PR, the gate control signal GS generated by the reset module 103 will turn on all the pixels P in the bistable display panel 101 at the same time, so that all the pixels P in the bistable display panel 101 The reset (refresh) is performed in response to the voltage difference between the (variable) reset signal RS generated by the reset module 103 and the (variable) common voltage Vcom generated by the common voltage generator 109 .

After all the pixels P in the bistable display panel 101 are reset (refreshed) in the reset phase PR, the bistable display 10 will then enter the driving phase PD. When the bistable display 10 enters the driving phase PD, since the first and second switching signals S1 and S2 are respectively disabled and enabled during the driving phase PD, the M first switches SW1 and the N The second switches SW2 are turned off at the same time, and the M third switches SW3 and the N fourth switches SW4 are turned on at the same time. In other words, in the driving phase PD, the switching module 107 will cause the reset module 103 to be disconnected from the bistable display panel 101 and cause the active driving module 105 to be connected to the bistable display panel 101 .

At the same time, in response to the control of the timing controller 111, the gate driver 301 and the source driver 303 will respectively generate the scanning signal SSj (j=1-N) and the display data signal DSi in the writing sub-phase PW of the driving phase PD. (i=1~M). Moreover, the source driver 303 will cooperate with the scan signals SS1-SSN sequentially generated by the gate driver 301 to generate display data signals DS1-DSM, so as to drive all the pixels P in the bistable display panel 101.

Next, in the display sub-phase PS, the source driver 303 and the gate driver 301 will respond to the control of the timing controller 111 and stop generating the display data signals DS1˜DSM and scan signals SS1˜SSN respectively, so as to stop driving the bistable state All the pixels P in the display panel 101; at the same time, since there is no voltage difference (that is, equipotential) between each data line DLi (i=1-M) and the common voltage Vcom, the bistable display panel 101 will be able to display images in the display sub-stage PS.

It can be seen that the bistable display 10 disclosed in this exemplary embodiment is related to cholesteric liquid crystal (ChLCD) and adopts an active driving method. Since the bistable display 10 resets (refreshes) all the pixels P in the bistable display panel 101 (cholesteric liquid crystal display panel) in the reset phase PR through the reset module 103 existing outside the source driver 303 , and drive all the pixels P in the bistable display panel 101 (cholesteric liquid crystal display panel) in the driving phase PD through the source driver 303 (that is, switch the gray scale through the analog voltage provided by the source driver 303) . In this way, in addition to obtaining a better grayscale display effect, the time for displaying the image can also be shortened, thereby achieving the effect of playing a dynamic image.

To be more clear, if switching 16 gray scales is taken as an example, the traditional passive driving method must spend 1 frame period (FP) to reset/update the pixels in the cholesteric liquid crystal display panel, and must spend 16 frame periods (FP) is used to drive the pixels in the cholesteric liquid crystal display panel. Therefore, for a cholesteric liquid crystal display with a frame refresh rate of 60Hz, the traditional passive driving method can only display 3 image frames in one second, so it is not necessary. It is good for playing dynamic pictures.

In contrast, in the present invention, if switching 16 gray scales is taken as an example, the active driving method adopted in the present invention also takes one frame period (FP) to reset/reset the pixels in the cholesteric liquid crystal display panel. update, but it only needs to spend one frame period (FP) to drive the pixels in the cholesteric liquid crystal display panel, so in terms of the cholesteric liquid crystal display with a frame refresh rate of 60Hz, the active type used in the present invention The driving method can display 30 images in one second, so it is more conducive to playing dynamic images.

On the other hand, FIG. 5 is a schematic diagram of a modified implementation of the bistable display 10 shown in FIG. 3 . Please refer to FIG. 3 and FIG. 5 together. It can be clearly seen from FIG. 3 that the M first switches SW1 and the M third switches SW3 are respectively arranged on the upper and lower sides of the bistable display panel 101, so as to to be respectively coupled with the data lines DL1~DLM in the bistable display panel 101; in addition, the N second switches SW2 and the N fourth switches SW4 are respectively arranged on the left and right sides of the bistable display panel 101. side, so as to be respectively coupled with the scan lines SL1 - SLN in the bistable display panel 101 .

Under a similar concept, as shown in FIG. 5 , the M first switches SW1 and the M third switches SW3 can (for example) be simultaneously configured on the lower side of the bistable display panel 101 (but can be changed to upper side), so as to be respectively coupled with the data lines DL1-DLM in the bistable display panel 101; in addition, the N second switches SW2 and the N fourth switches SW4 can also be (for example) simultaneously arranged on The right side of the bistable display panel 101 (but can be changed to the left side) is used to be respectively coupled to the scan lines SL1 - SLN in the bistable display panel 101 . However, since the operation modes of FIG. 3 and FIG. 5 are similar, they will not be repeated here.

In summary, the present invention provides a bistable display associated with cholesteric liquid crystals and adopts an active driving method, which uses a reset module outside the source driver to reset the cholesteric liquid crystal display panel during the reset phase. All the pixels in the cholesteric liquid crystal display panel are reset (updated) through the source driver to drive all the pixels in the cholesteric liquid crystal display panel in the driving phase (that is, the gray scale is switched through the analog voltage provided by the source driver). In this way, in addition to obtaining a better grayscale display effect, the time for displaying the image can also be shortened, thereby achieving the effect of playing a dynamic image.

To put it another way, as long as all the pixels in the cholesteric liquid crystal display panel are reset (updated) through any device/module/unit/circuit outside the (active) source driver, and through the (active) source driver A similar technical means or method for driving all the pixels in the cholesteric liquid crystal display panel by a polar driver falls within the scope of protection of the present invention.

In addition, although the above exemplary embodiments are described by taking the cholesteric liquid crystal display as an example, the present invention is not limited thereto. In other words, the technical means/concepts/thoughts disclosed/taught in the present invention can be applied to any type of flat panel display device with bistable characteristics and high driving voltage required. Even, the operation schematic diagram disclosed/taught in FIG. 4 can also be slightly changed and modified without departing from the spirit and scope of the present invention, for example: the state of the reset signal RS and the common voltage Vcom in the reset phase PR , or the duration of PR and PD (PW, PS) at each stage. Everything depends on the actual design/application/driver requirements.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention, and any person of ordinary skill in the art may make some changes and modifications without departing from the spirit and scope of the present invention. In addition, any embodiment or scope of claims of the present invention does not necessarily achieve all the objects or advantages or features disclosed in the present invention. In addition, the abstract and titles are only used to aid in searching patent documents, and are not intended to limit the scope of the present invention.

Claims (18)

1. A bistable display comprising: a bistable display panel; A reset module, used to reset the bistable display panel in a reset phase; an active driving module for driving the bistable display panel in a driving phase; and A switching module, coupled to the bistable display panel, the active driving module and the reset module, for responding to a first and a second switching signal to cause the reset module and the active The mode driving module is respectively connected with the bistable display panel in the reset phase and the driving phase. 2. The bistable display of claim 1, further comprising: A common voltage generator, coupled to the bistable display panel, is used to generate a common voltage for the bistable display panel. 3. The bistable display according to claim 2, wherein the bistable display panel comprises M data lines, N scan lines and a plurality of pixels arranged in a matrix, M and N are positive integers, and the Switch mods include: M first switches, the first end of which is used to receive a reset signal from the reset module, the second end of which is respectively coupled to the data lines, and the control end of which is used to receive the first switching signal ;as well as N second switches, the first end of which is used to receive a gate control signal from the reset module, the second end of which is respectively coupled to the scan lines, and the control end of which is used to receive the first switching signal . 4. The bistable display according to claim 3, wherein the switching module further comprises: M third switches, the first ends of which are used to respectively receive a plurality of display data signals from the active driving module, the second ends of which are respectively coupled to the data lines, and the control ends thereof are used to receive the first display data signals two switching signals; and N fourth switches, the first ends of which are used to sequentially receive a plurality of scanning signals from the active driving module, the second ends of which are respectively coupled to the scanning lines, and the control ends thereof are used to receive the first scanning signals Two switching signals. 5. The bistable display according to claim 4, wherein the active driving module comprises: a gate driver for sequentially generating the scan signals; and A source driver is used to generate the display data signals. 6. The bistable display of claim 5, wherein The first switching signal is enabled during the reset phase and disabled during the drive phase; and The second switching signal is disabled in the reset phase and enabled in the driving phase. 7. The bistable display of claim 6, wherein The first switches and the second switches are simultaneously turned on during the reset phase, and are simultaneously turned off during the drive phase; and The third switches and the fourth switches are turned off in the reset phase and turned on in the driving phase simultaneously. 8. The bistable display according to claim 7, wherein in the reset phase, the reset module provides the gate control signal to simultaneously turn on the pixels, and provides the reset signal to form a common voltage with the common voltage. pressure difference to reset the pixels simultaneously. 9. The bistable display according to claim 7, wherein the driving phase includes a writing sub-phase, and in the writing sub-phase, the source driver cooperates with the scanning signals generated by the gate driver The display data signals are generated to drive the pixels. 10. The bistable display according to claim 9, wherein the driving phase further comprises a display sub-phase, and in the display sub-phase, the source driver and the gate driver stop generating the display data signals and The scanning signals are used to stop driving the pixels; at the same time, the bistable display panel displays images. 11. The bistable display according to claim 4, wherein the first switches, the second switches, the third switches, and the fourth switches are simultaneously fabricated with the pixels in the bistable display panel. 12. The bistable display according to claim 4, wherein the first switches, the second switches, the third switches and the fourth switches are disposed outside the bistable display panel. 13. The bistable display according to claim 4, wherein the first switches and the third switches are respectively disposed on upper and lower sides of the bistable display panel, so as to be respectively coupled to the data lines. 14. The bistable display according to claim 13, wherein the second switches and the fourth switches are respectively disposed on left and right sides of the bistable display panel, so as to be respectively coupled to the scan lines. 15. The bistable display according to claim 4, wherein the first switches and the third switches are disposed on the upper side or the lower side of the bistable display panel at the same time, so as to respectively couple the data lines . 16. The bistable display according to claim 15, wherein the second switches and the fourth switches are arranged on the left side or the right side of the bistable display panel at the same time, so as to respectively couple the scan lines . 17. The bistable display of claim 2, further comprising: A timing controller, coupled to the active driving module, the common voltage generator, the reset module and the switching module, for controlling the active driving module, the common voltage generator, the reset The mod works with the switch mod. 18. The bistable display according to claim 1, wherein the bistable display is at least a cholesteric liquid crystal display, and the bistable display panel is at least a cholesteric liquid crystal display panel.

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