CN103226460B - Multichannel analogue multiply-divide arithmetic circuit - Google Patents

Abstract

The invention relates to analog integrated circuit technology, in particular to a multi-channel analog multiplication and division operation circuit. The invention discloses a multi-channel analog multiplication and division operation circuit. The technical solution adopted is that the multi-channel analog multiplication and division operation circuit includes: transistor Q _k , transistor Q' _k , k=0, 1..n, transistor M _i,j , transistor M' _i,j , i=k+1| _k=0,1..n‑1 , j=1,2, op amp and resistor. The circuit structure of the present invention can realize the multiplication and division operation of multi-channel analog signals, and the current _I'n satisfies the relational expression The invention has the characteristics of small output result temperature coefficient and simple circuit structure. The input and output of the present invention are both current signals, which belong to the current type analog multiplication and division operation circuit, have no Miller effect, and the operation speed is fast.

Description

Multi-channel analog multiplication and division operation circuit

technical field

The invention relates to analog integrated circuit technology, in particular to a multi-channel analog multiplication and division operation circuit.

Background technique

The analog multiplication and division circuit is used to realize the multiplication and division operation function between analog quantities. It can not only be used for the calculation of analog quantities, but also widely used in communication systems, measurement systems, control systems and other fields to convert analog signals. and processing.

Most commonly used analog multipliers use Gilbert units, as shown in Figure 1. The circuit controls the current i _EE of the current source Q3 by Vin2, and the change of i _EE leads to the change of the transconductance gm of Q1 and Q2, so this circuit is also called a variable transconductance analog multiplier. The circuit output V _O is:

V _O = -Kv _x v _y , where where V _T is the thermal voltage, which is temperature dependent.

Because the coefficient of the output V _O of this circuit contains the quantity V _{T proportional to the absolute temperature,} the temperature characteristic is poor, and the input and output are voltage signals, there is Miller effect, and the operation speed is slow.

Most analog division circuits use analog multiplier units, which are connected as shown in Figure 2. Therefore, the problems existing in the analog multiplier still exist in the analog divider, and the circuit structure is complicated. To realize the multiplication and division operation of multi-channel analog signals, it is necessary to cascade the analog multipliers and dividers, which further increases the complexity of the circuit.

Contents of the invention

The technical problem to be solved by the present invention is to provide a multi-channel analog multiplication and division operation circuit, which realizes multi-channel analog signal multiplication and division operation, simplifies circuit design, improves operation speed and reduces the influence of temperature on output results.

The present invention solves the technical problem, and adopts the technical scheme that a multi-channel analog multiplication and division operation circuit includes: transistor Q _k , transistor Q' _k , k=0,1..n, transistor M _i,j , transistor M ' _i,j , i=k+1| _k=0,1..n-1 , j=1,2, operational amplifier and resistance; It is characterized in that, described multi-channel analog multiplication and division operation circuit has a symmetrical structure, Transistor Q _k has the same structure as transistor Q' _k , and its position is symmetrical; transistor M _i, j has the same structure as transistor M' _i,j , and its position is symmetrical; the emitter of transistor Q _k is connected to the gate of transistor M _i,1 , and transistor Q' _k The emitter is connected to the gate of transistor M'_i,1; the source of transistor M _i,1 is connected to the drain of transistor M _i,2 and the base of transistor Q _i , and the source of transistor M' _i,1 is connected to transistor M' _{i ,2} The drain is connected to the base of the transistor Q'_i; the bias current I _Bi and I' _Bi are respectively input by the transistor M _i,1 and the transistor M' _i,1 , the emitter of the transistor Q _k is connected to the current I _k , the transistor The emitter of Q' _k is connected to the current I' _k , the emitter of transistor Q' _n is grounded through a resistor, the collector of transistor Q _k and transistor Q' _k is connected to the reference level, and the output terminal of the op amp is connected to transistor Q ₀ and transistor Q' ₀ The base of the operational amplifier, and the two input terminals of the operational amplifier are respectively connected to the emitter of the transistor _Qn and the transistor _Q'n .

Preferably, the operational amplifier is an output rail-to-rail operational amplifier.

Specifically, the multi-channel analog multiplication and division operation circuit is a current-type analog multiplication and division operation circuit.

Further, the transistor M _i,j and the transistor M' _i,j are field effect transistors or bipolar transistors.

Further, the transistor Q _k and the transistor Q' _k are NPN transistors or PNP transistors.

The beneficial effect of the present invention is that multiplication and division operations of multiple analog signals can be performed, the temperature coefficient of the output result is small, the circuit structure is simple, and the input and output are both current signals. The circuit of the invention belongs to the current type analog multiplication and division operation circuit, has no Miller effect, and has high operation speed.

Description of drawings

Fig. 1 is a traditional analog multiplier circuit diagram;

Fig. 2 is a circuit diagram of a traditional analog divider;

Fig. 3 is the circuit diagram of embodiment 1;

Fig. 4 is embodiment 2 circuit diagrams;

Fig. 5 is the circuit diagram of embodiment 3;

Fig. 6 is the current relationship curve of the circuit shown in Fig. 5;

FIG. 7 is a graph showing the relationship between output current and temperature of the circuit shown in FIG. 5 .

detailed description

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

The multi-channel analog multiplication and division operation circuit of the present invention includes: transistor Q _k , transistor Q' _k , k=0,1..n, transistor M _i,j , transistor M' _i,j , i=k+1| _k=0,1..n-1 , j=1,2, operational amplifiers and resistors. The structure of the multi-channel analog multiplication and division operation circuit of the present invention is symmetrical, and the transistor _{Qk and the transistor Q'k have} the same structure and parameters, and are located in the symmetrical position of the circuit. Transistor Q _k and transistor Q' _k can be NPN transistors or PNP transistors. The transistor M _i,j and the transistor M' _i,j also have the same structure and parameters, and are also located in a symmetrical position of the circuit. Transistors M _i,j and transistors M' _i,j may be field effect transistors or bipolar transistors. In terms of circuit connection, the emitter of transistor Q _k is connected to transistor M _i,1 , the emitter of transistor Q' _k is connected to transistor M'_i,1; transistor M _i,1 is connected to transistor M _i,2 , and transistor M' _i1 is connected with transistor M' _i2 . The bias current I _Bi and I' _Bi are input by the transistor _{Mi1 and the transistor M' i1 respectively} , the emitter of the transistor Q _k is connected to the current I _k , the emitter of the transistor Q' _k is connected to the current I' _k , and the transistor Q' _n emits The electrode is grounded through a resistor, and the transistor _Qk and transistor _Q'k collectors are connected to the reference level. The connection of the transistor _Qk and the transistor _Q'k collector in the present invention is not strictly regulated, and the reference level can be the power supply voltage. The connection point between the output terminal of the operational amplifier and the bases of the transistor Q0 and the transistor _{Q'0 is} a symmetrical point of the circuit of the present invention, and the two input terminals of the operational amplifier are respectively connected to the emitters of the transistor _Qn and the transistor _Q'n . In the multi-channel analog multiplication and division operation circuit of the present invention, the current I' _n satisfies the relational expression $I_{\mathrm{no}}^{\′}=\frac{{\Π}_{k=0}^{\mathrm{no}}{I}_k}{{\Π}_{k=0}^{\mathrm{no}-1}{I}_k^{\′}}.$

When the transistors Q _k and Q' _k are NPN transistors, and the transistors M _i,j and M' _i,j are field effect transistors N-type field effect transistors (NMOS transistors), the circuit connection mode is shown in FIG. 3 . When the transistor Q _k and the transistor Q' _k are PNP transistors, and the transistor M _i,j and the transistor M' _i,j are PMOS transistors, the circuit connection mode is shown in FIG. 4 .

Example 1

Referring to Fig. 3, when the transistor Q _k and the transistor Q' _k are NPN transistors, and the transistor M _i,j and the transistor M' _i,j are NMOS transistors, the circuit connection relationship in this example is that the emitter of the transistor Q _k is connected to The negative terminal of the current I _k and the gate of the transistor Mi _{,1 ,} the drain of the transistor Mi,1 is connected to the positive terminal of the bias current I _Bi and the gate of the transistor Mi _,2 . The source of transistor M _i,1 is connected to the drain of transistor M _i,2 and the base of transistor Q _i . The emitter of the transistor _Q'k is connected to the negative terminal of the input current _I'k and the gate of the transistor _{M'i,1 ,} and the drain of the transistor M'i,1 is connected to the positive terminal of the bias current _I'Bi and the transistor The gate of M'i _,2 , the source of transistor _M'i,1 is connected to the drain of transistor _{M'i ,2} and the base of Q'i. The emitter of the transistor Q _n is connected to the negative terminal of the current I _n and the inverting input terminal of the op amp A, the emitter of the transistor Q' _n is connected to the same input terminal of the op amp A and one end of the resistor R, and the resistor R The other end, the positive end of the current I _k , the positive end of the current I' _k , the transistor M _i,2 and the source of the transistor M' _i,2 are all grounded. The output terminal of the operational amplifier A is connected to the bases of the transistor _Q0 and the transistor _Q'0 . where k=0,1..n, i=k+1 | _k=0,1..n-1 , j=1,2.

In this embodiment, bias current I _Bi =I' _Bi , and M _ij and M' _ij tubes have the same type, structure and parameters, and transistor Q _k and transistor Q' _k have the same structural parameters. By reducing the width-to-length ratio of the transistor M _i,2 and the transistor M' _i,2 , the transistor M _i,1 and the transistor M' _i,1 work in the saturation region, so the current-voltage formula of the MOS transistor saturation region can be obtained

$V_{GS\left(m_{i1}\right)}=\sqrt{\frac{2I_{Bi}}{{\mathrm{\μ}}_{\mathrm{no}}{C}_{ox}\frac{W}{L}}}+V_T,V_{GS\left(m_{i1}^{\′}\right)}=\sqrt{\frac{2I_{Bi}^{\′}}{{\mathrm{\μ}}_{\mathrm{no}}{C}_{ox}\frac{W}{L}}}+V_T,$ Where i=k+1| _k=0,1..n-1 , μ _n is the electron mobility, and C _OX is the capacitance of the gate oxide layer.

From the bias current I _Bi = I' _Bi , get

And by the triode current voltage formula have to

$V_{be\left(Q_k\right)}=V_{T}l\mathrm{no}\frac{I_k}{I_{\mathrm{the\; s}\left(Q_k\right)}},V_{be\left(Q_k^{\′}\right)}=V_{T}l\mathrm{no}\frac{I_k^{\′}}{I_{\left(Q_k^{\′}\right)}},$ Among them k=0,1..n, I _S is the saturation current.

The input terminal of op amp A has a virtual short characteristic, and the emitter voltages of transistors _Qn and _Q'n are the same, so

${\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}\mathrm{<span\; class="notranslate">\; e</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}\mathrm{<span\; class="notranslate">\; e</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; )</span>}$

because $V_{GS\left(m_{i1}\right)}=V_{GS\left(m_{i1}^{\&prime;}\right)},$ which is

$\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\overset{\mathrm{<span\; class="notranslate">\; no</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; m</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; )</span>}$

so

$\underset{k=0}{\overset{\mathrm{no}}{\&Sigma;}}{V}_{be\left(Q_k\right)}=\underset{k=0}{\overset{\mathrm{no}}{\&Sigma;}}{V}_{be\left(Q_k^{\&prime;}\right)}$ then

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; \&Pi;</span>}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}{<span\; class="notranslate">\; \&Pi;</span>}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; )</span>}}{{<span\; class="notranslate">\; \&Pi;</span>}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}^{<span\; class="notranslate">\; \&prime;</span>}{<span\; class="notranslate">\; \&Pi;</span>}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; )</span>}}$

When transistors Q _k and Q' _k are of the same type and size, At this time there is

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; =</span>\frac{{<span\; class="notranslate">\; \&Pi;</span>}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}}{{<span\; class="notranslate">\; \&Pi;</span>}_{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}^{<span\; class="notranslate">\; \&prime;</span>}}$

The multiplication and division operation function of multiple analog signals is realized, and the output signal does not contain the temperature-related quantity V _T .

Example 2

When transistor Q _k and transistor Q' _k are PNP transistors, and transistor M _{i, j} and transistor M' _{i, j} are P-type field effect transistors (PMOS transistors), the multi-channel analog multiplication and division operation circuit of the present invention is specifically connected The relationship is shown in Figure 4, and the current I' _n also satisfies the relationship

Example 3

FIG. 5 is a specific implementation circuit of a multi-channel analog multiplication and division operation circuit of the present invention for multiplication and division of three-way analog signals, which is a special case when n=1 in the circuit shown in FIG. 3 . In this embodiment, through the cascode structure, the field effect transistors M ₃ , M ₄ and M ₅ , M ₆ respectively mirror the bias current I _B flowing through the field effect transistors M ₁ , M ₂ to obtain the mirror current I _B1 and _I'B1 . Set the bias current I _B ＝5μA, I _B :I _B1 :I' _B1 ＝1:1:1, and the gain of operational amplifier A is 80dB. The input current I' ₀ = 5μA, I ₁ takes a value every 2μA between 2μA and 10μA, and the change of the output current I' ₁ with I ₀ is scanned.

Figure 6 shows the output of the scan. From the data intercepted in Figure 6, it can be seen that the current signals satisfy Relationship.

FIG. 7 is a temperature characteristic curve of the output current I' ₁ under the conditions of I ₀ =6 μA, I ₁ =10 μA, and I' ₀ =5 μA. It can be seen from the curve that at -40°C, the output current I' ₁ =11.82uA; at 125°C, the output current I' ₁ =11.92uA. In the temperature range of -40°C to 125°C, the output current change caused by temperature change is less than 1%.

In summary, the multi-channel analog multiplication and division operation circuit of the present invention realizes the multi-channel analog signal multiplication and division operation, has a small output current temperature coefficient, simple circuit implementation, and fast operation speed.

Claims (5)

1. multichannel analogue multiply-divide arithmetic circuit, including: transistor Q_k, transistor Q'_k, k=0,1..n, transistor M_i,j, brilliant Body pipe M'_i,j, i=k+1 |_K=0,1..n-1, j=1,2, amplifier and resistance；It is characterized in that, described multichannel analogue multiply-divide arithmetic circuit has There are symmetrical structure, transistor Q_kWith transistor Q'_kStructure is identical, positional symmetry, transistor M_i,jWith transistor M'_i,jStructure phase With, positional symmetry；Transistor Q_kEmitter stage and transistor M_i,1Grid connects, transistor Q'_kEmitter stage and transistor M'_i,1Grid Connect；Transistor M_i,1Source electrode and transistor M_i,2Drain electrode and transistor Q_iBase stage connects, transistor M'_i,1Source electrode and transistor M'_i,2 Drain electrode and transistor Q'_iBase stage connects；Bias current I_Bi、I'_BiRespectively by transistor M_i,1With transistor M'_i,1Input, transistor Q_k Emitter stage meet electric current I_k, transistor Q'_kEmitter stage meet electric current I'_k, transistor Q'_nEmitter stage passes through resistance eutral grounding, transistor Q_k With transistor Q'_kColelctor electrode connects datum, and amplifier outfan connects transistor Q₀With transistor Q'₀Base stage, two of amplifier Input connects transistor Q respectively_nWith transistor Q'_nEmitter stage.

Multichannel analogue multiply-divide arithmetic circuit the most according to claim 1, it is characterised in that described amplifier is rail-to-rail for output Amplifier.

Multichannel analogue multiply-divide arithmetic circuit the most according to claim 1, it is characterised in that described multi-channel analog multiplication and division is transported Calculating circuit is that current mode simulates multiplication and division computing circuit.

Multichannel analogue multiply-divide arithmetic circuit the most according to claim 1, it is characterised in that described transistor M_i,jAnd crystal Pipe M'_i,jFor FET or bipolar transistor.

Multichannel analogue multiply-divide arithmetic circuit the most according to claim 1, it is characterised in that described transistor Q_kAnd crystal Pipe Q'_kFor NPN transistor or PNP transistor.