CN103106063B - A kind of simulation multiplication and division computing circuit - Google Patents

Abstract

An analog multiplication and division operation circuit belongs to the field of analog circuits. It consists of four Darlington transistors or a transistor composed of Darlington-connected triodes, three input current sources and one output current. When the four transistors are of NPN (or PNP) type, the positive (or negative) terminal of the first input current source is connected to the bases of the first and second transistors and the collector of the fourth transistor, and the base of the fourth transistor is connected to the first The emitter of a transistor is connected to the negative (or positive) terminal of the second input current source, the emitter of the second transistor is connected to the base of the third transistor and the negative (or positive) terminal of the third input current source, and the third transistor and The emitter of the fourth transistor is grounded (or connected to the power supply Vcc), and the output current io is output from the collector of the third transistor. The invention realizes the multiplication and division operation function of two-way or three-way analog signals, has simple structure, small output signal temperature coefficient and fast operation speed, and is suitable for integrated chips of Bipolar, BiCMOS and BCD technology.

Description

An analog multiplication and division operation circuit

technical field

The invention belongs to the field of analog circuits, and in particular relates to an analog multiplication and division operation circuit.

Background technique

The analog multiplication and division circuit is used to realize the function of multiplication or division between two analog quantities. It can be used not only for the operation of analog quantities, but also for the conversion and processing of analog signals. Therefore, it is widely used in communication systems , measurement systems, control systems and other fields,

Most commonly used analog multipliers use Gilbert units, as shown in Figure 3 of the specification. The circuit controls the mirror current i _EE of the transistor Q3, and the change of i _EE leads to the change of the transconductance g _m of the transistor Q1 and the transistor Q2, so the circuit is also called a variable transconductance analog multiplier. circuit output

${\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; Kv</span>}}_{\mathrm{<span\; class="notranslate">\; x</span>}}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; RV</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}$

Because the coefficient of the output Vo of this circuit contains the quantity V _T proportional to the absolute temperature, the temperature characteristic is poor, and the input and output are voltage signals, there is Miller effect, and the operation speed is slow.

Most analog division circuits use analog multiplier units, which are connected in the form shown in Figure 4. Therefore, the problems existing in the analog multiplier still exist in the analog divider, and the circuit structure is complicated. To realize the multiplication and division operation of the three-way analog signal, it is necessary to cascade the analog multiplier and divider, which further increases the complexity of the circuit.

Contents of the invention

In order to solve the problems of slow operation speed and complicated circuit of the traditional analog multiplication/division device, the invention proposes an analog multiplication and division operation circuit. The circuit can perform multiplication or division operations on two analog signals, and can also perform multiplication and division operations on three analog signals. The circuit implementation method is simple, the temperature coefficient of the output result is small, and the operation speed is fast.

Technical scheme of the present invention is:

An analog multiplication and division operation circuit, as shown in Figures 1 and 2, comprises four transistors 11, 12, 13 and 14, three input current sources and an output current io; the four transistors are Darlington tubes Or it is composed of a triode connected by Darlington;

When the four transistors are NPN transistors (as shown in Figure 1), the positive terminal of the first input current source is connected to the bases of the first transistor 11 and the second transistor 12, and is connected to the collector of the fourth transistor 14 at the same time. The base of four transistors 14 is connected to the emitter of the first transistor and the negative terminal of the second input current source, the emitter of the second transistor 12 is connected to the base of the third transistor 13 and the negative terminal of the third input current source, and the third The emitters of the transistor 13 and the fourth transistor 14 are grounded, and the output current io is output from the collector of the third transistor 13;

When the four transistors are PNP transistors (as shown in Figure 2), the negative terminal of the first input current source is connected to the bases of the first transistor 11 and the second transistor 12, and is connected to the collector of the fourth transistor 14 at the same time. The base of four transistors 14 is connected to the emitter of the first transistor and the positive terminal of the second input current source, the emitter of the second transistor 12 is connected to the base of the third transistor 13 and the positive terminal of the third input current source, and the third The emitters of the transistor 13 and the fourth transistor 14 are connected to the power supply Vcc, and the output current io is output from the collector of the third transistor 13 .

It should be noted:

1. The four transistors 11-14 in the analog multiplication and division operation circuit of the present invention can be Darlington transistors or Darlington connections formed by triodes.

2. The analog multiplication and division operation circuit of the present invention is a current input and output type analog multiplication and division operation circuit

Beneficial effects of the present invention: Compared with the commonly used multiplication/divider, the analog multiplication and division operation circuit provided by the present invention has a simpler circuit structure, a smaller temperature coefficient of the output result, and the input and output are current signals, without Miller effect, and the operation speed Fast, suitable for integrated chips based on Bipolar, BiCMOS and BCD processes.

Description of drawings

Fig. 1 is a kind of analog multiplication and division operation circuit of the present invention realizes the circuit with NPN transistor.

Fig. 2 is a PNP transistor realization circuit for an analog multiplication and division operation circuit of the present invention.

Figure 3 is a traditional analog multiplier.

Figure 4 is a traditional analog divider.

Fig. 5 is a current relation curve of a circuit for implementing the present invention.

Fig. 6 is the relationship curve between the output current and the temperature of the specific implementation circuit of the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and taking an NPN transistor as a specific embodiment.

An analog multiplication and division operation circuit, as shown in Figure 1, includes four transistors 11, 12, 13 and 14, three input current sources and an output current io; the four transistors are all Darlington tubes or It is composed of a triode connected by Darlington;

The four transistors are NPN type transistors, the positive terminal of the first input current source is connected to the bases of the first transistor 11 and the second transistor 12, and is connected to the collector of the fourth transistor 14 at the same time, and the base of the fourth transistor 14 is connected to the first The emitter of the transistor and the negative terminal of the second input current source, the emitter of the second transistor 12 is connected to the base of the third transistor 13 and the negative terminal of the third input current source, the emitter of the third transistor 13 and the fourth transistor 14 The pole is grounded, and the output current io is output from the collector of the third transistor 13 .

The working principle of the present invention is set forth below:

by the formula $I_o=I_{\mathrm{the\; s}}\exp \left(\frac{q{V}_{\mathrm{be}}}{\mathrm{kT}}\right)$ And I _o ＝I _c /3, get

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; ,</span>$ ${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 111</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 111</span>}<span\; class="notranslate">\; )</span>}}$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; ,</span>$ ${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 112</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 112</span>}<span\; class="notranslate">\; )</span>}}$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; ,</span>$ ${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 113</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 113</span>}<span\; class="notranslate">\; )</span>}}$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; io</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; ,</span>$ ${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; be</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 114</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{\mathrm{<span\; class="notranslate">\; q</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\frac{\mathrm{<span\; class="notranslate">\; io</span>}}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 114</span>}<span\; class="notranslate">\; )</span>}}$

because

V _be(101) +V _be(111) +V _be(102) +V _be(112) ＝V _be(103) +V _be(113) +V _be(104) +V _be(114)

then

${\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 113</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 114</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}}{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 111</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 112</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}}$

When 101~104 and 111~114 are the same type of transistors and are completely matched, and 101~104 work in the flat area of β in the I ₃ -β curve, β has almost nothing to do with the current.

$\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 113</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 114</span>}<span\; class="notranslate">\; )</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 111</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 112</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 103</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 104</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 113</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 114</span>}<span\; class="notranslate">\; )</span>}}{{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 101</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 102</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 111</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; no</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 112</span>}<span\; class="notranslate">\; )</span>}}$

Where n ₍₁₀₁₎ ~n ₍₁₀₄₎ n ₍₁₁₁₎ n ₍₁₁₄₎ are the numbers of transistors 101~104, 111~114 respectively. but

${\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&CenterDot;</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; a</span>}}}$

The coefficient k1 is only related to the number of 101~104,111~114, and has nothing to do with the temperature.

When the input currents i1, i2 and i3 of the three input current sources are all variable inputs, the circuit realizes the analog multiplication and division of the three analog input signals.

When the input current i3 of the third input current source is a fixed bias current, the circuit realizes the analog multiplication of two analog signals, the output i _o =k2·i ₁ ·i ₂ , k2=k1/i ₃ .

When the input current i1 of the first input current source or the input current i2 of the second input current source is a fixed bias current, the circuit realizes the analog division of two analog signals, and the output

i _o =k3·i ₁ /i ₃ , k3=k1·i ₂ or i _o =k3·i ₂ /i ₃ , k3=k1·i ₁ .

Carry on the simulation to the electric current relation of i1, i2, i3, io. Figure 5 shows the number of transistors 101~104, 111~114 as 1, i3=1.5uA, i2 takes a value every 500nA between 500nA~3uA, and the output current io changes with i1 obtained by scanning. It can be seen from the figure that the current i1, i2, i3, and io satisfy the relationship Here k=1.

Fig. 6 is the relationship curve of output current io and temperature. In the specific implementation circuit diagram shown in Figure 1, the simulation parameters are set as follows: the number of transistors 101~104, 111~114 is 1, i1=3uA, i2=2uA, i3=1.5uA. It can be seen from the curve that the output current io=3.94uA at -40°C; at 125°C, the output current io=4.173uA. In the temperature range of -40°C~125°C, the output current change caused by temperature change is less than ±3%.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (1)

1. simulate a multiplication and division computing circuit, comprise four transistors (11,12,13 and 14), three input current sources and an output current io; Described four transistors are Darlington transistor;

When four transistors are NPN transistor, the positive termination the first transistor (11) of the first input current source and the base stage of transistor seconds (12), connect the collector of the 4th transistor (14) simultaneously, the base stage of the 4th transistor (14) connects the emitter of the first transistor and the negative terminal of the second input current source, the emitter of transistor seconds (12) connects the base stage of third transistor (13) and the negative terminal of the 3rd input current source, the grounded emitter of third transistor (13) and the 4th transistor (14), output current io exports from the collector of third transistor (13),

When four transistors are PNP transistor, the negative terminal of the first input current source connects the base stage of the first transistor (11) and transistor seconds (12), connect the collector of the 4th transistor (14) simultaneously, the base stage of the 4th transistor (14) connects the emitter of the first transistor and the anode of the second input current source, the emitter of transistor seconds (12) connects the base stage of third transistor (13) and the anode of the 3rd input current source, the emitter of third transistor (13) and the 4th transistor (14) connects power Vcc, output current io exports from the collector of third transistor (13),

When input current i1, i2, i3 of three input current sources are variable input, the simulation multiplication and division computing of this circuit realiration Liao Dui tri-road analog input signal;

When the input current i3 of the 3rd input current current source is fixing bias current, the analogue multiplication computing of this circuit realiration to two-way simulating signal;

When the input current i1 of the first input current source or the input current i2 of the second input current source is fixing bias current, the simulation division computing of this circuit realiration to two-way simulating signal.