CN103219379B - A kind ofly adopt device with high electron mobility of first grid technique and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of high electron mobility devices, and in particular relates to a high electron mobility device using a gate-first process and a preparation method thereof. The invention adopts the gate-first process to prepare high electron mobility devices, uses the gate sidewall to realize the self-alignment of the gate and source positions, reduces the drift of product parameters, and at the same time, because the gate is protected by a passivation layer, The source and drain of the device can be formed by an alloying process after the gate is formed, which reduces the source and drain contact resistance and enhances the electrical performance of the high electron mobility device.

Description

A high electron mobility device using a gate-first process and its preparation method

technical field

The invention relates to a high electron mobility device, in particular to a high electron mobility device using a gate-first process and a preparation method thereof, belonging to the field of high electron mobility devices.

Background technique

High Electron Mobility Transistors (HEMTs) are generally considered to be one of the most promising high-speed electronic devices. Due to the characteristics of ultra-high speed, low power consumption, and low noise (especially at low temperature), it can greatly meet the special needs of ultra-high-speed computers, signal processing, satellite communications, etc., so HEMT devices are widely valued. As a new generation of microwave and millimeter wave devices, HEMT devices show unparalleled advantages in terms of frequency, gain and efficiency. After more than 10 years of development, HEMT devices have already possessed excellent microwave and millimeter-wave characteristics, and have become the main devices of microwave and millimeter-wave low-noise amplifiers in the fields of 2-100 GHz satellite communications and radio astronomy. At the same time, HEMT devices are also the core components used to make microwave mixers, oscillators and broadband traveling wave amplifiers.

At present, GaN-based HEMT RF power devices are mostly manufactured using the gate-last process, and the manufacturing process mainly includes: firstly, source and drain electrodes are manufactured. Photolithographic ohmic contact window, using electron beam evaporation to form a multilayer electrode structure, and lift-off process to form source and drain contacts, using rapid thermal annealing (RTA) equipment to form good source and drain under 900 ° C and 30 Sec argon protection conditions ohmic contact. Then photoetch out the area to be etched, and use reactive ion beam etching (RIE) equipment to pass in boron chloride to etch the steps. Finally, the Schottky barrier metal is formed again using photolithography, electron beam evaporation and lift-off process. However, as the size of the device shrinks, it is difficult to achieve precise alignment of the gate, source, and drain of the HEMT device by this gate-last process method, resulting in drift of product parameters.

Contents of the invention

The purpose of the present invention is to propose a high electron mobility device using gate-first technology and its preparation method, so as to realize the self-alignment of the gate and source positions of the high electron mobility device, reduce the drift of product parameters, and enhance Electrical properties of high electron mobility devices.

A high electron mobility device using a gate-first process proposed by the present invention includes:

A gallium aluminum nitride buffer layer, a gallium nitride channel layer, and a gallium aluminum nitride isolation layer are sequentially formed on the substrate;

a gate dielectric layer formed on the aluminum gallium nitride isolation layer;

a gate formed on the gate dielectric layer and a passivation layer on the gate;

gate spacers formed on both sides of the gate;

a drain and a source formed on both sides of the gate on the aluminum gallium nitride isolation layer;

On the gate dielectric layer, an insulating dielectric layer formed between the gate spacer near the drain and the drain;

The field plate connected to the source formed by covering the gate spacer near the drain side, and in the channel length direction of the device, the field plate faces the insulating dielectric layer and is located between the gate extending above the passivation layer.

The present invention also proposes a method for preparing the high electron mobility device using the gate-first process, and the specific steps are as follows:

Depositing an aluminum gallium nitride buffer layer, a gallium nitride channel layer, and an aluminum gallium nitride isolation layer in sequence on the substrate;

Perform active area photolithography, use photoresist as an etching barrier layer, sequentially etch the aluminum gallium nitride isolation layer, gallium nitride channel layer, and aluminum gallium nitride buffer layer to form the active area, and then remove the glue;

sequentially depositing a first layer of insulating film, a first layer of conductive film, and a second layer of insulating film on the exposed surface of the formed structure;

Perform photolithography and development to define the position of the gate of the device;

Using photoresist as an etching barrier layer, etch away the exposed second layer of insulating film and first layer of conductive film in sequence, and then remove the glue, and the unetched first layer of conductive film and second layer of insulating film are formed The gate of the device and the passivation layer over the gate;

Deposit a third layer of insulating film on the exposed surface of the formed structure, and define the position of the source and drain of the device by photolithography process, and then use photoresist as an etching barrier layer to etch away the exposed The third layer of insulating film;

Next, continue to etch away the exposed first layer of insulating film to expose the formed aluminum gallium nitride isolation layer, and then remove the glue, and the remaining third layer of insulating film forms the gate spacer and the insulating film on both sides of the gate. an insulating dielectric layer between the gate spacer and the drain near the drain;

Form the source and drain of the device on the exposed aluminum gallium nitride isolation layer through the lift-off process and alloying process;

A field plate connected to the source is formed by covering the side wall of the gate close to the drain, and in the channel length direction of the device, the field plate faces the formed insulating dielectric layer and the passivation layer above the gate. Extend up.

As mentioned above, the preparation method of the high electron mobility device adopting the gate-first process, the first layer of insulating film is silicon oxide, silicon nitride, hafnium oxide or aluminum oxide, and the second layer of insulating film is The thin film and the third insulating film are silicon oxide or silicon nitride.

According to the method for manufacturing a high electron mobility device using a gate-first process, the first layer of conductive film is an alloy containing chromium, or nickel, or tungsten.

The invention adopts the gate-first process to manufacture high electron mobility devices, uses the gate sidewall to realize the self-alignment of the gate and source positions, reduces the drift of product parameters, and at the same time, because the gate is protected by a passivation layer, The source and drain of the device can be formed by an alloying process after the gate is formed, which reduces the source and drain contact resistance and enhances the electrical performance of the high electron mobility device.

Description of drawings

FIG. 1 is a cross-sectional view of an embodiment of a high electron mobility device using a gate-first process disclosed in the present invention. Wherein, FIG. 1a is a schematic top view of the high electron mobility device using the gate-first process, and FIG. 1b is a cross-sectional view of the structure shown in FIG. 1a along the direction AA.

2 to 6 are process flow charts of an embodiment of a method for manufacturing a high electron mobility device using a gate-first process disclosed in the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. In the drawings, for the convenience of illustration, the thicknesses of layers and regions are enlarged or reduced, and the sizes shown do not represent actual sizes. Although these figures do not fully reflect the actual size of the device, they still completely reflect the mutual positions between the regions and the constituent structures, especially the upper-lower and adjacent relationships between the constituent structures.

Figure 1 is an embodiment of a high electron mobility device using a gate-first process proposed by the present invention, wherein Figure 1a is a schematic top view of the high electron mobility device, and Figure 1b is a schematic view of the structure shown in Figure 1a along the AA direction Sectional view. As shown in FIG. 1 , the substrate includes a substrate 200 and a gallium nitride buffer layer 201 formed on the substrate 200. On the gallium nitride buffer layer 201, a gallium aluminum nitride buffer layer 202 and a gallium nitride channel are sequentially formed. layer 203 and aluminum gallium nitride spacer layer 204 . A gate dielectric layer 205 is formed on the AlGaN isolation layer 204 , and a gate 206 of the device and a passivation layer 207 on the gate 206 are formed on the gate dielectric layer 205 .

Gate spacers 208 a are formed on both sides of the gate 206 .

A source 209 and a drain 210 are respectively formed on the AlGaN isolation layer 204 and on both sides of the gate 206 .

On the gate dielectric layer 205, an insulating dielectric layer 208b is formed between the gate spacer 208a on the side close to the drain 210 and the drain 210. The gate spacer 208a and the insulating dielectric layer 208b can be made of an insulating material 208 At the same time, the insulating material 208 may be silicon oxide or silicon nitride.

A field plate 211 connected to the source 209 is formed covering the gate spacer 208a on the side close to the drain 210, and in the channel length direction of the device, the field plate 211 extends to the passivation layer 207 and the insulating dielectric layer 208b .

Also formed on the gate 206 and the drain 210 are a source contact 212 and a drain contact 213 for connecting the gate 206 and the drain 210 to external electrodes, respectively.

The following describes the process flow of an embodiment of the method for manufacturing a high electron mobility device using the gate-first process proposed by the present invention.

First, as shown in FIG. 2 , a gallium aluminum nitride buffer layer 202 with a thickness of about 40 nanometers, a gallium nitride channel layer 203 with a thickness of about 40 nanometers, and a gallium nitride channel layer 203 with a thickness of about 22 nanometers are sequentially deposited on the substrate Aluminum gallium nitride isolation layer 204, and then deposit a layer of photoresist on the aluminum gallium nitride isolation layer 204 and mask, expose, and develop to define the position of the active region, and then use the photoresist as an etching barrier The exposed AlGaN isolation layer 204, GaN channel layer 203, and AlGaN buffer layer 202 are sequentially etched away to form an active region, and then the photoresist is stripped. 2a is a schematic top view of the formed structure, and FIG. 2b is a cross-sectional view of the structure shown in FIG. 2a along the direction AA.

The substrate described in this embodiment includes a substrate 200 and a gallium nitride buffer layer 201 formed on the substrate 200, and the substrate 200 may be silicon, silicon carbide or aluminum oxide.

Next, a first layer of insulating film 205, a first layer of conductive film and a second layer of insulating film are sequentially deposited on the exposed surface of the formed structure, and a layer of photoresist is deposited on the second layer of insulating film. Glue and mask, expose and develop to define the gate position of the device, and then use photoresist as an etching barrier layer to etch away the exposed second insulating film and the first conductive film in sequence, and the unetched The first layer of conductive film and the second layer of insulating film respectively form the gate 206 of the device and the passivation layer 207 on the gate, as shown in Figure 3 after stripping off the photoresist, where Figure 3a is the formed structure Figure 3b is a cross-sectional view of the structure shown in Figure 3a along the direction AA.

The first layer of insulating film 205 can be silicon oxide, silicon nitride, hafnium oxide or aluminum oxide, as the gate dielectric layer of the device, and its thickness is preferably 8 nanometers. The gate 206 may be an alloy containing chromium, or nickel, or tungsten, such as nickel-gold alloy, chromium-tungsten alloy, palladium-gold alloy, platinum-gold alloy, nickel-platinum-gold alloy or nickel-palladium-gold alloy. The passivation layer 207 can be silicon oxide or silicon nitride.

Next, deposit a third layer of insulating film 208 on the exposed surface of the formed structure, and deposit a layer of photoresist on the third layer of insulating film 208 and mask, expose, and develop to define the source of the device. The position of the electrode and the drain electrode, and then use photoresist as an etching barrier layer to etch away the exposed third insulating film 208.

Next, continue to etch away the exposed first insulating film 205 to expose the AlGaN isolation layer 204 . In the remaining third layer of insulating film 208, the insulating film 208 located on both sides of the gate 206 can form the gate spacer 208a of the device, and the insulating film 208 located between the gate 206 and the defined drain can form an interlayer. The insulating dielectric layer 208b between the gate spacer 208a on the side close to the drain and the drain, and the insulating film 208c part of the insulating film 208 on the passivation layer 207 can be used as a passivation layer on the gate 206. A part of the layer 207 is shown in FIG. 4 after stripping the photoresist, wherein FIG. 4a is a schematic top view of the formed structure, and FIG. 4b is a cross-sectional view of the structure shown in FIG. 4a along the direction AA.

As mentioned above, when the third insulating film 208 is etched, the part of the insulating film 208c located on the passivation layer 207 as a part of the passivation layer 207 located on the gate 206 can also be etched away. , as shown in Figure 4c.

Next, a layer of photoresist is deposited on the exposed surface of the formed structure and masked, exposed, and developed to define the positions of the source and drain of the device, and then through the lift-off process and alloying process in the nitriding The source electrode 209 and the drain electrode 210 of the device are formed on the gallium-aluminum isolation layer 204. The process is: first deposit a layer of conductive film, such as titanium/aluminum/nickel/gold alloy, and then remove the deposited film by a lift-off process. The conductive film on the photoresist, and the conductive film not deposited on the photoresist is retained, and then a good source and drain contact is formed by high temperature thermal annealing, as shown in Figure 5, where Figure 5a is the formed A schematic top view of the structure, and FIG. 5b is a cross-sectional view of the structure shown in FIG. 5a along the direction AA.

Finally, a new layer of photoresist is deposited on the exposed surface of the formed structure and the positions of the device field plate, gate, source and drain are defined by a photolithography process, and then a second layer of conductive film is deposited , the second conductive film can be titanium aluminum alloy, nickel aluminum alloy, nickel platinum alloy or nickel gold alloy. Then remove the second layer of conductive film deposited on the photoresist by lift-off process, and keep the second layer of conductive film that is not deposited on the photoresist, so as to close the gate on the drain electrode 210 side. The field plate 211 of the device is formed on the pole sidewall, and the field plate 211 is connected to the source 209, and the contact body 212 of the source electrode and the contact body 213 of the drain electrode are formed at the same time that the gate 206 and the drain electrode 210 are connected to the external electrodes, As shown in Figure 6.

As mentioned above, many widely different embodiments can be constructed without departing from the spirit and scope of the present invention. It should be understood that the invention is not limited to the specific examples described in the specification, except as defined in the appended claims.

Claims (3)

1. A method for preparing a high electron mobility device using a gate-first process, the high electron mobility device comprising: A gallium aluminum nitride buffer layer, a gallium nitride channel layer, and a gallium aluminum nitride isolation layer are sequentially formed on the substrate; a gate dielectric layer formed on the aluminum gallium nitride isolation layer; It is characterized in that it also includes: a gate formed on the gate dielectric layer and a passivation layer on the gate; gate spacers formed on both sides of the gate; a drain and a source formed on both sides of the gate on the aluminum gallium nitride isolation layer; On the gate dielectric layer, an insulating dielectric layer formed between the gate spacer near the drain and the drain; The field plate connected to the source formed by covering the gate spacer near the drain side, and in the channel length direction of the device, the field plate faces the insulating dielectric layer and is located between the gate Extended above the passivation layer; It is characterized in that the specific steps are as follows: Depositing an aluminum gallium nitride buffer layer, a gallium nitride channel layer, and an aluminum gallium nitride isolation layer in sequence on the substrate; Perform active area photolithography, use photoresist as an etching barrier layer, sequentially etch the aluminum gallium nitride isolation layer, gallium nitride channel layer, and aluminum gallium nitride buffer layer to form the active area, and then remove the glue; sequentially depositing a first layer of insulating film, a first layer of conductive film, and a second layer of insulating film on the exposed surface of the formed structure; Perform photolithography and development to define the position of the gate of the device; Using photoresist as an etching barrier layer, etch away the exposed second layer of insulating film and first layer of conductive film in sequence, and then remove the glue, and the unetched first layer of conductive film and second layer of insulating film are formed The gate of the device and the passivation layer over the gate; Deposit a third layer of insulating film on the exposed surface of the formed structure, and define the position of the source and drain of the device by photolithography process, and then use photoresist as an etching barrier layer to etch away the exposed The third layer of insulating film; Next, continue to etch away the exposed first layer of insulating film to expose the formed aluminum gallium nitride isolation layer, and then remove the glue, and the remaining third layer of insulating film forms the gate spacer and the insulating film on both sides of the gate. an insulating dielectric layer between the gate spacer and the drain near the drain; Form the source and drain of the device on the exposed aluminum gallium nitride isolation layer through the lift-off process and alloying process; A field plate connected to the source is formed by covering the side wall of the gate close to the drain, and in the channel length direction of the device, the field plate faces the formed insulating dielectric layer and the passivation layer above the gate. Extend up. 2. The method for preparing a high electron mobility device using a gate-first process as claimed in claim 1, wherein the first insulating film is silicon oxide, silicon nitride, hafnium oxide or dioxane Aluminum, the second insulating film and the third insulating film are silicon oxide or silicon nitride. 3 . The method for manufacturing a high electron mobility device using a gate-first process as claimed in claim 1 , wherein the first conductive film is an alloy containing chromium, nickel or tungsten. 4 .