CN103218304B - Off-chip distribution method in a kind of embedded memory data slice - Google Patents

Abstract

The present invention relates to off-chip distribution method in a kind of embedded memory data slice.On sheet, internal memory is as the key component of embedded system, directly affects the overall performance of system.Present invention firstly provides TCG model as weighing the new standard that data object causes Cache to lack, consider most key factor, such as data object size, life cycle, access times, temporal locality and spatial locality etc..Secondly propose SPM/Cache data distributing method and the data object being easiest to clash (TCG value is big) is assigned to SPM.Then data object big for TCG value is mapped to different Cache groups and avoids conflict by proposition fixing Cache data layout method.The inventive method makes internal memory hardware and the software run on it on sheet more mate, and reduces the time of routine access storage system, thus improving systematic entirety energy.

Description

A method for on-chip and off-chip allocation of embedded memory data

technical field

The invention belongs to the technical field of embedded memory. In particular, it relates to a method for on-chip and off-chip allocation of embedded memory data. The present invention can achieve optimal performance on specific memory configuration for specific applications, and is especially suitable for performance optimization of multimedia application programs on the hybrid memory structure of scratch pad memory/cache cache.

Background technique

Due to differences in manufacturing process and circuit logic structure, the speed of processor execution components has always been higher than the read and write speed of memory, and with the development of semiconductor process technology, the performance difference caused by this speed gap is gradually increasing. An important technology to solve the speed mismatch between the processor and the external memory is that the storage system adopts a layered design and integrates a small but faster memory on the chip to improve the system storage access performance.

As an important part of the embedded system, the on-chip memory structure directly affects key parameters such as system performance, power consumption, and cost. There are two types of on-chip memory structures: cache Cache and scratch pad memory SPM (Scratch-PadMemory). Compared with Cache, SPM consumes less area and power consumption per bit. Therefore, it is gradually becoming a trend to adopt a hybrid structure of SPM/Cache for the on-chip memory structure of embedded systems. However, the small capacity and specificity of SPM make how to effectively use on-chip memory resources a key issue in embedded system design.

Existing research on software data storage optimization mainly focuses on how to increase the command rate of Cache, or how to increase the number of SPM accesses, but there is a lack of research on data memory access optimization using the hybrid on-chip memory structure of Cache and SPM.

Data on-chip and off-chip allocation technology is an embedded system storage optimization technology. Using this technology, the on-chip and off-chip allocation strategy determines which data is accessed through SPM (called on-chip) and which data is accessed through Cache (called off-chip). Data on-chip and off-chip allocation technology optimizes the allocation of data between SPM and Cache, and can achieve the best performance for specific applications. It has become a hot spot in the research of embedded system storage optimization.

Contents of the invention

The object of the present invention is to provide a method for on-chip and off-chip allocation of embedded memory data in view of the deficiencies in the prior art, which can realize the optimal performance of specific application programs in specific memory configurations.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention comprises the following steps:

Step 1. Utilize compiler and emulator tools to extract specific application information;

Step 2. Build a TCG model on these information;

Step 3. Propose a data allocation method to allocate data objects with large TCG values to SPM;

Step 4. A data layout method is proposed to map data objects with large TCG values to different Cache groups to avoid conflicts.

The specific application information described in step 1 includes the size, life cycle, number of visits, temporal locality, and spatial locality of the data object; the temporal locality is represented by the temporal relationship graph TRG (TemporalRelationshipGraph); the spatial Locality is represented by the maximum number of consecutive accesses.

The TCG model described in step 2 includes the size, life cycle, number of visits, temporal locality and spatial locality factors of the data object extracted in step 1, and its model formula is as follows:

TCG=(number of visits*lifetime*TRG value)/(maximum number of consecutive visits*object size).

The data distribution method described in step 3 specifically includes the following steps:

3-1. Arrange all data objects in descending order of TCG values, initialize them, and then allocate them to off-chip memory as data objects to be allocated;

3-2. Among all the data objects to be allocated, select the first data object whose capacity is less than or equal to the remaining capacity of the pad memory in descending order, and allocate the data object to the on-chip scratch pad memory;

3-3. Step 3-2 is repeated until the capacity of all data objects to be allocated is greater than the remaining capacity of the scratch pad, then the process ends.

The data layout method described in step 4 includes the following steps:

4-1. Calculate the number of cache groups required by the data objects in the remaining data objects to be allocated. The calculation formula is as follows:

Number of groups = data object size / cache group size;

4-2. Assign the current group number of the cache to the data object, add one to the current group number of the cache, and decrease the number of groups required by the data object by one;

4-3. Repeat step 4-2 until the number of groups required for the data object is zero;

4-4. Repeat steps 4-1, 4-2 and 4-3 until all remaining data objects to be allocated are allocated.

The beneficial effects of the present invention are as follows:

The method of the present invention utilizes the TCG model to model the application program information, comprehensively considers the reasonable utilization of the SPM and the reasonable layout of the off-chip memory data objects, optimizes the data allocation between the SPM and the Cache, and reduces program consumption in data storage access time and reduce data storage access energy consumption, and realize the optimal performance of specific applications on specific memory configurations.

Description of drawings

Fig. 1 is the flowchart of the inventive method;

Fig. 2 is the TCG model structural diagram that the inventive method proposes;

Fig. 3 is the flow chart of the SPM/Cache data allocation method in the method of the present invention;

FIG. 4 is a flow chart of the fixed Cache data layout method in the method of the present invention.

detailed description

The present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

As shown in Figure 1, at first utilize compiler and emulator tool to extract the information of concrete application program in the present embodiment: 1. select the -O3 optimization option static compilation application program of GCC-2.7.1-MIPS compiler to obtain MIPS assembly code; ②Select the MIPS emulator to configure the on-chip memory, including capacity, access delay, and organization (replacement strategy, write strategy, write-miss strategy, and association method), etc., and open the performance statistics tool to simulate the data storage access performance of the program . Secondly, establish a TCG model for these information; then use the SPM/Cache data allocation method to allocate data objects with large TCG values to SPM; finally use the fixed Cache data layout method to map data objects with large TCG values to different Cache groups to avoid conflicts .

The specific application information includes the size, life cycle, access times, temporal locality and spatial locality of the data object; the temporal locality is represented by the temporal relationship graph TRG (TemporalRelationshipGraph); spatial locality It is represented by the maximum number of consecutive visits.

As shown in Figure 2, the described TCG model includes the size, life cycle, number of visits, temporal locality and spatial locality factors of the data object extracted in step 1, and its model formula is as follows:

TCG=(number of visits*lifetime*TRG value)/(maximum number of consecutive visits*object size).

Among them, the temporal relationship graph TRG (TemporalRelationshipGraph) and TRG values can be found in the reference text after the title of N.Gloy, T.Blockwell, M.D.Zorn paper title Procedure placement using temporal ordering information.

As shown in Figure 3, the purpose of the SPM/Cache data allocation in this embodiment is to allocate the most conflict-prone data objects to the SPM, including the following steps:

Step1. Arrange all data objects in descending order of TCG values, initialize them, and then allocate them to off-chip memory as data objects to be allocated;

Step2, among all data objects to be distributed, select the first data object satisfying capacity less than or equal to the remaining capacity of the pad memory in descending order, and distribute the data object to the on-chip scratch pad memory SPM;

Step 3. Repeat Step 2 until the capacity of all data objects to be allocated is greater than the remaining capacity of the scratch pad, then end.

As shown in Figure 4, the fixed Cache data layout in this embodiment has two goals: ① reduce the number of Cache misses; ② reduce the off-chip memory space (that is, reduce the holes in the off-chip memory after the data layout is completed), including the following step:

Step4. Calculate the number j of cache groups required for each data object in the remaining i data objects to be allocated. The calculation formula is as follows:

Number of groups j = data object size / cache group size;

Step5. Assign the current group number setNO of the cache to the data object, and add one to the current group number setNO of the cache, and decrease the number of groups j required by the data object by one;

Step6, repeat steps 4-5 until the required number of groups j of the data object is zero;

Step7. Repeat steps 4-4, 4-5 and 4-6 until the remaining i data objects to be allocated are all allocated.

Claims (1)

1. off-chip distribution method in an embedded memory data slice, it is characterised in that comprise the steps:

Step 1. utilizes compiler and simulator tool to extract the information of concrete application program；

These information are set up TCG model by step 2.；

Step 3. proposes data distributing method and data object big for TCG value is assigned to SPM；

Step 4. proposes data layout's method and data object big for TCG value is mapped to different Cache groups to avoid conflict；

The information of the concrete application program described in step 1, including the size of data object, life cycle, access times, temporal locality and spatial locality；Described temporal locality is to be represented by time chart TRG；Spatial locality is to be represented by maximum connected reference number of times；

TCG model described in step 2, its content includes the size of data object, life cycle, access times, temporal locality and the spatial locality factor that step 1 is extracted, and its model formation is as follows:

TCG=(access times * life cycle * TRG value)/(maximum connected reference number of times * object size)；

Data distributing method described in step 3, specifically includes following steps:

Total data object according to TCG value descending, and is initialized by 3-1., is then dispensed for off-chip internal memory, as data to be distributed object；

3-2., in all data to be distributed objects, selects first according to descending order and meets the capacity data object less than or equal to scratch-pad memory residual capacity, be assigned on sheet by this data object scratch-pad memory；

3-3. repeats step 3-2, until all data to be distributed object capacities are all higher than scratch-pad memory residual capacity, then terminates；

Data layout's method described in step 4 comprises the steps of:

4-1. calculates the cache set number that in residue data to be distributed object, data object needs, and computing formula is as follows:

Group number=data object size/cache set size；

Current for high-speed cache group number is distributed to data object by 4-2., and adds one by current for buffer memory group number, and data object required group number subtracts one simultaneously；

4-3. repeats step 4-2, until data object required group number is zero；

4-4. repeats step 4-1,4-2 and 4-3, until residue data to be distributed object is all assigned.