CN101989183A - Method for realizing energy-saving storing of hybrid main storage - Google Patents

Abstract

The invention discloses a method for realizing energy-saving storage of a mixed main memory, which comprises the following steps: constructing a mixed main memory with a phase change memory as the main memory and a dynamic random access memory as a buffer memory, and designing a read-write strategy adapted to the structure of the main memory , and read and write data in the disk and phase change memory according to the read and write strategy. The present invention improves the original main memory structure, fully utilizes the advantages of large capacity and low power consumption of the phase change memory and the low time delay of the dynamic random access memory, so that the hybrid main memory does not increase power consumption and time delay. It can achieve greater capacity under the environment, thereby reducing the number of accesses to the disk and realizing energy saving in storage.

Description

A method of hybrid main memory to realize energy-saving storage

Technical field

The invention relates to the field of storage and energy saving of embedded systems, in particular to a method for improving the main memory structure and read-write strategy to realize energy-saving storage.

Background technique

Memory is a very important part of a computer system and is used to store programs and data. The main memory is the storage space that the processor can directly address, and all programs and data must be loaded into the main memory to run. Therefore, the performance of the main memory directly affects the operating speed of the entire computer system. As the speed of the processor continues to increase, the read and write speed of the main memory is far behind the speed of the processor, which has gradually become a bottleneck for improving system performance. Therefore, how to maximize the capacity and read/write speed of the main memory without increasing the cost and energy consumption has always been a research hotspot.

The cache technology is proposed to solve the problem of slow read and write speed of the main memory. Because the speed of the processor is much faster than the access speed of the main memory, the processor often waits for the read and write of the main memory to complete before continuing to execute. This makes the performance of the processor not fully utilized. In order to alleviate the speed gap between the processor and the main memory, cache technology came into being. Cache is a special memory subsystem between the processor and the main memory, and its access speed is faster than the main memory. The data in the main memory frequently accessed by the processor and the storage addresses of these data are stored in the cache. When the processor needs to access an address in main memory, the cache checks to see if the address is stored. If the address is stored, the data corresponding to the address is returned to the processor; if the address is not stored, the usual main memory access is performed.

Virtual memory is a technology to solve the shortage of main memory capacity. This technique combines main memory and temporary space on disk to make the application think that it has a very large contiguous full memory. Virtual memory is actually moving part of the data from the main memory to the hard disk when the remaining space of the main memory is insufficient, so as to free up part of the space for the program to continue running.

Although the proposal of these technologies alleviates the speed conflict between the processor and the main memory to a certain extent, the mitigation ability of these technologies is always limited. For example: In order to adapt to the improvement of processor speed, a second-level cache or even a third-level cache is proposed on the basis of the first-level cache. However, the performance impact of the third-level cache is not so obvious. It is only beneficial to large-scale programs such as servers or games, and has little effect on most home computers. The capacity of virtual memory is not unlimited, it is generally 1.5-2 times of physical memory, and it cannot exceed the memory addressing range of 32-bit operating system 4GB. It can be seen that these technologies still have not changed the situation that the read/write speed of the main memory is the bottleneck restricting the performance improvement of the entire computer system. Since the improvement of main memory access speed is far behind the improvement of processor speed, the contradiction in speed between them will inevitably be highlighted sooner or later.

The advent of the multi-core era has put forward a more severe test for the main memory. The current mainstream DRAM-based main memory has reached its limit. If the capacity of the main memory is increased in order to adapt to the high speed of the processor, higher costs and energy consumption must be paid, which will greatly reduce the cost performance. However, as the number of cores increases, the current main memory will face more and more challenges. Therefore, many experts and scholars are committed to researching better storage materials to solve the current dilemma of storage technology.

Flash memory is an electrically erasable programmable read-only memory, which has the characteristics of solid state, small size, light weight, anti-vibration, and low energy consumption. It is a non-volatile memory, that is, it can still store data for a long time without power supply, and its storage characteristics are equivalent to magnetic disks. It is between RAM and disk in terms of price, access latency, transfer bandwidth, storage density, and power consumption. Because the Flash memory is much different than the main memory in terms of access delay, it is difficult to apply it to the main memory. At present, Flash memory is mainly used in mobile storage devices, such as U disk, MP3, digital camera, etc. With increasing capacity and lower prices, Flash memory may replace disks and be used in computer systems in the near future.

Phase-change memory PCM is a memory based on the Ovshinsky electronic effect proposed by Ovshinsky in the late 1960s, using the characteristics of fast phase transition of chalcogenide materials under the action of electric pulses. Due to the limitations of process technology, this semiconductor memory technology has been progressing very slowly. It was not until the end of the last century, when the manufacturing technology of the semiconductor industry reached the nanometer level, that this technology showed its great superiority and developed rapidly. Phase change memory has the characteristics of high scalability, high access speed, high storage density and low energy consumption. It is only slightly slower than DRAM in access speed. According to these characteristics of phase change memory, if it can be well applied to the main memory, it will effectively solve the problems of low capacity and high energy consumption faced by the current main memory, thereby greatly improving the overall performance of the computer system. Because its access speed is relatively low compared with DRAM, if it is simply used as the main memory, it will reduce the performance of the computer system. If it can be combined with DRAM to form the main memory to achieve the effect of learning from each other and complementing each other's advantages, it should be helpful to improve the performance of the main memory.

Contents of the invention

In order to maximize the capacity of the main memory without increasing power consumption and delay, adapt to the rapid increase of processor speed, reduce the number of accesses to the disk, and reduce the energy consumed by storage, the present invention provides a hybrid A method for realizing energy-saving storage in a main memory.

The technical solution adopted by the present invention to solve its technical problems is:

A method for realizing energy-saving storage by mixing main memory, comprising the steps of:

1) Construct a hybrid main memory:

The hybrid main memory is composed of phase change memory PCM and dynamic random access memory DRAM. The phase change memory provides the main capacity of the hybrid main memory and is used to store instructions and data required for program operation; DRAM is connected to the disk and phase change memory through data lines , used to buffer the data of the disk and phase change memory, and the DRAM is also connected to the processor through a data line to send data to the processor;

2) Read and write data in the disk and phase change memory according to the following read and write strategies:

When the processor needs data or instructions, first determine whether they exist in the DRAM buffer, and if they exist, send them to the processor; if they do not exist in the DRAM buffer, continue to determine whether they exist in the phase change memory , if they exist in PCM, they are read into the DRAM buffer first, and then sent to the processor; if they do not exist in PCM, they are read from disk into the DRAM buffer, and then sent to the processor;

When the DRAM buffer is full, some page tables will be replaced to load new data. Before these page tables are replaced, first determine whether the page table to be replaced is in the phase change memory and whether it is dirty data , if it is not in the phase change memory or is dirty data, write it into the phase change memory, otherwise, directly overwrite it with new data.

In order to facilitate the management of the data in the DRAM buffer, the present invention also adds a TAG tag to each item of data in the DRAM buffer, and judges the following information of the marked data by the TAG tag: whether it is valid, whether it is in the phase change memory Among them, whether it has been modified; the data structure of the TAG tag includes a valid bit item, a PCM bit item, and a dirty data bit item, each of which is stored with a bit, and the setting rules for each item are as follows:

1) Valid bit setting: when data is stored in the DRAM buffer, the valid bit in its tag TAG is set to 1; when the data is replaced out of the DRAM buffer, the valid bit in its tag TAG is set to 0; the valid bit is The data area corresponding to the TAG of 1 cannot load new data, and the data area corresponding to the TAG whose effective bit is 0 can load new data, and the effective bit of the TAG is set to 1 after loading the new data;

2) PCM bit setting: when the data is read from the disk into the DRAM buffer, the PCM bit in the tag TAG is set to 0; when the data is read from the phase change memory PCM into the DRAM buffer, the PCM in the tag TAG bit set to 1;

3) Dirty data bit setting: When data is read from disk or phase change memory into the DRAM buffer, the dirty data bit in its tag TAG is set to 0; when the data is modified by the processor, the dirty data in its tag TAG bit is set to 1.

In the process of writing the DRAM buffer to the phase change memory, there is also a phase change memory write queue. When the page tables replaced by the DRAM buffer need to be written back to the phase change memory, these page tables are first sent to the phase change memory. Change memory write queue, and then write phase change memory.

Compared with background technology, the beneficial effect that the present invention has is:

The hybrid main memory formed by combining the phase-change memory and the dynamic random access memory can make full use of their respective advantages and achieve the effect of complementary advantages. The phase change memory provides the main capacity of the hybrid main memory, greatly increases the capacity of the main memory with its high storage density characteristics, and effectively reduces the energy consumption of the entire main memory with its low voltage and low energy consumption characteristics. The dynamic random access memory is used as a buffer of the mixed main memory, and its high access speed characteristic ensures that the access speed of the main memory is not affected by the phase change memory. Therefore, the hybrid main memory of the present invention can obtain the following characteristics: large capacity, low cost, low energy consumption, high storage density and high access speed. These characteristics of the hybrid main memory can effectively solve the problems of small capacity, high cost and high energy consumption faced by the current main memory, thereby improving the overall performance of the computer system.

Description of drawings

FIG. 1 is a schematic structural diagram of a hybrid main memory according to an embodiment of the present invention;

Fig. 2 is the data structure figure of TAG in the DRAM buffer zone of the embodiment of the present invention;

FIG. 3 is a flow chart of a hybrid main memory read strategy according to an embodiment of the present invention;

FIG. 4 is a flow chart of a hybrid main memory write strategy according to an embodiment of the present invention.

Detailed ways

The specific implementation manner of the embodiment of the present invention is: at first, set up the hardware environment of system according to the schematic diagram of hybrid main memory structure shown in Figure 1; Then configure DRAM buffer according to the TAG data structure shown in Figure 2; Read and write data in disk and phase change memory. This implementation is described in more detail below.

(1) Construction of hybrid main memory

Hybrid main memory is composed of phase change memory PCM and dynamic random access memory DRAM. Among them, the phase change memory provides the main capacity of the hybrid main memory, which is used to store the instructions and data required for the program to run; the dynamic random access memory is used as the buffer memory of the hybrid main memory, and is used to buffer the data of the disk and the phase change memory. The DRAM buffer can read the data of the disk and the phase change memory, so it needs the data line to be directly connected with the disk and the phase change memory. The DRAM buffer is the only part that can send data directly to the processor, so it's the only one that has data lines connected directly to the processor. When the DRAM buffer is full, part of the page table will be replaced to load new data. If the replaced data is not in the phase-change memory or is dirty data (that is, the data in the DRAM buffer is inconsistent with its source data in the disk or phase-change memory), it needs to be written into the phase-change memory. In order to alleviate the low write speed of the phase change memory and avoid the processor waiting for a long time, a phase change memory write queue is added during the process of writing from the DRAM buffer to the phase change memory. Therefore, the data line written back from the DRAM buffer is not directly connected to the phase change memory, but is first connected to the PCM write queue, and then connected to the phase change memory PCM. The structure of the hybrid main memory is shown in Figure 1.

(2) DRAM buffer label TAG:

In order to facilitate the management of the data in the DRAM buffer, a tag TAG is added to each item of data. Through the TAG, the following information of the marked data can be judged: whether it is valid, whether it is in the phase change memory, and whether it has been modified. The data structure of TAG is shown in Figure 2, where each item is stored with one bit. The rules for each setting are as follows:

1) Valid bit setting: when data is stored in the DRAM buffer, the valid bit in its tag TAG is set to 1; when the data is replaced out of the DRAM buffer, the valid bit in its tag TAG is set to 0. The data area corresponding to the TAG whose effective bit is 1 cannot load new data, and the data area corresponding to the TAG whose effective bit is 0 can load new data, and the effective bit of the TAG is set to 1 after loading the new data.

2) PCM bit setting: when the data is read from the disk into the DRAM buffer, the PCM bit in the tag TAG is set to 0; when the data is read from the phase change memory PCM into the DRAM buffer, the PCM in the tag TAG bit is set to 1.

3) Dirty data bit setting: When data is read from disk or phase change memory into the DRAM buffer, the dirty data bit in its tag TAG is set to 0; when the data is modified by the processor, the dirty data in its tag TAG bit is set to 1.

(3) Read and write strategy of mixed main memory:

When the processor needs data or instructions, first determine whether they exist in the DRAM buffer, and if they exist, send them to the processor; if they do not exist in the DRAM buffer, continue to determine whether they exist in the phase change memory PCM If it exists, read it into the DRAM buffer first, then send it to the processor, and set the data item TAG to 110; if they do not exist in the phase change memory, read it from the disk into the DRAM buffer area, and then send it to the processor, and set the data item TAG to 100 at the same time. The specific flow of the read strategy is shown in Figure 3. When the DRAM buffer is full, some page tables will be replaced to load new data. Before these page tables are replaced, it is first necessary to determine whether they are in the phase change memory and whether they are dirty data. If there is dirty data in the change memory, it is first sent to the PCM write queue, and then written into the phase change memory PCM, otherwise, the valid bit in the data item TAG is set to 0. The specific process of writing strategy is shown in Figure 4.

Claims (3)

1. A method for mixing main memory to realize energy-saving storage, characterized in that it may further comprise the steps: 1) Construct a hybrid main memory: The hybrid main memory is composed of phase change memory PCM and dynamic random access memory DRAM. The phase change memory provides the main capacity of the hybrid main memory and is used to store instructions and data required for program operation; DRAM is connected to the disk and phase change memory through data lines , used to buffer the data of the disk and phase change memory, and the DRAM is also connected to the processor through a data line to send data to the processor; 2) Read and write data in the disk and phase change memory according to the following read and write strategies: When the processor needs data or instructions, first determine whether they exist in the DRAM buffer, and if they exist, send them to the processor; if they do not exist in the DRAM buffer, continue to determine whether they exist in the phase change memory , if they exist in PCM, they are read into the DRAM buffer first, and then sent to the processor; if they do not exist in PCM, they are read from disk into the DRAM buffer, and then sent to the processor; When the DRAM buffer is full, some page tables will be replaced to load new data. Before these page tables are replaced, first determine whether the page table to be replaced is in the phase change memory and whether it is dirty data , if it is not in the phase change memory or is dirty data, write it into the phase change memory, otherwise, directly overwrite it with new data. 2. the method for realizing energy-saving storage of hybrid main memory as claimed in claim 1 is characterized in that: add a TAG label to each item of data in the DRAM buffer zone, judge the following information of its marked data by TAG label: whether Valid, whether it is in the phase-change memory, whether it has been modified; the data structure of the TAG tag includes valid bit items, PCM bit items, and dirty data bit items, each of which is stored with a bit, and each item The setting rules are as follows: 1) Valid bit setting: when data is stored in the DRAM buffer, the valid bit in its tag TAG is set to 1; when the data is replaced out of the DRAM buffer, the valid bit in its tag TAG is set to 0; the valid bit is The data area corresponding to the TAG of 1 cannot load new data, and the data area corresponding to the TAG whose effective bit is 0 can load new data, and the effective bit of the TAG is set to 1 after loading the new data; 2) PCM bit setting: when the data is read from the disk into the DRAM buffer, the PCM bit in the tag TAG is set to 0; when the data is read from the phase change memory PCM into the DRAM buffer, the PCM in the tag TAG bit set to 1; 3) Dirty data bit setting: When data is read from disk or phase change memory into the DRAM buffer, the dirty data bit in its tag TAG is set to 0; when the data is modified by the processor, the dirty data in its tag TAG bit is set to 1. 3. the method for realizing energy-saving storage of hybrid main memory as claimed in claim 1 is characterized in that: in the process that DRAM buffer is written to phase-change memory, a phase-change memory write queue is provided, when DRAM buffer is replaced When the lost page tables need to be written back into the phase change memory, these page tables are first sent to the phase change memory write queue, and then written into the phase change memory.

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