CN103208250B - A kind of driving circuit, driving method and display device - Google Patents

Abstract

The invention discloses a driving circuit, a driving method and a display device, which are used for increasing the refresh frequency of the scanning signal of the driving circuit. The driving circuit is used to drive the pixels on the array substrate to realize image display, the array substrate is divided into a first display area and a second display area, and the circuit includes m rows connected to the pixels in the first display area Gate scan lines and n columns of data signal lines; m rows of gate scan lines and n columns of data signal lines connected to pixels in the second display area; gate drive circuits connected to each gate scan line; The first source driver circuit and the second source driver circuit of the pixels on the array substrate; the gate driver circuit simultaneously outputs scan signals row by row to the 2m gate scan lines, and the first source driver The driving circuit and the second source driving circuit respectively output data signals to the respective connected data signal lines, and the m and n are positive integers.

Description

A driving circuit, a driving method and a display device

technical field

The present invention relates to the field of display technology, in particular to a driving circuit, a driving method and a display device.

Background technique

In the field of display technology, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Organic Light Emitting Display (OLED) are two main flat panel display devices.

As people's demands for large-size and high-resolution display devices continue to increase, large-size display devices are also developing rapidly. Currently, one of the factors restricting large-sized display devices with high performance and high resolution is the refresh rate. The refresh rate is the number of times the screen is refreshed per second. Different sizes of display devices have different refresh rate requirements. For large-sized displays such as 50 inches or more, a higher refresh rate is required to meet better visual requirements.

The refresh rate is related to the structure of the driving circuit on the array substrate, that is, to the driving method.

As shown in Figure 1, it is the driving circuit of the existing array substrate, including:

A plurality of pixel thin film transistor TFTs distributed in a matrix, a plurality of gate scanning lines (G1, G2, G3, G4, G5, ..., Gm) connected to each pixel and a plurality of data lines (D1, D2, D3, D4,..., D(n-3), D(n-2), D(n-1), D(n)), the gate scanning lines and data lines are distributed in rows and columns, and the gate drive circuit is also included 10 and a source driving circuit 20, the gate driving circuit is composed of m shift registers connected to the gate scanning lines in one-to-one correspondence, the first shift register unit, the second shift register unit, ..., the first shift register unit m shift register units, and a source drive circuit 20 connected to all data signal lines.

The driving method of the existing driving circuit is as follows: the timing controller controls the shift register to scan the gate scanning lines row by row, and when each gate scanning line is turned on, the timing controller controls the source driving circuit to input the current row corresponding to the gate scanning line. data signal. Assuming that there are m rows of scanning lines and n rows of data lines, for a large-sized display device, it takes a long time to scan a frame of image (corresponding to m rows and n columns of pixels), and accordingly, the refresh rate of the display device is low .

Contents of the invention

Embodiments of the present invention provide a driving circuit, a driving method and a display device, which are used to increase the refresh rate of gate signals.

An embodiment of the present invention provides a driving circuit for driving pixels on an array substrate to realize image display. The array substrate is divided into a first display area and a second display area. The circuit includes:

m rows of gate scanning lines and n columns of data signal lines connected to the pixels in the first display area;

m rows of gate scan lines and n columns of data signal lines connected to the pixels in the second display area;

a gate drive circuit connected to each gate scan line;

a first source drive circuit connected to n columns of data signal lines in the first display area and a second source drive circuit connected to n columns of data signal lines in the second display area;

The gate driving circuit simultaneously outputs scanning signals row by row to the gate scanning lines of the first display area and the second display area, and at the same time, the first source driving circuit and the second source driving circuit respectively send The connected data signal lines output data signals, wherein the m and n are positive integers.

Preferably, the gate drive circuit is composed of 2m shift register units, and the shift register units connected to the gate scanning lines of the first display area form a first shift register, which is connected with the second display area. The shift register units connected to the gate scan lines of the region form a second shift register;

The first shift register unit in the first shift register is connected to the first or mth shift register unit in the second shift register;

Wherein, m shift register units in each shift register unit are cascaded with each other.

Preferably, the gate drive circuit is composed of 2m shift register units, and the shift register units connected to the gate scanning lines of the first display area form a first shift register, which is connected with the second display area. The shift register units connected to the gate scan lines of the region form a second shift register;

The mth shift register unit in the first shift register is connected to the first or mth shift register unit in the second shift register;

Wherein, m shift register units in each shift register unit are cascaded with each other.

Preferably, the gate drive circuit is composed of m shift register units, the m shift register units are connected to the m gate scanning lines of the first display area in one-to-one correspondence, and the m shift register units The bit register units are connected to the m gate scanning lines in the second display area in one-to-one correspondence, wherein the m shift register units are cascaded with each other.

Preferably, the gate driving circuit is a gate driving chip, and the gate driving chip is connected to m gate scanning lines in the first display area;

Moreover, the m gate scanning lines in the first display area are connected to the m gate scanning lines in the second display area in one-to-one correspondence.

A method for driving the above-mentioned driving circuit provided by an embodiment of the present invention includes:

In the process of displaying a frame of image, the control gate drive circuit simultaneously outputs scanning signals to the m gate scanning lines of the first display area and the m gate scanning lines of the second display area, and outputs When scanning signals, control the first source drive circuit connected to the data signal lines of the first display area and the second source drive circuit connected to the data signal lines of the second display area to output data signals to the respective data signal lines , the m and n are positive integers.

Preferably, the gate drive circuit is composed of 2m shift register units connected to the 2m gate scanning lines in one-to-one correspondence, and the shift register units connected to the gate scanning lines of the first display area are composed of The first shift register, the shift register unit connected to the gate scanning line of the second display area forms a second shift register; the m shift register units in each shift register unit are cascaded with each other , in the process of displaying a frame of image, the method is specifically:

controlling the first shift register unit in the first shift register and the first shift register unit in the second shift register to simultaneously output the scanning signal, controlling the first source drive circuit and the second source drive circuit The circuit outputs data signals;

controlling the second shift register unit in the first shift register and the second shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source drive circuit and the second source drive The circuit outputs data signals;

controlling the third shift register unit in the first shift register and the third shift register unit in the second shift register to simultaneously output the scanning signal, controlling the first source driver circuit and the second source driver The circuit outputs data signals;

By analogy, until the mth shift register unit in the first shift register and the mth shift register unit in the second shift register are controlled to output the scanning signal at the same time, the first source driver circuit and the first source drive circuit are controlled. until the second source driving circuit outputs the data signal.

Preferably, the gate drive circuit is composed of 2m shift register units connected to the 2m gate scanning lines in one-to-one correspondence, and the m shift register units in each display area are cascaded to each other, and are connected to the first The m shift register units connected to the gate scanning lines of a display area are the first shift registers, and the m shift register units connected to the gate scanning lines of the second display area are the second shift registers, In the process of displaying a frame of image, the method is specifically:

Controlling the first shift register unit in the first shift register and the mth shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source driver circuit and the second source driver The circuit outputs data signals;

controlling the second shift register unit in the first shift register and the m-1th shift register unit in the second shift register to simultaneously output the scanning signal, and controlling the first source drive circuit and the second source The pole drive circuit outputs data signals;

controlling the third shift register unit in the first shift register and the m-2th shift register unit in the second shift register to simultaneously output the scanning signal, and controlling the first source drive circuit and the second source The pole drive circuit outputs data signals;

By analogy, until the mth shift register unit in the first shift register and the first shift register unit in the second shift register are controlled to output the scanning signal at the same time, the first source driver circuit and the first source drive circuit are controlled. until the second source driving circuit outputs the data signal.

Preferably, the gate drive circuit is composed of m shift register units, the m shift register units are connected to the m gate scanning lines of the first display area in one-to-one correspondence, and the m shift register units The bit register units are connected to the m gate scanning lines of the second display area in one-to-one correspondence, wherein the m shift register units are cascaded with each other; in the process of displaying a frame of image, the method is specifically as follows: :

controlling the first shift register unit to output scanning signals to the two gate scanning lines connected to it, and controlling the first source driving circuit and the second source driving circuit to output data signals;

controlling the second shift register unit to output scan signals to the two gate scan lines connected to it, and controlling the first source drive circuit and the second source drive circuit to output data signals;

controlling the third shift register unit to output scan signals to the two gate scan lines connected to it, and controlling the first source drive circuit and the second source drive circuit to output data signals;

By analogy, until the mth shift register unit is controlled to output scanning signals to the two gate scanning lines connected to it, and the first source driving circuit and the second source driving circuit are controlled to output data signals.

Preferably, the gate driving circuit is a gate driving chip, and the gate driving chip is connected to 2m gate scanning lines in the first display area; and, the m gates in the first display area The electrode scanning lines are connected to the m gate scanning lines in the second display area in one-to-one correspondence; in the process of displaying a frame of images, the method is specifically:

Controlling the gate driving chip to output scanning signals to the gate scanning lines of the first display area and the gate scanning lines of the second display area row by row, and simultaneously controlling the first source driving circuit and the second source driving circuit to output data until the signal.

An embodiment of the present invention provides a display device, including the above driving circuit.

In the embodiment of the present invention, two display regions are arranged on the array substrate, and the driving circuit simultaneously drives the pixels of the two display regions on the array substrate, thereby increasing the refresh frequency of the scanning signal of the driving circuit. Specifically, in the process of displaying a frame of image, the gate driving circuit is controlled to simultaneously output scanning signals to the m gate scanning lines of the first display area and the m gate scanning lines of the second display area, and each When outputting scanning signals once, the first source driving circuit in the first display area and the second source driving circuit in the second display area are controlled to output data signals to the data signal lines connected to them, so as to realize image display with a high refresh rate.

Description of drawings

FIG. 1 is a schematic structural diagram of a driving circuit for driving an array substrate in the prior art;

FIG. 2 is a schematic structural diagram of an array substrate provided by Embodiment 1 of the present invention;

FIG. 3 is one of the structural schematic diagrams of the driving circuit provided by Embodiment 1 of the present invention;

FIG. 4 is the second structural schematic diagram of the driving circuit provided by the first embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a driving circuit provided by Embodiment 2 of the present invention;

FIG. 6 is a schematic structural diagram of a driving circuit provided by Embodiment 3 of the present invention;

FIG. 7 is a timing diagram corresponding to the driving circuit shown in FIG. 3;

FIG. 8 is a timing diagram corresponding to the driving circuit shown in FIG. 4 .

Detailed ways

Embodiments of the present invention provide a driving circuit, a driving method and a display device, which are used to increase the refresh rate of scanning signals of the driving circuit.

The array substrate provided by the present invention includes pixels in the first display area and pixels in the second display area, and the driving circuit provided in the embodiment of the present invention simultaneously drives the pixels in the first display area and the pixels in the second display area to improve scanning The refresh frequency of the signal, or prolong the charging time of the pixels connected to each gate scan line.

Specifically, two gate scan lines of the first display area and the second display area are simultaneously turned on in each pulse time period, and the gate scan lines of each display area are scanned row by row, thereby increasing the image refresh rate.

The driving circuit provided by the embodiment of the present invention may be, but not limited to, the field of liquid crystal display and the field of organic light-emitting display.

In the specific implementation process, the driving circuit on the array substrate mainly includes a timing control circuit, a gate driving circuit (that is, a scanning driving circuit), and a source driving circuit (that is, a data driving circuit), and each gate scanning line and data signal Wire.

The array substrate, the driving circuit and the driving method provided by the embodiments of the present invention will firstly be described in detail with reference to the accompanying drawings.

Referring to Fig. 2, the array substrate provided by the embodiment of the present invention includes:

Substrate 1;

A pixel array formed by a plurality of pixels 2 on the substrate 1 (a pixel array formed by 2m rows and n columns of pixels);

The first m rows and n columns of pixels form the first display area 3, and the second m rows and n columns of pixels form the second display area 4 (such as the circuit in the dotted line box);

The driving circuits for driving the above-mentioned array substrate to realize image display provided by the embodiments of the present invention are different according to different gate driving circuits, and will be described separately for different gate driving circuits below.

First embodiment:

Referring to FIG. 3, the driving circuit provided in Embodiment 1 includes:

m gate scanning lines (G1U, G2U, G3U, ... G(m-1)U, Gm U in Fig. 3) connected to the pixels in the first display area 3), n data signal lines ( D1U, D2U, D3U, D4U, ..., D(n-3)U, D(n-2)U, D(n-1)U, Dn U), and connected to the n data signal lines The first source drive circuit 32;

m gate scanning lines (G1D, G2D, G3D, ... G(m-1)D, Gm D in Fig. D1D, D2D, D3D, D4D, ..., D(n-3)D, D(n-2)D, D(n-1)D, Dn D), and connected to the n data signal lines The second source driver circuit 42.

The gate drive circuit provided by Embodiment 1 is composed of 2m shift register units (Shift Register), and the m shift register units corresponding to the first display area 3 are the first shift register 31; and the second display area 4 The corresponding m shift register units are the second shift register 41;

The first shift register unit in the first shift register 31 is connected with the first or m shift register unit in the second shift register 41; or the m shift register unit in the first shift register 31 The bit register unit is connected to the first or the m shift register unit in the second shift register 41; the m shift register units in each shift register are cascaded with each other; that is, the first shift register The first shift register unit to the mth shift register unit in 31 are cascaded with each other (connected end to end in sequence); the first shift register unit to the mth shift register unit in the second shift register 41 The register units are cascaded with each other.

The 2m shift register units are connected to the 2m gate scanning lines in one-to-one correspondence;

Under the control of the timing controller (shown as STV in Figure 3), the gate drive circuit simultaneously drives the m rows of pixels and the last m rows of pixels in the first display area 3 and the second display area 4 row by row to realize image display , the m and n are positive integers.

FIG. 3 is a driving circuit in which the first shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41 .

FIG. 4 is a driving circuit in which the mth shift register unit in the first shift register 31 is connected to the first shift register unit in the second shift register 41 .

Taking the array substrate shown in FIG. 3 as an example, the driving method of the driving circuit shown in Embodiment 1 includes:

In the process of displaying each frame of image, control the first shift register unit in the first shift register and the first shift register unit in the second shift register to output the scanning signal simultaneously, and control the first The source driving circuit and the second source driving circuit output data signals;

controlling the second shift register unit in the first shift register and the second shift register unit in the second shift register to simultaneously output the scan signal, controlling the first source drive circuit and the second source drive The circuit outputs data signals;

controlling the third shift register unit in the first shift register and the third shift register unit in the second shift register to simultaneously output the scanning signal, controlling the first source driver circuit and the second source driver The circuit outputs data signals;

By analogy, until the mth shift register unit in the first shift register and the mth shift register unit in the second shift register are controlled to output the scanning signal at the same time, the first source driver circuit and the first source drive circuit are controlled. until the second source driving circuit outputs the data signal.

The drive circuit shown in Figure 3, in the specific implementation process, the timing controller only needs to output the first shift register unit in the first shift register and the first shift register unit in the second shift register Just scan the signal, because the shift register units corresponding to each display area are cascaded with each other, the output of the first shift register unit in each shift register is the input of the second shift register unit; The output of the second shift register unit is the input of the third shift register unit; and so on, the output of the m-1th shift register unit is the input of the mth shift register unit.

Embodiment two:

Referring to FIG. 5 , the gate drive circuit is composed of a shift register, which is composed of m mutually cascaded shift register units, and the m shift register units are connected to the m bars in the first display area 3 The gate scanning lines are connected in one-to-one correspondence, and at the same time are connected in one-to-one correspondence with the m gate scanning lines in the second display region 4 .

In the drive circuit shown in Figure 5, the first grid scan line in the first display area is connected to the first grid scan line in the second display area, and the second grid scan line in the first display area is connected to the second grid scan line in the second display area. The second gate scan line of the display area is connected until the m gate scan line of the first display area is connected with the m gate scan line of the second display area, and the scan signal is transmitted from the first gate scan line enter.

The driving method of the driving circuit shown in Figure 5 includes:

In the process of displaying each frame of image, control the first shift register unit to output scanning signals to the two gate scanning lines connected to it, and control the first source driving circuit and the second source driving circuit to output data signals ;

controlling the second shift register unit to output scan signals to the two gate scan lines connected to it, and controlling the first source drive circuit and the second source drive circuit to output data signals;

controlling the third shift register unit to output scan signals to the two gate scan lines connected to it, and controlling the first source drive circuit and the second source drive circuit to output data signals;

By analogy, until the mth shift register unit is controlled to output scanning signals to the two gate scanning lines connected to it, and the first source driving circuit and the second source driving circuit are controlled to output data signals.

Similarly, in the specific implementation process, the timing controller only needs to output the scanning signal to the first shift register unit. Since the shift register units are cascaded with each other, the output of the upper shift register unit is the next Input to a shift register unit.

The scanning mode shown in FIG. 5 is progressive scanning from top to bottom, and may also be progressive scanning from bottom to top.

When the scan mode is row-by-row scan from bottom to top, the scan signal is input from the mth gate scan line.

Embodiment three:

Referring to FIG. 6, the gate drive circuit is a gate drive chip 6, and the gate drive chip 6 is connected to 2m gate scanning lines;

Wherein, the m gate scanning lines in the first display area 3 are connected to the m gate scanning lines in the second display area 4 in a one-to-one correspondence.

The driving method of the driving circuit shown in Figure 6 includes:

Controlling the gate driving chip to output scanning signals to the gate scanning lines of the first display area and the gate scanning lines of the second display area row by row, and simultaneously controlling the first source driving circuit and the second source driving circuit to output data until the signal.

3 to 6, the gate scanning lines in the first display area 3 and the second display area 4 are arranged in multiple rows, and the data signal lines in the first display area 3 and the second display area 4 are in multiple rows. column arrangement.

Specifically, all the gate scanning lines in the first display area 3 are adjacent to each other in sequence, and all the gate scanning lines in the second display area 4 are adjacent to each other in sequence.

The n data signal lines in the first display area 3 are arranged crosswise with the m gate scanning lines in the first display area.

The n data signal lines in the second display area 3 are arranged crosswise with the m gate scanning lines in the second display area.

Correspondingly, the driving circuits shown in FIGS. 3-6 , the first source driving circuit and the second source driving circuit are located in the peripheral area of the entire array substrate, which does not affect the aperture ratio of the display device. Such an arrangement facilitates the wiring of the circuit structure and improves the display quality of the image of the display device.

Preferably, the first source driving circuit and the second source driving circuit can be realized by a shift register fabricated on the array substrate, or can be realized by a gate driving chip (Integrated Circuit Card, IC).

It should be noted that the drive circuits provided by Embodiments 1 to 3 of the present invention are not limited to the structures shown in FIGS. 3-6 , but also include modules such as a reference voltage source and a voltage source conversion circuit.

The driving method of the driving circuit provided by the embodiment of the present invention will be specifically described below with reference to the timing circuit diagrams shown in FIG. 7 and FIG. 8 .

The gate drive circuit of the present invention is used to sequentially output an appropriate switching voltage to a specific gate scan line to drive the pixels connected to the gate scan line; the source drive circuit inputs the pixel voltage of the gate scan line to the The gate scan line is connected to each pixel.

In the present invention, two rows of gate scanning lines are simultaneously turned on within one pulse time period, and data signals are simultaneously input to the data signal lines corresponding to the two rows of gate scanning lines. In this way, the times of turning on the gate scanning lines on the array substrate are halved, and the refresh frequency can be doubled, or the charging time of each row can be increased under the premise of a certain refresh frequency.

An embodiment of the present invention provides a driving method for driving the above-mentioned array substrate to realize image display, which generally includes:

In the process of displaying a frame of image, the gate drive circuit is controlled to simultaneously output scanning signals to the m gate scanning lines of the first display area and the m gate scanning lines of the second display area. signal, control the first source driver circuit in the first display region and the second source driver circuit in the second display region to output data signals to the data signal lines connected to them.

FIG. 7 is a schematic diagram of timing signals of a timing controller corresponding to the driving circuit shown in FIG. 3 .

In the first pulse time period of the display time of one frame image, control the first gate scanning line G1U in the first display area and the first gate scanning line G1D in the second display area to be turned on at a high level , and the other gate scanning lines are turned off at low level;

In the second pulse time period, control the second gate scanning line G2U in the first display area and the second gate scanning line G2D in the second display area to be turned on at high level, and the remaining gate scanning lines are at low level closure;

In the third pulse period, control the third gate scanning line G3U in the first display area and the third gate scanning line G3D in the second display area to be turned on at a high level, and the remaining gate scanning lines are at a low level closure;

By analogy, the m-1th pulse time period controls the m-1th gate scan line G(m-1)U in the first display area and the second gate scan line in the second display area G(m-1)D is turned on at a high level, and the other gate scanning lines are turned off at a low level;

In the mth pulse time period, control the mth gate scanning line GmU in the first display area and the mth gate scanning line GmD in the second display area to be turned on at a high level, and the remaining gate scanning lines are at a low level closure.

The scanning of the gate scanning lines in the first display area and the second display area is completed within the display time of one frame of image.

FIG. 8 is a schematic diagram of timing signals of a timing controller corresponding to the driving circuit shown in FIG. 4 .

During the display time of one frame image, in the first pulse time period, control the mth gate scanning line GmD in the first display area and the first gate scanning line G1U in the second display area to be high level (corresponding to the high-level open state in Figure 8), and the remaining gate scanning lines are low-level;

In the second pulse period, control the m-1th gate scanning line G(m-1)D in the first display area and the second gate scanning line G1U in the second display area to be high level, The other gate scan lines are low level;

In the third pulse period, control the m-2th gate scan line G(m-2)D in the first display area and the third gate scan line G1U in the second display area to be high level, The other gate scan lines are low level;

By analogy, control the second gate scanning line G2D in the first display area and the m-1th gate scanning line G(m-1)U in the second display area to be at high level, and the remaining gates Scan line low level;

Until the first gate scanning line G2D in the first display area and the mth gate scanning line GmU in the second display area are controlled to be at high level, the remaining gate scanning lines are at low level;

The scanning of the gate scanning lines in the first display area and the second display area is completed within the display time of one frame of image.

When the pulse width of the existing scanning signal is the same, the refresh rate of the image is doubled. When the refresh rate is the same as the existing one, the charging time of the pixel is doubled.

The array substrate and the driving method provided by the embodiments of the present invention are preferably applicable to an array substrate with a high degree of integration, such as low temperature polysilicon technology (Low Temperature Poly-silicon, LTPS).

The embodiment of the present invention also provides a display device, the display device includes the driving circuit provided by the embodiment of the present invention, and the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal TV, an organic electroluminescent display OLED panel, an OLED display, Display devices such as OLED TVs or electronic paper.

In the embodiment of the present invention, by setting two display regions (the first display region and the second display region) to simultaneously drive the pixel array on the array substrate, the refresh rate of image display on the array substrate is improved. Specifically, the first display area turns on the gate scan lines in the circuit row by row, and the second display area turns on the gate scan lines in the circuit row by row. When a certain gate scan line is turned on in the first display area, the second The two display areas also turn on one gate scanning line at the same time, that is to say, at the same time, two gate scanning lines on the array substrate are turned on at the same time, and the two gate scanning lines are respectively connected to a source driving circuit. When the scanning lines are turned on, the two source driving circuits respectively input the data signals corresponding to the respective data signal lines to realize image display. From the above, it can be seen that the refresh rate of the image displayed on the array substrate is at least doubled.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (3)

1. A driving circuit for driving pixels on an array substrate to realize image display, wherein the array substrate is divided into a first display area and a second display area, and the circuit comprises: m rows of gate scanning lines and n columns of data signal lines connected to the pixels in the first display area; m rows of gate scan lines and n columns of data signal lines connected to the pixels in the second display area; a gate drive circuit connected to each gate scan line; a first source drive circuit connected to n columns of data signal lines in the first display area and a second source drive circuit connected to n columns of data signal lines in the second display area; The gate driving circuit simultaneously outputs scanning signals row by row to the gate scanning lines of the first display area and the second display area, and at the same time, the first source driving circuit and the second source driving circuit respectively send The connected data signal line outputs a data signal, wherein the m and n are positive integers; The gate drive circuit is composed of m shift register units, the m shift register units are connected to the m gate scanning lines in the first display area in one-to-one correspondence, and the m shift register units are connected to The m gate scanning lines in the second display area are connected in one-to-one correspondence, wherein the m shift register units are cascaded with each other. 2. A driving method of the driving circuit according to claim 1, comprising: In the process of displaying a frame of image, the control gate drive circuit simultaneously outputs scanning signals to the m gate scanning lines of the first display area and the m gate scanning lines of the second display area, and outputs When scanning signals, control the first source drive circuit connected to the data signal lines of the first display area and the second source drive circuit connected to the data signal lines of the second display area to output data signals to the respective data signal lines , the m and n are positive integers; The gate drive circuit is composed of m shift register units, the m shift register units are connected to the m gate scanning lines in the first display area in one-to-one correspondence, and the m shift register units are connected to The m gate scanning lines in the second display area are connected in one-to-one correspondence, wherein the m shift register units are cascaded with each other; in the process of displaying a frame of image, the method is specifically: controlling the first shift register unit to output scanning signals to the two gate scanning lines connected to it, and controlling the first source driving circuit and the second source driving circuit to output data signals; controlling the second shift register unit to output scan signals to the two gate scan lines connected to it, and controlling the first source drive circuit and the second source drive circuit to output data signals; controlling the third shift register unit to output scan signals to the two gate scan lines connected to it, and controlling the first source drive circuit and the second source drive circuit to output data signals; By analogy, until the mth shift register unit is controlled to output scanning signals to the two gate scanning lines connected to it, and the first source driving circuit and the second source driving circuit are controlled to output data signals. 3. A display device, comprising the drive circuit according to claim 1.