CN103187399A - Through-silicon via (TSV) testing structure and TSV testing method - Google Patents
Through-silicon via (TSV) testing structure and TSV testing method Download PDFInfo
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Abstract
The invention discloses a through-silicon via (TSV) testing structure and a TSV testing method. The TSV testing structure comprises a semiconductor substrate, an interlayer dielectric layer located on the surface of the semiconductor substrate, a TSV formed in the semiconductor substrate and the interlayer dielectric layer, and at least one interconnection structural ring, wherein the interconnection structural ring is distributed in an annular shape on the periphery of the TSV regarding the TSV as the center and is formed by metal layers on different layers, and electric conduction plugs between the metal layers in a serial-connection mode. Due to the fact that the interconnection structural ring is distributed in the annular shape on the periphery of the TSV regarding the TSV as the center, resistance of the interconnection structural ring is tested in directions far away from the TSV in sequence, tested resistance values are compared with a reference resistance value, then the range of an isolation region between the interconnection structural ring and the TSV can be obtained, and therefore the TSV testing structure and the TSV testing method are convenient and fast to use.
Description
Technical field
The present invention relates to the semiconductor test technical field, particularly a kind of silicon through hole test structure and method of testing of the scope that interconnection structure is exerted an influence for test silicon through hole stress.
Background technology
Along with for example fast development of mobile phone etc. of portable electric appts, the volume of portable electric appts becomes more and more littler, and the function that provides becomes more and more widely, therefore is necessary very much under the prerequisite that does not increase equipment size, improves the integrated level of built-in chip.At present, three-dimension packaging becomes a kind of method that can effectively improve chip integration.Present three-dimension packaging comprises chip-stacked (Die Stacking) based on the gold thread bonding, encapsulation stacking (Package Stacking) and based on silicon through hole (Through Silicon Via, TSV) three-dimensional stacked.Wherein, utilize the three-dimensional stacked technology of silicon through hole to have following three advantages: (1) high density is integrated.By three-dimensional stacked, can significantly improve the integrated level of semiconductor device, the physical dimension that reduces to encapsulate satisfies microelectronic product for multi-functional and demand miniaturization; (2) improve electrical property.Because silicon through hole technology can shorten the length of electrical interconnection significantly, thereby can solve the problems such as signal delay that appear in two-dimentional system level chip (SOC) technology well, improve electrical property; (3) multi-functional integrated.Traditional two-dimentional SOC technology must realize that the chip that will have limited several functions carries out integrated by the design of complexity and very big chip size, be difficult to realize the integrated of multifunction chip, and by utilizing silicon through hole technology, can integrate to realize the multi-functional of packaged chip to the chip with difference in functionality (as radio frequency, internal memory, logic, MEMS etc.).Therefore, the described three-dimensional stacked technology of interconnecting silicon through holes structure of utilizing becomes a kind of comparatively popular chip encapsulation technology day by day.
The main method that forms the silicon through hole at present comprises: utilize the first surface that is dry-etched in Semiconductor substrate to form through hole; Form separator at described through-hole side wall and lower surface; Adopt electric plating method that copper is filled full described through hole, and remove unnecessary copper electrodeposited coating with chemico-mechanical polishing; Second surface to described Semiconductor substrate carries out chemico-mechanical polishing, up to exposing the through hole of filling full copper, forms the silicon through hole, and described second surface is relative with first surface.
More information about the silicon through hole please refer to the american documentation literature that publication number is US2010/0171226A1.
But because described silicon through hole runs through Semiconductor substrate, described silicon through hole can impact near interconnection structure and semiconductor device, therefore around described silicon through hole, need to vacate an isolated area, in described isolated area, can not be formed with interconnection structure and semiconductor device, in order to avoid the electric property of described interconnection structure, semiconductor device is caused harmful effect.But also there is not a kind of semi-conductor test structure can test out the isolated area scope of interconnection structure around the silicon through hole effectively at present.
Summary of the invention
The problem that the present invention solves provides a kind of silicon through hole test structure and method of testing, is used for testing the isolated area scope of interconnection structure around the silicon through hole.
For addressing the above problem, the embodiment of the invention provides a kind of silicon through hole test structure, comprising:
Semiconductor substrate is positioned at the interlayer dielectric layer of described semiconductor substrate surface, is positioned at the silicon through hole of described Semiconductor substrate and interlayer dielectric layer;
Comprise that also at least one interconnection structure ring, described interconnection structure ring are distributed in described silicon through hole periphery ringwise centered by the silicon through hole, described interconnection structure ring is in series by metal level and the conductive plunger between described metal level of different layers.
Optionally, described metal level comprises two-layer at least.
Optionally, when described interconnection structure ring during at least two, described interconnection structure ring is concentric ring and distributes, and the spacing between each interconnection structure equates.
Optionally, described concentric ring is distributed as that donut distributes or the concentric rectangles ring distributes.
Optionally, described interconnection structure ring is non-sealing.
Optionally, the quantity of described silicon through hole is at least one.
When described interconnection structure ring when being a plurality of, in the described adjacent interconnection structure ring at the metal level of same layer with equaling the minimal design spacing with the spacing between the conductive plunger of one deck.
The embodiment of the invention also provides a kind of method of testing of utilizing described silicon through hole test structure, comprising:
On away from the direction of silicon through hole, successively adjacent interconnection structure circulating application is added test voltage, the puncture voltage that test is corresponding;
With described puncture voltage with compare with reference to puncture voltage, obtain the maximum magnitude that stress that the silicon through hole produces exerts an influence to interlayer dielectric layer.
Optionally, described is the puncture voltage that does not have between two corresponding in the identical interconnection structure ring of the shape of silicon through hole interconnection structure rings with reference to puncture voltage.
Optionally, when certain puncture voltage that records equals described during with reference to puncture voltage for the first time, the zone that the interconnection structure ring of more close silicon through hole surrounds in two corresponding interconnection structure rings is the stress of silicon through hole to the maximum magnitude of the influence of interlayer dielectric layer.
The embodiment of the invention also provides the another kind of method of testing of utilizing described silicon through hole test structure, comprising:
Opening two ends to each interconnection structure ring apply test voltage successively on away from the direction of silicon through hole, the resistance that test is corresponding;
Described resistance and reference resistance are compared the maximum magnitude that the stress that acquisition silicon through hole produces exerts an influence to interconnection structure.
Optionally, described reference resistance is the resistance that does not have the identical interconnection structure ring of the shape of silicon through hole.
Optionally, when certain resistance that records equaled described reference resistance for the first time, the zone that corresponding interconnection structure ring surrounds was the maximum magnitude that the stress of silicon through hole exerts an influence to interconnection structure.
Compared with prior art, the present invention has the following advantages:
Described at least one interconnection structure ring is distributed in described silicon through hole periphery ringwise, and described interconnection structure ring is in series by metal level and the conductive plunger between described metal level of different layers.By the resistance of test interconnection structure ring, and the described resistance that records and reference resistance compared, whether the isolated area scope that can obtain between silicon through hole and the interconnection structure is suitable, and detection method is convenient and swift.
Further, when described interconnection structure ring is at least two, by testing the puncture voltage of adjacent interconnection structure ring, and with the described puncture voltage that records with compare with reference to puncture voltage, can obtain the silicon through hole for the scope of the isolated area of interconnection structure, convenient and swift.
Description of drawings
Fig. 1 is the structural representation of the silicon through hole test structure of first embodiment of the invention;
Fig. 2 is the cross-sectional view of the silicon through hole test structure of first embodiment of the invention;
Fig. 3 is the structural representation of the silicon through hole test structure of another embodiment of the present invention;
Fig. 4 is the schematic flow sheet of method of testing of the silicon through hole test structure of the embodiment of the invention;
Fig. 5 is the schematic flow sheet of method of testing of the silicon through hole test structure of the embodiment of the invention.
Embodiment
In the prior art, three-dimensional stacked for chip is realized, the silicon through hole runs through whole Semiconductor substrate to realize up and down the electrical connection between two chips.What wherein, fill in the described silicon through hole is copper.But when the temperature of described Semiconductor substrate changes, because the thermal coefficient of expansion of described copper and Semiconductor substrate does not match, making the silicon through hole that Semiconductor substrate on every side, interlayer dielectric layer are produced easily stretches or compression stress, described stretching or compression stress make the interlayer dielectric layer that finally forms around described silicon through hole, the lattice of metal interconnecting layer variation take place, thereby made the electric property of interconnection structure that variation take place.And, along with increasing integrated circuit uses low-K dielectric material as the material of interlayer dielectric layer, because described low-K dielectric material mechanical strength is lower, described interlayer dielectric layer deforms easily, make interconnection structure deform easily or produce defective that the electrical parameter of interconnection structure changes.Therefore, electrical parameter for fear of interconnection structure changes, can not make the performance of integrated circuit of final formation change, isolated area for interconnection structure should be set in described silicon through hole zone on every side, namely in integrated circuit (IC) design, in described isolated area, must not be provided with interconnection structure.
Therefore, the inventor has proposed a kind of silicon through hole test structure and method of testing through research, and described silicon through hole test structure comprises: Semiconductor substrate, be positioned at the interlayer dielectric layer of described semiconductor substrate surface, be positioned at the silicon through hole of described Semiconductor substrate and interlayer dielectric layer; At least one interconnection structure ring, described interconnection structure ring are distributed in described silicon through hole periphery ringwise centered by the silicon through hole, described interconnection structure ring is in series by metal level and the conductive plunger between described metal level of different layers.Because described interconnection structure ring is distributed in described silicon through hole periphery ringwise centered by the silicon through hole, on away from the direction of silicon through hole, successively the interconnection structure ring is carried out resistance test, the described resistance that records and reference resistance are compared, can obtain the scope of corresponding isolated area, convenient and swift.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
The embodiment of the invention at first provides a kind of silicon through hole test structure, please in the lump with reference to figure 1 and Fig. 2, described Fig. 1 is the structural representation of overlooking the visual angle of the silicon through hole test structure of present embodiment, described Fig. 2 is that silicon through hole test structure among Fig. 1 is along the cross-sectional view of AA ' line of cut, specifically comprise: Semiconductor substrate 100, be positioned at the interlayer dielectric layer 110 on described Semiconductor substrate 100 surfaces, run through the silicon through hole 120 of described interlayer dielectric layer 110 and Semiconductor substrate 100; At least one interconnection structure ring 130, described several interconnection structure rings 130 are positioned at the interlayer dielectric layer 110 on every side of described silicon through hole 120 and surround several concentric rings centered by described silicon through holes 120, and described interconnection structure ring 130 is in series by metal level 131 and the conductive plunger 135 between described metal level 131 of different layers.
Described Semiconductor substrate 100 is wherein a kind of of silicon substrate, germanium substrate, silicon-Germanium substrate, silicon carbide substrates, gallium nitride substrate.The material of described interlayer dielectric layer 110 is silica or low-K dielectric material.
Described silicon through hole 120 is positioned at described interlayer dielectric layer 110 and Semiconductor substrate 100, described silicon through hole 120 can run through described Semiconductor substrate 100 and interlayer dielectric layer 110, also can not run through described Semiconductor substrate 100 and interlayer dielectric layer 110, be connected with interconnection structure with other semiconductor device by the layer of metal interconnection layer on described silicon through hole 120 surfaces.In the present embodiment, described silicon through hole 120 runs through described Semiconductor substrate 100 and interlayer dielectric layer 110, described silicon through hole 120 surfaces are formed with layer of metal interconnection layer (not shown), and the top layer metallic layer of described metal interconnecting layer and interconnection structure ring is positioned at same one deck.In other embodiments, described metal interconnecting layer also can be positioned at different layers with the top layer metallic layer of interconnection structure ring.
Described silicon through hole 120 comprises through hole (not shown), be positioned at the insulating barrier (not shown) of described through-hole side wall, be positioned at the electric conducting material (not shown) of the full described through hole of filling of described surface of insulating layer.Described insulating barrier is with the electric conducting material in the silicon through hole and Semiconductor substrate electric isolation, avoids later use silicon through hole to carry out taking place when electricity connects electric leakage or short circuit.Between described electric conducting material and insulating barrier, can also be formed with diffusion impervious layer (not shown).Described diffusion impervious layer both can prevent that described electric conducting material from diffusing in the insulating barrier, influenced the insulation property of insulating barrier, can also prevent electric conducting material and insulation displacement as the tack coat of electric conducting material and insulating barrier.
In the present embodiment, described interconnection structure ring 130 surrounds a silicon through hole 120.In other embodiments, please refer to Fig. 3, described interconnection structure ring 130 be surrounded by several silicon through holes 120 '.Described at least one interconnection structure ring 130 by described several silicon through holes 120 ' central point centered by be concentric ring and distribute.
Please continue with reference to figure 1 and Fig. 2, described interconnection structure ring 130 comprises some layers of metal level 131 and conductive plunger 135.The material of described metal level 131 and conductive plunger 135 is copper, aluminium, tungsten etc.In the existing integrated circuits manufacturing process, metal level in the described interlayer dielectric layer 110 is generally multilayer, whether can cause damage to the wherein layer of metal layer of interconnection structure ring 130 in order accurately to record silicon through hole 120, or can not cause damage to the interlayer dielectric layer 110 of certain height, or can not cause damage to the conductive plunger 135 of one deck wherein, need the corresponding metal level of test whether to be positioned at described silicon through hole 120 stress influence scopes, whether corresponding interlayer dielectric layer 110 is positioned at described silicon through hole 120 stress influence scopes, whether corresponding conductive plunger 135 is positioned at described silicon through hole 120 stress influence scopes, thereby tests out described silicon through hole 120 for the scope of the isolated area of interconnection structure.Therefore, the number needs of the metal level that comprises of described interconnection structure ring 130 is many as much as possible.In the present embodiment, described interconnection structure ring 130 comprises three-layer metal layer 131 and two-layer conductive plunger 135.In other embodiments, described interconnection structure ring comprises two metal layers and one deck conductive plunger at least.
Described some layers of metal level 131 and conductive plunger 135 series connection form interconnection structure ring 130, and described interconnection structure ring 130 can seal, also can be nonocclusive.In the present embodiment, described interconnection structure ring 130 is nonocclusive, has opening, when test voltage is applied to the opening two ends of described interconnection structure ring 130, can detect the resistance of each interconnection structure ring 130, thereby judge whether described interconnection structure ring 130 sustains damage.
When described interconnection structure ring when being a plurality of, described interconnection structure ring 130 surrounds several concentric rings around the silicon through hole.Described concentric ring be shaped as donut or concentric rectangles ring.The cross section of described silicon through hole be shaped as circle or rectangle.The shape of described concentric ring can be corresponding with the shape of silicon through hole, also can be not corresponding.In the present embodiment, described silicon through hole be shaped as circle, described concentric ring be shaped as the concentric rectangles ring.In other embodiments, when the shape of described concentric ring is corresponding with the shape of silicon through hole, if described silicon through hole be shaped as circle, described concentric ring be shaped as donut; If described silicon through hole be shaped as rectangle, described silicon through hole be shaped as the concentric rectangles ring.
Spacing between the described adjacent interconnection structure ring 130 equates, because described spacing is determined, which when test, only need test out from interconnection structure ring 130, interlayer dielectric layer between the interconnection structure ring no longer is subjected to the influence of the stress effect of silicon through hole generation, just can test out the silicon through hole for the scope of the isolated area of interconnection structure, convenient and swift.In the present embodiment, the spacing between the described adjacent interconnection structure ring 130 is the minimal design spacing, and described minimal design spacing is the attainable minimum spacing of technology between the adjacent wires, between the adjacent conductive connector in the circuit design.Because the spacing between metal wire, the conductive plunger is all more than or equal to the minimal design spacing in circuit design, when the spacing of two interconnection structure rings is the minimal design spacing, measured puncture voltage when not changing with reference to puncture voltage, thereby can judge whether corresponding interconnection structure ring 130 is positioned at described silicon through hole stress influence scope.In order to record the puncture voltage between the adjacent interconnection structure ring more delicately, need make that metal level and conductive plunger are approaching as far as possible in the adjacent interconnection structure ring, therefore, being positioned at the metal level of one deck and being positioned at corresponding setting of conductive plunger with one deck in the described adjacent interconnection structure ring makes in the described adjacent interconnection structure ring at the metal level of same layer and equaling the minimal design spacing with the spacing between the conductive plunger of one deck.
When needs obtain corresponding silicon through hole for the scope of the isolated area of interconnection structure by the puncture voltage between the described adjacent interconnection structure ring of test, described interconnection structure ring 130 is at least two.The resistance that passes through the described interconnection structure ring of test when needs obtains corresponding silicon through hole for the scope of the isolated area of interconnection structure, and the quantity of described interconnection structure ring 130 is at least 1.The quantity and spacing of described interconnection structure ring can specifically be set with different silicon via process according to different test needs.
The embodiment of the invention also provides a kind of method of testing of utilizing described silicon through hole test structure, please refer to Fig. 4, and the schematic flow sheet for the method for testing of present embodiment specifically comprises:
Step S101 adds test voltage to adjacent interconnection structure circulating application successively on away from the direction of silicon through hole, the puncture voltage that test is corresponding;
Step S102, with described puncture voltage with compare with reference to puncture voltage, obtain the maximum magnitude that stress that the silicon through hole produces exerts an influence to interlayer dielectric layer.
Concrete, because behind the breakdown voltage breakdown of interlayer dielectric layer between the adjacent interconnection structure ring, can make and produce defective in interlayer dielectric layer and the corresponding interconnection structure ring, interconnection structure ring through the test puncture voltage can not be proceeded test, therefore, on the direction away from the silicon through hole, respectively odd number interconnection structure ring and even number interconnection structure ring are tested.For example, on the direction away from the silicon through hole, earlier the first interconnection structure ring, the second interconnection structure ring are tested, again the 3rd interconnection structure ring, the 4th interconnection structure ring are tested.
Compare with the described puncture voltage that several record with reference to puncture voltage.Described is the puncture voltage that does not have between two corresponding in the identical interconnection structure ring of the shape of silicon through hole interconnection structure rings with reference to puncture voltage.When the described puncture voltage that records when identical with reference to puncture voltage, show that the interlayer dielectric layer between described two interconnection structure rings is not subjected to the stress influence that the silicon through hole produces, the interlayer dielectric layer between described two interconnection structure rings is positioned at outside the stress influence scope of described silicon through hole.When the described puncture voltage that records during less than the reference puncture voltage, show that there is defective in the interlayer dielectric layer between described two interconnection structure rings, interlayer dielectric layer between described two interconnection structure rings has been subjected to the stress influence that the silicon through hole produces, and the interlayer dielectric layer between described two interconnection structure rings is positioned at the stress influence scope of described silicon through hole.Therefore, on away from the direction of silicon through hole successively to adjacent interconnection structure ring test puncture voltage, and with the described puncture voltage that records with compare with reference to puncture voltage.Since when the interconnection structure ring too when the silicon through hole, the stress of silicon through hole can influence corresponding interlayer dielectric layer, the feasible puncture voltage that records is less than the reference puncture voltage.When certain puncture voltage that records equals described during with reference to puncture voltage for the first time, show that corresponding interconnection structure ring is the border of the stress influence scope of silicon through hole, the zone that the interconnection structure ring of more close silicon through hole surrounds in two corresponding interconnection structure rings is silicon through hole stress to the coverage of interlayer dielectric layer.Can make the electric property of interconnection structure cause harmful effect owing to form interconnection structure at silicon through hole stress in to the coverage of interlayer dielectric layer, therefore, described silicon through hole stress is the silicon through hole to the coverage of interconnection structure to the coverage of interlayer dielectric layer, is the silicon through hole for the scope of the isolated area of interconnection structure.
The stress effect of described silicon through hole may make that also interlayer dielectric layer and metal level deform, adjacent interconnection structure ring short circuit.When test voltage is applied on the adjacent interconnection structure ring, if produce bigger conducting electric current, adjacent interconnection structure ring short circuit shows that the position of corresponding interconnection structure ring is positioned at silicon through hole stress influence scope.
The embodiment of the invention also provides the another kind of method of testing of utilizing described silicon through hole test structure, each interconnection structure ring of described silicon through hole test structure is non-sealing, has opening, please refer to Fig. 5, schematic flow sheet for the method for testing of present embodiment specifically comprises:
Step S201, the opening two ends to each interconnection structure ring apply test voltage successively on away from the direction of silicon through hole, the resistance that test is corresponding;
Step S202 compares described resistance and reference resistance, the maximum magnitude that the stress that acquisition silicon through hole produces exerts an influence to interconnection structure.
Concrete, described test voltage by the opening two ends that are applied to described interconnection structure ring after, record corresponding electric current, thereby obtain the resistance of corresponding interconnection structure ring.
Resistance and the reference resistance of the described interconnection structure ring that several record are compared.Described reference resistance is the resistance that does not have the identical interconnection structure ring of the shape of silicon through hole.When the described resistance that records is identical with reference resistance, show that metal level and conductive plunger in the described interconnection structure ring are not subjected to the stress influence that the silicon through hole produces, do not deform or produce defective, described interconnection structure ring is positioned at outside the stress influence scope of described silicon through hole.When the described resistance that records during greater than reference resistance, show that described interconnection structure environment-development gives birth to deformation or produce defective, described interconnection structure ring has been subjected to the stress influence that the silicon through hole produces, and described interconnection structure ring is positioned at the stress influence scope of described silicon through hole.Therefore, successively to interconnection structure ring test resistance, and resistance and the reference resistance that records compared on away from the direction of silicon through hole.Because when the too close silicon through hole of interconnection structure ring, the stress of silicon through hole can influence the resistance of interconnection structure ring, when certain resistance that records equals described reference resistance for the first time, show that described interconnection structure ring is the border of silicon through hole stress influence scope, the zone that corresponding interconnection structure ring surrounds be silicon through hole stress to the coverage of interconnection structure, be the silicon through hole for the scope of the isolated area of interconnection structure.
To sum up, described at least one interconnection structure ring of the embodiment of the invention is distributed in described silicon through hole periphery ringwise centered by the silicon through hole, and described interconnection structure ring is in series by metal level and the conductive plunger between described metal level of different layers.By the resistance of test interconnection structure ring, and the described resistance that records and reference resistance compared, whether the isolated area scope that can obtain between silicon through hole and the interconnection structure is suitable, and detection method is convenient and swift.
Further, when described interconnection structure ring is at least two, by testing the puncture voltage of adjacent interconnection structure ring, and with the described puncture voltage that records with compare with reference to puncture voltage, can obtain the silicon through hole for the scope of the isolated area of interconnection structure, convenient and swift.
Though the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (13)
1. silicon through hole test structure comprises:
Semiconductor substrate is positioned at the interlayer dielectric layer of described semiconductor substrate surface, is positioned at the silicon through hole of described Semiconductor substrate and interlayer dielectric layer;
It is characterized in that, also comprise that at least one interconnection structure ring, described interconnection structure ring are distributed in described silicon through hole periphery ringwise, described interconnection structure ring is in series by metal level and the conductive plunger between described metal level of different layers.
2. silicon through hole test structure as claimed in claim 1 is characterized in that described metal level comprises two-layer at least.
3. silicon through hole test structure as claimed in claim 1 is characterized in that, when described interconnection structure ring during at least two, described interconnection structure ring is concentric ring and distributes, and the spacing between each interconnection structure equates.
4. silicon through hole test structure as claimed in claim 3 is characterized in that, described concentric ring is distributed as the donut distribution or the concentric rectangles ring distributes.
5. silicon through hole test structure as claimed in claim 1 is characterized in that, described interconnection structure ring is non-sealing.
6. silicon through hole test structure as claimed in claim 1 is characterized in that, the quantity of described silicon through hole is at least one.
7. silicon through hole test structure as claimed in claim 1, it is characterized in that, when described interconnection structure ring when being a plurality of, in the described adjacent interconnection structure ring at the metal level of same layer with equaling the minimal design spacing with the spacing between the conductive plunger of one deck.
8. a method of testing of utilizing silicon through hole test structure as claimed in claim 1 is characterized in that, comprising:
On away from the direction of silicon through hole, successively adjacent interconnection structure circulating application is added test voltage, the puncture voltage that test is corresponding;
With described puncture voltage with compare with reference to puncture voltage, obtain the maximum magnitude that stress that the silicon through hole produces exerts an influence to interlayer dielectric layer.
9. method of testing as claimed in claim 8 is characterized in that, described is the puncture voltage that does not have between two corresponding in the identical interconnection structure ring of the shape of silicon through hole interconnection structure rings with reference to puncture voltage.
10. method of testing as claimed in claim 8, it is characterized in that, when certain puncture voltage that records equals described during with reference to puncture voltage for the first time, the zone that the interconnection structure ring of more close silicon through hole surrounds in two corresponding interconnection structure rings is the stress of silicon through hole to the maximum magnitude of the influence of interlayer dielectric layer.
11. a method of testing of utilizing silicon through hole test structure as claimed in claim 5 is characterized in that, comprising:
Opening two ends to each interconnection structure ring apply test voltage successively on away from the direction of silicon through hole, the resistance that test is corresponding;
Described resistance and reference resistance are compared the maximum magnitude that the stress that acquisition silicon through hole produces exerts an influence to interconnection structure.
12. method of testing as claimed in claim 11 is characterized in that, described reference resistance is the resistance that does not have the identical interconnection structure ring of the shape of silicon through hole.
13. method of testing as claimed in claim 11 is characterized in that, when certain resistance that records equaled described reference resistance for the first time, the zone that corresponding interconnection structure ring surrounds was the maximum magnitude that the stress of silicon through hole exerts an influence to interconnection structure.
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