CN103187258B - The minimizing technology of silicon nitride layer in floating boom manufacture process - Google Patents
The minimizing technology of silicon nitride layer in floating boom manufacture process Download PDFInfo
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- CN103187258B CN103187258B CN201110456273.3A CN201110456273A CN103187258B CN 103187258 B CN103187258 B CN 103187258B CN 201110456273 A CN201110456273 A CN 201110456273A CN 103187258 B CN103187258 B CN 103187258B
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- silicon nitride
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- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 78
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000005516 engineering process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims description 20
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 229920005591 polysilicon Polymers 0.000 abstract description 12
- 230000015654 memory Effects 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 239000011800 void material Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Abstract
The invention discloses the minimizing technology of silicon nitride layer in a kind of floating boom manufacture process, including: substrate is provided, described substrate comprises substrate and substrate is sequentially depositing silicon oxide layer and silicon nitride layer, and fleet plough groove isolation structure, described silicon nitride layer is separated at least one separate part by described fleet plough groove isolation structure；Remove partial nitridation silicon layer；Following step is repeated, until silicon nitride layer is all removed: the recess sidewall formed after removing partial nitridation silicon layer is carried out part removal, and again removes partial nitridation silicon layer.The groove structure formed by the method for the present invention, its cross section is the opening reverse trapezoid shape more than bottom width, this groove structure is in floating boom manufacturing process subsequently, wherein during deposit polycrystalline silicon, ensure that polysilicon is fully filled with whole groove, leave a void defect the most in a groove, it is ensured that prepared floating boom and the quality of memory element, ensure the reliability of memory element.
Description
Technical Field
The invention relates to a semiconductor manufacturing technology, in particular to a method for removing a silicon nitride layer in a floating gate manufacturing process.
Background
Self-aligned floating gate (self-aligned floating gate) is widely used in the manufacturing process of memory cells of flash memories (such as NOR flash memories).
The preparation method of the floating gate in the prior art comprises the following steps:
as shown in fig. 1, a silicon oxide layer 2 and a silicon nitride layer 3 are sequentially deposited on a wafer substrate 1 such as a silicon substrate, and a shallow trench 4 is formed on the substrate 1 by photolithography, the shallow trench 4 penetrating the silicon nitride layer 3 and the silicon oxide layer 2, as shown in fig. 2. Silicon oxide deposition is continued to form Shallow Trench Isolation (STI)5 as shown in fig. 3. The shallow trench isolation 5 is subjected to Chemical Mechanical Polishing (CMP) until the silicon nitride layer 3 is exposed at the surface, at which time the silicon nitride layer 3 is divided by the shallow trench isolation 5 into several independent structures separated from each other, as shown in fig. 4. As shown in fig. 5, the silicon nitride layer 3 is removed to form a plurality of recesses 6. Polysilicon is deposited and chemical mechanical polished to form polysilicon 7 separated from each other as shown in fig. 6. After the formation of the polysilicon, the subsequent existing processes for preparing the floating gate are continued to form the floating gate structure.
In the manufacturing process of the above prior art, referring to fig. 4 to fig. 6, the silicon nitride layer 3 is removed at one time by a dry etching method or a wet etching method, after the silicon nitride layer 3 is removed to form the groove 6, the opening width of the groove 6 is smaller than the groove bottom width, when the polysilicon 7 is deposited in the groove 6, the polysilicon 7 is not easy to completely fill the whole groove 6, and a void is easy to occur in the groove 6, which generates a defect 8 (as shown in fig. 6), which affects the preparation of the floating gate, thereby causing the performance of the memory cell to be reduced or even fail.
Disclosure of Invention
In view of this, the present invention provides a method for removing a silicon nitride layer in a floating gate manufacturing process, so as to ensure that polysilicon deposited in a groove formed by removing the silicon nitride layer can completely fill the whole groove when a subsequent floating gate manufacturing process is performed after the silicon nitride layer is removed, thereby avoiding defects.
The technical scheme of the invention is realized as follows:
a method for removing a silicon nitride layer in the manufacturing process of a floating gate comprises the following steps:
providing a substrate, wherein the substrate comprises a substrate, a silicon oxide layer and a silicon nitride layer which are deposited on the substrate in sequence, and a shallow trench isolation structure, and the shallow trench isolation structure separates the silicon nitride layer into at least one mutually independent part;
removing part of the silicon nitride layer;
repeating the following steps until the silicon nitride layer is completely removed:
and partially removing the side wall of the groove formed after removing part of the silicon nitride layer, and removing part of the silicon nitride layer again.
Further, the width of the opening of the groove formed after the silicon nitride layer is completely removed is larger than the width of the bottom of the groove.
Further, the cross section of the groove is in an inverted trapezoid shape.
Further, a wet etching method is adopted for removing part of the silicon nitride layer, the etching solution is hot phosphoric acid with the temperature of 160 ℃, and the etching rate of the silicon nitride isThe etching time was 5 min.
Further, a wet etching method is adopted for partially removing the side wall of the groove, and HF: H is adopted as etching liquid2Hydrofluoric acid solution with O of 1:200 and silicon oxide etching rate ofThe etching time is 5-10 min.
It can be seen from the above scheme that the new method provided by the method for removing the silicon nitride layer in the floating gate manufacturing process of the present invention replaces the step of removing the silicon nitride layer once in the existing floating gate manufacturing technology, the method adopts a multi-step execution mode for the removal process of the silicon nitride layer, wherein in each step, part of the silicon nitride layer is removed, and in each step, after part of the silicon nitride layer is removed, the sidewalls of the formed grooves are also partially removed, so that in the course of performing each step, the width between the sidewalls of the grooves is widened, and as the steps are increased, the sidewalls of the grooves are correspondingly widened for each removed portion of the silicon nitride layer, so that the groove structure is formed, the width of the opening is wider than that of the bottom of the groove, and after all the silicon nitride layers are removed, the whole groove is in an inverted trapezoidal shape with the cross section being larger than that of the bottom. In the subsequent floating gate manufacturing process, when the polycrystalline silicon is deposited in the groove structure in the shape, the polycrystalline silicon can be ensured to completely fill the whole groove, no gap defect is left in the groove, the quality of the prepared floating gate and the memory cell is ensured, and the reliability of the memory cell is ensured.
Drawings
Fig. 1 to 4 are schematic diagrams illustrating the device structure evolution from the substrate supply to the shallow trench isolation cmp in the floating gate manufacturing method according to the prior art and the embodiment of the present invention;
FIGS. 5 and 6 are schematic diagrams illustrating the device structure evolution during the process of removing the silicon nitride layer and depositing the polysilicon layer in the prior art floating gate preparation method;
FIG. 7 is a flow chart of a method for removing a silicon nitride layer during the manufacture of a floating gate according to the present invention;
fig. 8 to 12 are schematic diagrams illustrating the device structure evolution in the process of removing the silicon nitride layer by using the method of the present invention.
In the drawings, the names corresponding to the reference numbers are as follows:
1. substrate, 2, silicon oxide layer, 3, silicon nitride layer, 4, shallow trench, 5, shallow trench isolation, 6, groove, 7, polysilicon, 8, defect
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and examples.
The method for removing the silicon nitride layer in the floating gate manufacturing process of the present invention, as shown in fig. 7, includes:
providing a substrate, wherein the substrate comprises a substrate, a silicon oxide layer and a silicon nitride layer which are deposited on the substrate in sequence, and a shallow trench isolation structure, and the shallow trench isolation structure separates the silicon nitride layer into at least one mutually independent part;
removing part of the silicon nitride layer;
repeating the following steps until the silicon nitride layer is completely removed:
and partially removing the side wall of the groove formed after removing part of the silicon nitride layer, and removing part of the silicon nitride layer again.
The method of the present invention will now be further described in connection with a floating gate fabrication process.
Referring to fig. 1 to 4, a silicon oxide layer 2 and a silicon nitride layer 3 are sequentially deposited on a wafer substrate 1 such as a silicon substrate. The substrate 1 may comprise any base material capable of being used as a semiconductor device to be built thereon, such as a silicon substrate.
A shallow trench 4 is formed on the substrate 1 by photolithography, the shallow trench 4 penetrating the silicon nitride layer 3 and the silicon oxide layer 2. The method of forming the shallow trench 4 includes, for example: coating photoresist on the surface of a wafer, exposing and developing the photoresist, transferring a predefined pattern onto the photoresist, etching by using the residual photoresist as a mask, and sequentially etching the silicon nitride layer 3, the silicon oxide layer 2 and part of the substrate 1 on the wafer, which are not covered by the photoresist, to form a shallow trench 4. The bottom of the shallow trench 4 is located in the substrate 1.
On the substrate after the formation of the shallow trenches 4, the deposition of silicon oxide is continued, which fills in the shallow trenches 4 forming Shallow Trench Isolations (STI)5 and covers the silicon nitride layers 3 separated from each other by the above-mentioned photolithography process. Then, the device surface is subjected to Chemical Mechanical Polishing (CMP) to remove the silicon oxide covering the silicon nitride layer 3 until the silicon nitride layer 3 is exposed.
The above processes are all the prior art, and can be realized by adopting the conventional method, and the specific process is not described herein again.
Referring to fig. 8 to 12, one embodiment of removing the silicon nitride layer 3 is as follows.
As shown in fig. 8, a portion of the silicon nitride layer 3 is removed, such that the height of the silicon nitride layer 3 is lower than the shallow trench isolation 5 of the silicon oxide, and a groove 6 is formed. Removing part of the silicon nitride layer 3 by wet etching method, wherein the etching solution is hot phosphoric acid with the temperature of 160 ℃, and the etching rate of the silicon nitride isThe etching time was 5 min.
As shown in fig. 9, after removing part of the silicon nitride layer 3, the silicon oxide material on the sidewall of the formed recess 6 (i.e. the sidewall of the shallow trench isolation 5) is partially removed. Removing partial silicon oxide side wall material by wet etching method, and using HF: H as etching liquid2Hydrofluoric acid solution with O (weight ratio) of 1:200 and silicon oxide etching rate ofThe etching time is 5-10 min.
As shown in fig. 10, a part of the silicon nitride layer 3 is removed again. The process is the same as the process for removing part of the silicon nitride layer 3, and is not described in detail.
As shown in fig. 11, the silicon oxide material on the sidewalls of the formed recess 6 portion (i.e., the sidewalls of the shallow trench isolation 5) is again partially removed. The process is the same as the above-mentioned process for removing part of the sidewall material, and is not described again.
The above-described process of removing a part of the silicon nitride layer 3 and a part of the side wall is repeated.
The last remaining silicon nitride layer 3 is removed as shown in fig. 12. The process is the same as the process for removing part of the silicon nitride layer 3, and is not described in detail.
After the above-described repetition of removing a part of the silicon nitride layer 3 and partially removing the side wall of the groove 6 formed after the silicon nitride layer 3 is removed, the formed groove 6 has an inverted trapezoidal shape (the width of the opening of the groove 6 is larger than the width of the groove bottom). The inverted trapezoidal shape ensures that polysilicon can be fully deposited into the recess 6 during the subsequent floating gate fabrication process, avoiding the defects shown in fig. 6, improving the stability of the supported floating gate and device, and thus ensuring the reliability of the memory cell. The last step of the above process is to remove the silicon nitride layer 3 (as shown in fig. 12), and after removing the silicon nitride layer 3, part of the sidewall silicon oxide material is not removed, although the width of the opening near the bottom of the trench, as shown in fig. 12, is slightly smaller than the width of the bottom of the trench after removing the silicon nitride layer 3, which does not affect the subsequent polysilicon deposition and the subsequent floating gate manufacturing process.
The subsequent polysilicon deposition and the subsequent floating gate fabrication can be performed using conventional floating gate fabrication steps, which are not described herein.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (2)
1. A method for removing a silicon nitride layer in the manufacturing process of a floating gate comprises the following steps:
providing a substrate, wherein the substrate comprises a substrate, a silicon oxide layer and a silicon nitride layer which are deposited on the substrate in sequence, and a shallow trench isolation structure, and the shallow trench isolation structure separates the silicon nitride layer into at least one mutually independent part;
removing part of the silicon nitride layer;
repeating the following steps until the silicon nitride layer is completely removed:
removing part of the side wall of the groove formed after removing part of the silicon nitride layer, and removing part of the silicon nitride layer again;
furthermore, the width of the opening of the groove formed after the silicon nitride layer is completely removed is larger than the width of the bottom of the groove; wherein,
removing part of the silicon nitride layer by adopting a wet etching method, wherein the etching liquid is hot phosphoric acid;
partially removing the side wall of the groove by adopting a wet etching method, wherein the etching liquid adopts hydrofluoric acid solution; wherein,
the temperature of the hot phosphoric acid is 160 ℃, and the etching rate of the hot phosphoric acid to the silicon nitride isEtching time is 5 min;
HF H in the hydrofluoric acid solution2O in a weight ratio of 1:200, and an etching rate of silicon oxide ofThe etching time is 5-10 min.
2. The method of claim 1, wherein the silicon nitride layer is removed during the floating gate manufacturing process, and the method further comprises the steps of: the cross section of the groove is in an inverted trapezoid shape.
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| CN201110456273.3A CN103187258B (en) | 2011-12-30 | 2011-12-30 | The minimizing technology of silicon nitride layer in floating boom manufacture process |
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| CN201110456273.3A CN103187258B (en) | 2011-12-30 | 2011-12-30 | The minimizing technology of silicon nitride layer in floating boom manufacture process |
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| CN103187258B true CN103187258B (en) | 2016-08-31 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103943478A (en) * | 2014-04-03 | 2014-07-23 | 武汉新芯集成电路制造有限公司 | Method for manufacturing floating gate structure |
| CN103943549B (en) * | 2014-04-28 | 2016-08-17 | 上海华力微电子有限公司 | A kind of shallow trench oxide cavity and the removing method of floating gate polysilicon concave point |
| CN105336696A (en) * | 2014-06-18 | 2016-02-17 | 上海华力微电子有限公司 | Method for improving STI and FG poly filling hole process window simultaneously |
| CN105470201A (en) * | 2014-06-18 | 2016-04-06 | 上海华力微电子有限公司 | Flash memory device process for simultaneously improving shallow trench isolation (STI) filling holes and floating gate polycrystalline silicon (FG Poly) filling holes |
| CN104078351A (en) * | 2014-06-30 | 2014-10-01 | 上海华力微电子有限公司 | Semiconductor structure manufacturing method |
| CN106469730B (en) * | 2015-08-18 | 2019-06-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor structure |
| CN106298678A (en) * | 2016-08-22 | 2017-01-04 | 上海华力微电子有限公司 | A kind of method for improving of the control gate coefficient of coup |
| CN108717931A (en) * | 2018-05-23 | 2018-10-30 | 武汉新芯集成电路制造有限公司 | A kind of method and semiconductor structure improving floating boom defect |
| CN110610856A (en) * | 2019-09-20 | 2019-12-24 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113223996A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | ETOX structure flash memory floating gate filling method and flash memory thereof |
| CN113808930A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Floating gate manufacturing method and circuit of NOR flash memory and application of floating gate |
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| KR100634404B1 (en) * | 2004-08-04 | 2006-10-16 | 삼성전자주식회사 | Method of forming a pattern without voids and a gate pattern structure formed using the same |
| JP4665455B2 (en) * | 2004-08-09 | 2011-04-06 | 富士ゼロックス株式会社 | Silicon structure manufacturing method, mold manufacturing method, molded member manufacturing method, silicon structure, ink jet recording head, and image forming apparatus |
| KR20070118348A (en) * | 2006-06-12 | 2007-12-17 | 삼성전자주식회사 | Manufacturing method of nonvolatile memory device |
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