CN103178062A - Metal nanocrystalline storage - Google Patents

Abstract

The invention discloses a metal nanocrystal memory. The metal nanocrystal memory comprises: a substrate; source terminals and drain terminals formed on both sides of the substrate channel region; layer and gate electrode; wherein, the metal nanocrystal storage layer is formed by depositing metal nanocrystal colloid on the tunnel dielectric layer by spraying method and evaporating the solvent in the metal nanocrystal colloid. The metal nanocrystalline memory of the present invention is realized based on the method of laser ablation and spray gun spraying. Compared with the conventional preparation of nanocrystalline floating gate non-volatile memory, it has the advantages of low cost, controllable nanoparticle diameter, good uniformity and no pollution. , Excellent device performance and many other advantages.

Description

A metal nanocrystalline memory

technical field

The invention relates to the technical field of memory in the microelectronics industry, in particular to a metal nanocrystal memory.

Background technique

The current microelectronics products are mainly divided into two categories: logic devices and storage devices, and storage devices occupy a very important position in the field of microelectronics. Storage devices can generally be classified into volatile memories and non-volatile memories. The main feature of non-volatile memory is the ability to retain stored information for a long period of time without power on. It not only has the characteristics of read-only memory, but also has high access speed, and is easy to erase and rewrite, and consumes less power. With the demand for large-capacity and low-power storage in multimedia applications and mobile communications, the market share of non-volatile memory, especially flash memory (Flash), is becoming larger and larger, and is also increasing. The more it becomes a very important memory type. For these memories, how to improve the performance and simplify the process by adjusting the structural materials, and effectively control the process cost is an urgent problem to be solved. Flash memory represented by nanocrystalline memory has advantages in this regard.

The core of traditional Flash memory is silicon-based non-volatile memory based on polysilicon thin film floating gate structure. However, polysilicon thin film floating gate devices have disadvantages such as complicated manufacturing process, long writing time, and high writing power consumption. Moreover, with the continuous reduction of technology nodes, the tunnel dielectric layer of devices is getting thinner and thinner, which makes the charge leakage problem of devices more and more serious. This is because for traditional polysilicon thin film floating gate memory, a defect on the tunnel oxide layer will form a fatal discharge channel and cause the device to fail. In order to solve this problem, a charge-trap memory is proposed. Using the characteristics of localized storage of charges in the trapping layer, the charge-trapping memory realizes discrete charge storage, and the defects on the tunneling dielectric layer only cause local charge leakage, which makes the charge more stable. Among them, nanocrystalline memory has attracted more attention due to its advantages of using a thinner tunnel oxide layer, lower program/erase (P/E) voltage, faster P/E speed, and stronger data retention. The scientific community and the industry are of great concern. At the same time, the introduction of high-K materials as the tunneling dielectric layer and the charge blocking layer can effectively solve the trade-off problem between data retention and high erasability. Because of the high-K gate dielectric, the physical thickness of the gate dielectric layer will be higher than that of traditional materials (such as silicon dioxide, silicon nitride) under the condition that the unit gate capacitance remains unchanged, which can effectively solve the problem of gate leakage current And maintain a high programming and erasing speed. Trap-trap memories using nanocrystalline materials can meet the needs of high-performance memories and have been extensively studied. At the same time, compared with Si or Ge nanocrystals, metal nanocrystals have greater advantages, such as adjustable work function, high density of states near the Fermi level, and small perturbation. Therefore, they are favored by the industry and scientific research circles. extensive attention.

Preparation of nanocrystalline memory, wherein the key process is the preparation of nanocrystalline thin film. There are various preparation methods, mainly including the following: (1) ion implantation method to form nanocrystalline particles; (2) rapid thermal annealing method to form nanocrystalline particles; (3) CVD direct growth method to prepare nanocrystalline particles .

In the process of realizing the present invention, the applicant realized that the prior art metal nanocrystal storage device has the following technical defects: the metal nanocrystal particles have large diameter and poor uniformity, which seriously affects the storage performance of the floating gate memory.

Contents of the invention

(1) Technical problems to be solved

In order to solve one or more of the above problems, the present invention provides a method for preparing a metal nanocrystal memory, so as to improve the quality of the metal nanocrystal layer and reduce the process complexity and cost of preparing the metal nanocrystal memory.

(2) Technical solutions

According to one aspect of the present invention, a metal nanocrystal memory is provided. The metal nanocrystal memory includes: a substrate; source terminals and drain terminals formed on both sides of the substrate channel region; layer and gate electrode; wherein, the metal nanocrystal storage layer is formed by depositing metal nanocrystal colloid on the tunnel dielectric layer by spraying and evaporating the solvent in the metal nanocrystal colloid.

(3) Beneficial effects

It can be seen from the above technical scheme that the metal nanocrystal memory of the present invention has the following beneficial effects:

(1) The nanocrystalline memory of the present invention combines the charge localized storage characteristics of nanocrystals and the anti-leakage characteristics of high-K gate dielectrics;

(2) The metal nanocrystalline memory of the present invention is realized based on the method of laser ablation and spray gun spraying. Compared with the conventional preparation of nanocrystalline floating gate non-volatile memory, it has low cost, controllable nanoparticle diameter, and good uniformity. , No pollution, excellent device performance and many other advantages.

Description of drawings

1A is a schematic cross-sectional view of a metal nanocrystal memory according to an embodiment of the present invention;

1B is a schematic diagram of a three-dimensional structure of a nanocrystalline memory according to an embodiment of the present invention;

2A is a schematic diagram of a NOR array composed of nanocrystalline memory according to an embodiment of the present invention;

Figure 2B is a schematic diagram of the direction of the NOR array shown in Figure 2A;

3A is a schematic structural diagram along the A-A' direction after the substrate is subjected to shallow trench isolation in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

3B is a schematic structural view along the B-B' direction after the substrate is subjected to shallow trench isolation in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

4A is a schematic structural diagram along the A-A' direction after depositing a high-K tunnel dielectric layer in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

4B is a schematic structural view along the B-B' direction after depositing a high-K tunnel dielectric layer in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

5A is a schematic diagram of a metal nanocrystal colloid device prepared by laser ablation in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

5B is a schematic diagram of a spray gun used for depositing a metal nanocrystal colloid in a method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

6A is a schematic structural diagram along the A-A' direction after forming a metal nanocrystal storage layer in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

6B is a schematic structural diagram along the B-B' direction after forming a metal nanocrystal storage layer in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

7A is a schematic structural view along the A-A' direction after depositing a charge blocking layer in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

7B is a schematic structural view along the B-B' direction after depositing a charge blocking layer in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

Fig. 8 is a schematic structural view of the A-A' direction after etching in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

9A is a schematic structural diagram along the A-A' direction after depositing a gate in the method for manufacturing a metal nanocrystal memory according to an embodiment of the present invention;

9B is a schematic structural diagram along the B-B' direction after depositing the gate in the method for manufacturing the metal nanocrystal memory according to the embodiment of the present invention;

Fig. 10 is a schematic structural diagram along the B-B' direction after etching along the B-B' direction in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention;

Fig. 11 is a schematic diagram of the structure along the B-B' direction after the source terminal and the drain terminal are formed in the method for fabricating the metal nanocrystal memory according to the embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. While illustrations of parameters including particular values may be provided herein, it should be understood that parameters need not be exactly equal to the corresponding values, but rather may approximate the values within acceptable error margins or design constraints.

In an exemplary embodiment of the present invention, a metal nanocrystal memory is provided. FIG. 1A is a schematic cross-sectional view of a metal nanocrystal memory according to an embodiment of the present invention. FIG. 1B is a schematic diagram of a three-dimensional structure of a nanocrystalline memory according to an embodiment of the present invention. As shown in FIG. 1A and FIG. 1B , the metal nanocrystalline memory of this embodiment includes: a substrate 101; a source terminal 102 and a drain terminal 103 formed on both sides of the channel region of the substrate; a tunnel formed above the channel region of the substrate. the metal nanocrystal storage layer 105 formed above the tunnel dielectric layer 104 ; the charge blocking layer 106 formed above the metal nanocrystal storage layer 105 ; and the gate electrode 107 formed above the charge blocking layer 106 . Wherein, the metal nanocrystal storage layer is formed by the metal nanoparticle remaining after the metal nanocrystal colloid is deposited on the tunnel dielectric layer 104 by spraying method and the solvent in the metal nanocrystal colloid is evaporated. Moreover, the metal nanocrystal colloid is produced by laser ablation.

In this embodiment, the metal nanocrystalline storage layer 105 is preferably a single layer, its particle size is between 2-15nm (depending on the process conditions), and the material is gold (Au), silver (Ag), platinum (Pt) Metallic materials with large work functions.

In this embodiment, the material of the gate electrode can be selected from precious metals platinum (Pt), silver (Ag), palladium (Pd); commonly used metals tungsten (W), titanium (Ti), aluminum (Al), copper (Cu); metal oxides ITO (indium tin oxide), IZO (indium zinc oxide), etc. and polysilicon materials.

In this embodiment, both the tunneling dielectric layer and the charge blocking layer are high-K materials, that is, materials with a high dielectric constant, which are generally higher than silicon nitride (Si ₃ N ₄ ), such as hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ) or other materials with similar properties or stacked by multi-layer materials (such as HfO ₂ /Al ₂ O ₃ double-layer).

In this embodiment, the metal nanocrystal memory comprehensively utilizes the charge localization storage characteristic of the metal nanocrystal and the leakage prevention characteristic of the high-K gate dielectric, which can greatly improve the storage performance of the metal nanocrystal memory. In particular, in this embodiment, the metal nanocrystal storage layer is deposited on the tunneling medium layer by spraying the metal nanocrystal colloid. The diameter of the nanoparticles is controllable, the uniformity is good, and there is no chemical pollution. Performance of Nanocrystalline Memory.

In another exemplary embodiment of the present invention, a method for preparing the above-mentioned metal nanocrystal memory is also provided. For the convenience of explanation, the directions on the substrate are specified first.

FIG. 2A is a schematic diagram of a NOR array composed of nanocrystalline memory according to an embodiment of the present invention. As shown in FIG. 2A , the drains of the nanocrystalline memories in the same row are connected to the bit line; the gates of the nanocrystalline memories in the same column are connected to the word line, and their sources are connected to the source line (SL). It should be noted that the NOR array structure shown in FIG. 2A is the same as the NOR array structure in the prior art, and will not be described in detail here.

FIG. 2B is a schematic diagram of the orientation of the NOR array shown in FIG. 2A . As shown in FIG. 2B, the A-A' direction corresponds to the word line direction (WL) of the NOR array, and the B-B' direction corresponds to the bit line direction of the NOR array. The present embodiment will be described in detail below in conjunction with the directions specified in FIG. 2B . The method for preparing a metal nanocrystal memory according to the embodiment of the present invention includes:

Step S302, performing ion implantation and rapid annealing on the substrate (for adjusting the doping concentration distribution of the substrate); depositing a sacrificial oxide layer (for preventing damage to the surface by the next implantation), and after depositing the oxide layer Threshold adjustment implantation and punch-through prevention implantation are performed on the substrate.

In this step, the substrate is preferably a silicon substrate, and may also be a germanium substrate. Ion implantation is a step that must be carried out on the surface of the substrate except for shallow trench isolation. After ion implantation, rapid annealing is also performed. The purpose is to make ions evenly doped on the substrate surface. The temperature of rapid annealing is roughly 500 ~ It varies from 1000°C, which is related to the ion implantation metering.

Step S304: forming shallow trench isolation (Shallow Trench Isolation, referred to as STI) on the substrate, as shown in FIG. 3A and FIG. 3B;

Among them, FIG. 3A is a schematic structural diagram along the A-A' direction after performing shallow trench isolation on the substrate in the method for fabricating the metal nanocrystal memory according to the embodiment of the present invention. Fig. 3B is a schematic diagram of the structure along the B-B' direction after performing shallow trench isolation on the substrate in the method for manufacturing the metal nanocrystal memory according to the embodiment of the present invention. In FIG. 3A and FIG. 3B , 301 is shallow trench isolation, 303 and 302 are threshold adjustment implantation and anti-punching implantation respectively, and 304 is a sacrificial oxide layer.

Step S306: removing the sacrificial oxide layer 304, and depositing a high-K tunneling dielectric layer 104, as shown in FIG. 4A and FIG. 4B;

Among them, FIG. 4A is a schematic diagram of the structure along the A-A' direction after depositing a high-K tunnel dielectric layer in the method for fabricating a metal nanocrystal memory according to an embodiment of the present invention. Fig. 4B is a schematic structural diagram along the B-B' direction after depositing a high-K tunneling dielectric layer in the method for fabricating a metal nanocrystal memory according to an embodiment of the present invention.

In this step, both the tunneling dielectric layer and the charge blocking layer are high-K materials, that is, materials with a high dielectric constant, whose dielectric constant is generally higher than that of silicon nitride Si ₃ N ₄ , such as hafnium oxide (HfO ₂ ), Aluminum oxide (Al ₂ O ₃ ), titanium oxide, zirconium oxide, hafnium aluminum oxide, hafnium oxynitride or other materials with similar properties or stacked by multi-layer materials (such as HfO ₂ /Al ₂ O ₃ double layers) have similar properties Structure.

Step S308, using a spray gun to deposit metal nanocrystal colloids on the tunneling dielectric layer;

In this step, the metal material in the metal nanocrystal colloid is gold (Au), silver (Ag), platinum (Pt), and other metal materials with relatively large work functions. The particle size of the metal material is between 2nm and 15nm.

5A is an ablation optical path diagram of metal nanocrystal colloid prepared by laser ablation in the method for preparing metal nanocrystal memory according to the embodiment of the present invention. The ablation optical path includes: laser b01, attenuator b02, power detector b03, convex lens b04, total reflection mirror b05; cuvette b06. A laser power detector b03 and an attenuator b02 are set in the ablation optical path for monitoring and adjusting the power of the laser. Cuvette b06 is used to place water solvent and metal target. Specifically, both the metal target b07 and the solvent b08 are placed in the cuvette b06, the laser is focused by the convex lens and then irradiated by the total reflection mirror on the metal target in the cuvette, and the metal atoms or atomic groups escape from the metal target Nanocrystalline particles are formed on the surface, and the metal nanocrystals form a colloid in solvent b08.

Here, the solvent b08 of this embodiment is a water solvent, in which sodium dodecyl sulfate (SDS) or p-tetrakis-(4-N-methylpyridine) porphyrin (H2TMPyP) is added as an active agent. Of course, the solvent b08 can also be an organic solvent, such as acetonitrile (CH3CN), etc., and in the case of using an organic solvent, no active agent is needed. In addition, specific metals may require different surfactants, but the above-mentioned metal materials with larger work functions can fully meet the requirements with water solvent and SDS active agent, and the use of aqueous solution has the advantages of convenient transfer and cost saving. Nanocrystals prepared by laser ablation have the advantages of good particle uniformity and no chemical pollution. In addition, during the specific operation process, the rate and size of nanoparticle generation can be adjusted by adjusting the power and wavelength of the laser.

Taking the preparation of silver nanocrystals as an example, the frequency doubled light generated by Nd:YAG laser is 532nm, the pulse width is 10ns, and the repetition frequency is 10Hz. Through the attenuator to adjust the light intensity and split 40% for monitoring power. The ablation beam is focused on the metal target immersed in the aqueous solution through a 150mm quartz lens; the silver nanoparticles ablated by the laser will melt in the aqueous solution to form silver nanocrystal colloids.

The metal nanocrystal colloid in the cuvette b06 is transferred to the sample chamber c01 of the above-mentioned spray gun through a glue tip dropper or a small measuring cup.

FIG. 5B is a schematic diagram of a spray gun used for depositing metal nanocrystal colloid in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention. The spray gun that adopts in the present embodiment is the Richpen 112B type spray gun of Japan Fuso Seiki Co., Ltd. The process of depositing metal nanocrystal colloids comprises: at first the prepared metal nanocrystal colloids are loaded into the sample chamber c01, the substrate of the deposited tunnel dielectric layer is placed on the heating table c05; nitrogen gas is fed through nitrogen gas inlets c02 and c03 ( or inert gas) as a protective gas to ensure that the entire process is completed under a protective atmosphere; the spray gun head c04 sprays the nanocrystalline colloid in the sample chamber c01 on the high-temperature substrate placed on the heating table c05. For different materials, the parameters of spray gun settings are different. Taking silver nanocrystalline colloid as an example, the temperature of the heating table is 190 degrees Celsius, and the nitrogen pressure is 2bar. Adjust the flow rate through the flow button on the spray gun to control the final thickness. , the thickness of the nanocrystal storage layer is one layer of nanocrystal.

Step S210, volatilize the solvent in the metal nanocrystal colloid, and the remaining metal nanocrystals form a metal nanocrystal storage layer 105 on the surface of the tunneling medium layer, as shown in FIGS. 6A and 6B ;

Fig. 6A is a schematic structural diagram along the A-A' direction after forming a metal nanocrystal storage layer in the method for fabricating a metal nanocrystal memory according to an embodiment of the present invention. Fig. 6B is a schematic structural diagram along the B-B' direction after forming a metal nanocrystal storage layer in the method for fabricating a metal nanocrystal memory according to an embodiment of the present invention.

In this step, the moisture of the metal nanocrystal colloid can be dried naturally, or the substrate on which the metal nanocrystal colloid is sprayed and deposited can be dried for 180 minutes in a drying oven at 190 degrees under a nitrogen atmosphere. The use of a drying box can save time, and there is less water residue, which is conducive to the realization of the later steps.

Step S212, depositing a high-K dielectric charge blocking layer 106 on the metal nanocrystal storage layer, as shown in FIG. 7A and FIG. 7B;

Fig. 7A is a schematic structural diagram along the direction A-A' after depositing a charge blocking layer in the method for fabricating a metal nanocrystal memory according to an embodiment of the present invention. Fig. 7B is a schematic diagram of the structure along the B-B' direction after depositing the charge blocking layer in the method for fabricating the metal nanocrystal memory according to the embodiment of the present invention.

In this step, the material of the charge blocking layer is similar to that of the aforementioned tunneling dielectric layer, and will not be described in detail here.

Step S212, etching along the A-A' direction, etching away the tunneling layer, nanocrystalline storage layer and barrier layer above the shallow trench isolation;

Fig. 8 is a schematic diagram of the structure after etching in the A-A' direction in the method for preparing the metal nanocrystal memory according to the embodiment of the present invention.

Step S214, depositing a gate material 107 on the etched substrate, as shown in FIGS. 9A and 9B ;

Fig. 9A is a schematic diagram of the structure along the direction A-A' after depositing the gate in the method for fabricating the metal nanocrystal memory according to the embodiment of the present invention. Fig. 9B is a schematic diagram of the structure along the B-B' direction after the gate electrode is deposited in the method for fabricating the metal nanocrystal memory according to the embodiment of the present invention.

In this step, the gate is polysilicon, metal, metal silicide or a structure with similar properties stacked by multiple layers of materials.

Step S216, etching along the BB' direction on the substrate after the gate is deposited, etching away the tunneling layer, nanocrystalline storage layer, barrier layer and gate material layer above the substrate to form the gate 107 , as shown in Figure 10;

Fig. 10 is a schematic diagram of the structure along the B-B' direction after etching along the B-B' direction in the method for preparing a metal nanocrystal memory according to an embodiment of the present invention.

Step S218, forming a source terminal and a drain terminal on the silicon substrate exposed by etching (B-B' direction), as shown in FIG. 11 ;

Fig. 11 is a schematic diagram of the structure along the B-B' direction after the source terminal and the drain terminal are formed in the method for fabricating the metal nanocrystal memory according to the embodiment of the present invention. In Fig. 11, 102 is the drain doping region opposite to the doping type of the channel region, 103 is the source doping region opposite to the doping type of the channel region, and the source is in common communication along the A-A' direction Yes, a common source structure is formed, a03 is the anti-penetration injection region, and a04 is the side wall.

In step S220 , metal electrodes are fabricated, and bit lines and word lines are respectively drawn out from the doped drain region and the gate region to form a non-volatile memory array. Wherein, the electrode material can be metal, polysilicon, metal oxide, silicide and other materials.

In summary, the nanocrystal memory of the present invention comprehensively utilizes the charge localized storage characteristics of nanocrystals and the leakage prevention characteristics of high-K gate dielectrics, and can provide the comprehensive storage performance of metal nanocrystal memory. Furthermore, the nanocrystalline memory provided by the present invention is realized based on the method of laser ablation and spray gun spraying. Compared with the conventional preparation of nanocrystalline floating gate non-volatile memory, it has low cost, controllable nanoparticle diameter, and good uniformity. , No pollution, excellent device performance and many other advantages.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. A metal nanocrystal memory, characterized in that, comprising: Substrate; source and drain terminals formed on both sides of the channel region of the substrate; and sequentially forming a tunnel dielectric layer, a metal nanocrystal storage layer, a charge blocking layer and a gate electrode above the channel region of the substrate; Wherein, the metal nanocrystal storage layer is formed by depositing metal nanocrystal colloid on the tunneling medium layer by spraying and evaporating the solvent in the metal nanocrystal colloid. 2. The nanocrystalline memory according to claim 1, wherein the metal nanocolloid is prepared by laser ablation. 3 . The nanocrystal memory according to claim 1 , wherein the metal nanocrystal storage layer is a single layer of metal nanocrystal particles, the particle size of which is between 2-15 nm. 4 . 4. The nanocrystal memory according to claim 3, wherein the material of the metal nanocrystal memory layer is a metal material with a large work function. 5 . The nanocrystalline memory according to claim 4 , wherein the metal material with high work function is gold, silver or platinum. 6. The nanocrystalline memory according to any one of claims 1 to 5, characterized in that, the materials of the tunneling dielectric layer and the charge blocking layer are high dielectric constant materials. 7 . The nanocrystalline memory according to claim 6 , wherein the high dielectric constant material is hafnium oxide, aluminum oxide, or hafnium oxide/aluminum oxide double-layer stack. 8. The nanocrystalline memory according to any one of claims 1 to 5, wherein the material of the gate electrode is platinum, silver, palladium, tungsten, titanium, aluminum, copper, ITO, IZO or polysilicon material .

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