CN103176320A - Transversely-distributed pixel structure, liquid crystal display (LCD) device and manufacture method of pixel structure and LCD device - Google Patents
Transversely-distributed pixel structure, liquid crystal display (LCD) device and manufacture method of pixel structure and LCD device Download PDFInfo
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Abstract
The invention discloses a transversely-distributed pixel structure, a liquid crystal display (LCD) device and a manufacture method of the pixel structure and the LCD device. Each data line of the pixel structure is respectively connected with source electrodes of two thin film transistors in an electric mode, and different data lines are in electric connection with different thin film transistors. Gate electrodes of the two thin film transistors in electric connection with the same data line are respectively connected with different gate lines in an electric mode. A pixel electrode of a first sub-pixel area is partially overlapped with a pixel common line to form a storage capacitor. A pixel electrode of a second sub-pixel area is partially overlapped with a gate line opposite to the gate line in electric connection with the gate electrode of the thin film transistor corresponding to the pixel electrode of the second sub-pixel area to form a storage capacitor. A pixel electrode of a third sub-pixel area is partially overlapped with a pixel common line of a next pixel unit to form a storage capacitor. The pixel structure is arranged in one pixel unit, two common lines are reduced in the prior art, the area of a shading area is reduced, and the aperture ratio of the LCD device is improved.
Description
Technical field
The present invention relates to the display technique field, especially relate to a kind of transversely arranged dot structure and liquid crystal indicator and preparation method thereof.
Background technology
Liquid crystal display (Liquid crystal disLlay, LCD) is a kind of flat-panel screens that is widely used at present.General, the viewing area of LCD comprises a plurality of main pixel regions, each main pixel region comprises three sub-pixel area, be provided with a thin film transistor (TFT) (thin film transistor in each sub-pixel area, TFT) and pixel electrode (Pixel Electrode), this thin film transistor (TFT) is switch module.
Usually, in 3D shows, for fear of departing from and aberration of the Show Color that causes because of stopping of the grating grid of longitudinal arrangement, usually the sub-pixel area of each color is transversely arranged, present pixel horizontal mode comprises following several: the pixel horizontal mode that the pixel horizontal mode that the pixel horizontal mode of the horizontal use of perpendicular screen that single grid drives, bigrid drive and three grids drive.
in prior art, no matter adopt the liquid crystal indicator of the dot structure of which kind of horizontal mode, wherein memory capacitance is all by pixel electrode and public electrode is overlapping forms, concrete, as shown in Figure 1, the pixel horizontal mode that drives take three grids is as example, the main pixel region of each on tft array substrate comprises three sub-pixel area that vertically are arranged in order, has a TFT in each sub-pixel area, data line is connected longitudinally by one for the source electrode of the TFT of each row, the grid of the TFT of every delegation is connected by a gate line, the drain electrode of each TFT is connected with the pixel electrode of the sub-pixel area at its place respectively, the memory capacitance of each sub-pixel area by the pixel electrode of this sub-pixel area with the public electrode lead-in wire com that is positioned at this sub-pixel area with the shading line is overlapping forms.As shown in Figure 1, the memory capacitance of sub-pixel area R11 by the pixel electrode 11 of this sub-pixel area with public electrode lead-in wire com1 with shading line 12 is overlapping forms.
In sum, the dot structure of prior art, remove outside two public electrode lead-in wires (hereinafter to be referred as concentric line) between main pixel region, the adjacent position of each gate line or data line all is provided with a concentric line and corresponding shading line, described shading line is used for covering the gap portion between gate line and concentric line, and this will inevitably cause the aperture opening ratio of liquid crystal indicator to reduce.
Summary of the invention
for solving the problems of the technologies described above, the transversely arranged dot structure that the embodiment of the present invention provides a kind of bigrid to drive, liquid crystal indicator and preparation method thereof, can be applicable to copline conversion (In-Plane Switching, be called for short IPS), fringe field switching (Fringe Field Swithing, be called for short FFS) or twisted nematic (Twisted Nematic, abbreviation TN) liquid crystal indicator of drive pattern, liquid crystal indicator more of the prior art, public electrode lead-in wire and shading line have been reduced, improved the aperture opening ratio of liquid crystal indicator.
For addressing the above problem, the embodiment of the present invention provides following technical scheme:
The transversely arranged dot structure that a kind of bigrid drives comprises:
By along two adjacent pixel cells that main pixel region forms of first direction, wherein, each main pixel region comprises respectively the first sub-pixel area, the second sub-pixel area, the 3rd sub-pixel area that is arranged in order along second direction, and described first direction is substantially vertical with described second direction;
Six thin film transistor (TFT)s are arranged at respectively in corresponding sub-pixel area;
The pixel electrode that is arranged in each sub-pixel area and is electrically connected to the drain electrode of corresponding thin film transistor (TFT), described pixel electrode covers on the photic zone of sub-pixel area;
Be parallel to described first direction, and be arranged at respectively two gate lines between interior adjacent two sub-pixel area of each main pixel region;
Be parallel to described second direction, and be arranged at respectively between two main pixel regions of described pixel cell or be arranged at three data lines outside two main pixel regions;
Be parallel to a pixel concentric line of described gate line, the pixel electrode part of this pixel concentric line and the first sub-pixel area is overlapping, forms the memory capacitance of this sub-pixel area;
Wherein, every data line is electrically connected to the source electrode of two thin film transistor (TFT)s respectively, and the thin film transistor (TFT) that different data lines is electrically connected to is different; The grid of two thin film transistor (TFT)s that are electrically connected to from the same data line is electrically connected to different gate line respectively;
The gate line part of the gate line offside that the grid of the pixel electrode of the second sub-pixel area and the thin film transistor (TFT) corresponding with it is electrically connected to is overlapping, forms the memory capacitance of this sub-pixel area;
The pixel concentric line part of the pixel electrode of the 3rd sub-pixel area and next pixel cell is overlapping, forms the memory capacitance of this sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
The embodiment of the invention also discloses a kind of liquid crystal indicator, comprising:
First substrate, second substrate and the liquid crystal layer between first substrate and second substrate;
Wherein, comprise on described first substrate:
The transversely arranged dot structure that above-described bigrid drives, described pixel cell is the array repeated arrangement;
An edge concentric line that is parallel to described gate line, be positioned at one side that described first substrate does not arrange the pixel concentric line, overlapping with pixel electrode and this edge concentric line part of this edge concentric line next-door neighbour's the 3rd sub-pixel area, form the memory capacitance of the 3rd sub-pixel area.
The embodiment of the invention also discloses the method for making of more than one liquid crystal indicators, comprising:
First substrate is provided;
Form a plurality of gate lines, a plurality of pixel concentric line and edge concentric line that is parallel to each other on described first substrate, described a plurality of gate line, a plurality of pixel concentric line and an edge concentric line form in same lithography step, and be formed on same conductive layer, wherein, described edge concentric line is positioned at one side that described first substrate does not arrange the pixel concentric line, overlapping with pixel electrode and this edge concentric line part of this edge concentric line next-door neighbour's the 3rd sub-pixel area, form the memory capacitance of the 3rd sub-pixel area;
Form the first medium layer on described a plurality of gate lines, a plurality of pixel concentric line and concentric line surface, an edge;
Form semiconductor layer, a plurality of data lines that are parallel to each other on described semiconductor layer surface on described first medium layer surface;
Form the second medium layer on described data line surface, form through hole at the second medium layer region that is positioned on the drain surface of thin film transistor (TFT);
Form pixel electrode above described second medium layer, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole;
Wherein, in described pixel cell, the pixel concentric line part of the pixel electrode of the first sub-pixel area and this pixel cell is overlapping, forms the memory capacitance of the first sub-pixel area;
The gate line part of the gate line offside that the grid of the pixel electrode of described the second sub-pixel area and the thin film transistor (TFT) corresponding with it is electrically connected to is overlapping, forms the memory capacitance of the second sub-pixel area;
The pixel concentric line part of the pixel electrode of described the 3rd sub-pixel area and next pixel cell is overlapping, form the memory capacitance of the 3rd sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
Compared with prior art, technique scheme has the following advantages:
transversely arranged dot structure and liquid crystal indicator that the bigrid that the embodiment of the present invention provides drives, can be applicable to IPS, the liquid crystal indicator of FFS or TN drive pattern, in a pixel cell, reduced by two concentric lines than prior art, namely only keep along the concentric line between every 2 pixel cells of data line direction arrangement, in the embodiment of the present invention, the memory capacitance of the second sub-pixel area is mainly by the pixel electrode of this sub-pixel area and overlapping formation of gate line of non-this sub-pixel area, the memory capacitance of the first sub-pixel area and the 3rd sub-pixel area is by the pixel electrode of this sub-pixel area and overlapping formation of concentric line of close this sub-pixel area, thereby can omit concentric line and the shading line of gate line adjacent position, owing to having omitted the shading line and having reduced the quantity of concentric line, reduced simultaneously the area of lightproof area, thereby improved the aperture opening ratio of liquid crystal indicator.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, during the below will describe embodiment, the accompanying drawing of required use is done to introduce simply, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic diagram of the transversely arranged dot structure that drives of three grids that prior art provides;
Fig. 2 is the transversely arranged dot structure schematic diagram that a kind of bigrid that the embodiment of the present invention provides drives;
Fig. 3 is the transversely arranged dot structure schematic diagram that another kind of bigrid that the embodiment of the present invention provides drives;
Fig. 4 is the transversely arranged dot structure vertical view that a kind of bigrid that the embodiment of the present invention provides drives;
Fig. 5 is the sectional view in the transversely arranged dot structure A-A ' zone that drives of a kind of bigrid that the embodiment of the present invention provides;
Fig. 6 is the sectional view in the transversely arranged dot structure B-B ' zone that drives of a kind of bigrid that the embodiment of the present invention provides;
Fig. 7 is the dot structure figure of the liquid crystal indicator of available technology adopting TN type of drive;
Fig. 8 is the dot structure figure of the liquid crystal indicator of the employing TN type of drive that provides of the embodiment of the present invention;
Fig. 9 is the dot structure figure of the liquid crystal indicator of the employing FFS type of drive that provides of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the present invention is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
Just as stated in the Background Art, the aperture opening ratio of liquid crystal indicator of the prior art is lower, the inventor studies discovery, the reason that this problem occurs is, in liquid crystal indicator of the prior art, the adjacent position of each gate line or data line all is provided with a public electrode lead-in wire and corresponding shading line, and namely concentric line and shading line are too much, will inevitably cause the aperture opening ratio of liquid crystal indicator to reduce.
the mode of operation of liquid crystal indicator mainly is divided into normal white mode and Chang Hei pattern, TN type liquid crystal indicator adopts normal white mode, this liquid crystal indicator is controlled the distribution of electrodes of liquid crystal molecule on two plate bases, the direction of an electric field that applies is perpendicular to substrate, when not applying electric field, liquid crystal molecule parallel substrate alignment direction, incident light can see through polaroid, screen display is white screen, the alignment direction of first substrate and second substrate becomes 90 ° of cross-over configuration (the up and down polaroid also becomes 90 degree to arrange), after applying electric field, liquid crystal molecule is to moving perpendicular to orientation substrate, the liquid crystal indicator of IPS or FFS type adopts normal black pattern, its direction of an electric field is level, liquid crystal molecule is under the effect of electric field, be parallel to substrate and carry out twisting motion, and liquid crystal molecule parallel substrate orientation, generally, the polarizing axis of bottom polaroid is joined as identical with liquid crystal molecule, the polarizing axis of upper strata polaroid becomes with it 90 °, when not applying electric field, incident light can't pass through the upper strata polaroid, make screen present lighttight blank screen state (i.e. " often black pattern "), after applying electric field, liquid crystal molecule can reverse, change the direction that incident light is advanced, make incident light can pass through the upper strata polaroid, present light transmission state.
Transversely arranged dot structure and liquid crystal indicator that the disclosed bigrid of the embodiment of the present invention drives can be applicable to the liquid crystal indicator of IPS, FFS or TN type of drive, and this dot structure comprises:
By along two adjacent pixel cells that main pixel region forms of first direction, wherein, each main pixel region comprises respectively the first sub-pixel area, the second sub-pixel area, the 3rd sub-pixel area that is arranged in order along second direction, and described first direction is substantially vertical with described second direction;
Six thin film transistor (TFT)s are arranged at respectively in corresponding sub-pixel area;
The pixel electrode that is arranged in each sub-pixel area and is electrically connected to the drain electrode of corresponding thin film transistor (TFT), described pixel electrode covers on the photic zone of sub-pixel area;
Be parallel to described first direction, and be arranged at respectively two gate lines between interior adjacent two sub-pixel area of each main pixel region;
Be parallel to described second direction, and be arranged at respectively between two main pixel regions of described pixel cell or be arranged at three data lines outside two main pixel regions;
Be parallel to a pixel concentric line of described gate line, the pixel electrode part of this pixel concentric line and the first sub-pixel area is overlapping, forms the memory capacitance of this sub-pixel area;
Wherein, every data line is electrically connected to the source electrode of two thin film transistor (TFT)s respectively, and the thin film transistor (TFT) that different data lines is electrically connected to is different; The grid of two thin film transistor (TFT)s that are electrically connected to from the same data line is electrically connected to different gate line respectively;
The pixel electrode of the second sub-pixel area with and the gate line part of the gate line offside that is electrically connected to of the grid of the thin film transistor (TFT) corresponding with it overlapping, form the memory capacitance of this sub-pixel area;
The pixel concentric line part of the pixel electrode of the 3rd sub-pixel area and next pixel cell is overlapping, forms the memory capacitance of this sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
in the embodiment of the present invention in a pixel cell, reduced by two concentric lines than prior art, namely only keep along the concentric line between every 2 pixel cells of data line direction arrangement, in the embodiment of the present invention, the memory capacitance of the second sub-pixel area is mainly by the pixel electrode of this sub-pixel area and overlapping formation of gate line of non-this sub-pixel area, the memory capacitance of the first sub-pixel area and the 3rd sub-pixel area is by the pixel electrode of this sub-pixel area and overlapping formation of concentric line of close this sub-pixel area, thereby can omit concentric line and the shading line of gate line adjacent position, owing to having omitted the shading line and having reduced the quantity of concentric line, reduced simultaneously the area of lightproof area, thereby improved the aperture opening ratio of liquid crystal indicator.
Be more than the application's core concept, for the technical scheme that the embodiment of the present invention is provided is clearer, following embodiment is described in detail technique scheme of the present invention:
The transversely arranged dot structure that the embodiment of the present invention provides a kind of bigrid to drive can be applicable to the liquid crystal indicator of IPS, FFS or TN type of drive, this dot structure schematic diagram as shown in Figure 2, this dot structure comprises:
along two adjacent main pixel regions of first direction, i.e. the first main pixel region Z1 and the second main pixel region Z2, two main pixel regions are a pixel cell, wherein, each main pixel region comprises respectively the first sub-pixel area that is arranged in order along second direction, the second sub-pixel area, the 3rd sub-pixel area, namely have 6 sub-pixel area in a pixel cell, be sub-pixel area L11-L13 and L21-L23, wherein, described first direction is substantially vertical with described second direction, preferably, first direction in the present embodiment is the direction that is parallel to gate line, second direction is the direction that is parallel to data line,
Six thin film transistor (TFT) T11-T13 and T21-T23 are arranged at respectively in corresponding sub-pixel area, namely are provided with a thin film transistor (TFT) in each sub-pixel area, and each thin film transistor (TFT) includes source electrode, drain and gate;
Six pixel electrode P11-P13 and P21-P23, each pixel electrode cover on the photic zone of corresponding sub-pixel area, and are electrically connected to the drain electrode of corresponding thin film transistor (TFT) respectively;
Article two, gate line, be first grid polar curve G1 and second gate line G2, be arranged at respectively between adjacent two sub-pixel area in each main pixel region, with respect to the first main pixel region Z1, in the present embodiment, first grid polar curve G1 is arranged between sub-pixel area L11 and L12, and second gate line G2 is arranged between sub-pixel area L12 and L13;
Article three, data line, i.e. tactic the first data line D1, the second data line D2 and the 3rd data line D3, three data lines are arranged at respectively between two main pixel regions of described pixel cell or are arranged at outside two main pixel regions;
Be parallel to a pixel concentric line com1 of described gate line, the pixel electrode part of this pixel concentric line com1 and the first sub-pixel area L11 and L21 is overlapping, forms the memory capacitance of this sub-pixel area;
Wherein, every data line is electrically connected to the source electrode of two thin film transistor (TFT)s respectively, and the thin film transistor (TFT) that different data lines is electrically connected to is different; The grid of two thin film transistor (TFT)s that are electrically connected to from the same data line is electrically connected to different gate line respectively;
The pixel electrode of the second sub-pixel area L12 and L22 is overlapping with the gate line part that is not electrically connected to the grid of the thin film transistor (TFT) of this sub-pixel area, namely, the gate line part of the gate line offside that the grid of the pixel electrode of the second sub-pixel area L12 and L22 and the thin film transistor (TFT) corresponding with it is electrically connected to is overlapping, forms the memory capacitance of this sub-pixel area;
The pixel electrode of the 3rd sub-pixel area L13 and L23 and the pixel concentric line of next pixel cell (as the com2 in Fig. 2) part are overlapping, form the memory capacitance of this sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
According to above description as can be known, the dot structure of the present embodiment, in a pixel cell, a concentric line is only arranged, pixel cell more of the prior art has removed all shading lines and 2 concentric lines, that is to say, the present embodiment has only kept along the concentric line between every 2 pixel cells of data line direction arrangement, namely the memory capacitance of the first sub-pixel area and the 3rd sub-pixel area is by concentric line and pixel electrode part is overlapping forms, and the memory capacitance of the second sub-pixel area is by gate line and pixel electrode part is overlapping forms.
Concrete, the generation type of memory capacitance as shown in Figure 2, the grid of the thin film transistor (TFT) of the first sub-pixel area in two main pixel regions in the described pixel cell in Fig. 2 all is connected with described first grid polar curve, namely the grid of the thin film transistor (TFT) T11 of the first sub-pixel area L11 and L21 and T21 all is connected with first grid polar curve G1, and the memory capacitance of the first sub-pixel area L11 and L21 is respectively by overlapping formation of pixel concentric line com1 part of pixel electrode P11 and P21 and this pixel cell;
The thin film transistor (TFT) T13 of the 3rd sub-pixel area L13 and L23 and the grid of T23 all are connected with second gate line G2, and the memory capacitance of the 3rd sub-pixel area L13 and L23 is respectively by overlapping formation of pixel concentric line com2 part of pixel electrode P13 and P23 and lower pixel cell;
the grid of the thin film transistor (TFT) T12 of the second sub-pixel area L12 of the first main pixel region Z1 is connected with described first grid polar curve G1, the grid of the thin film transistor (TFT) T22 of the second sub-pixel area L22 of the second main pixel region Z2 is connected with described second gate line G2, therefore, the memory capacitance of the second sub-pixel area L12 of described the first main pixel region is by pixel electrode P12 and overlapping formation of described second gate line G2 part of this sub-pixel area, the memory capacitance of the second sub-pixel area L22 of described the second main pixel region is by pixel electrode P22 and overlapping formation of described first grid polar curve G1 part of this sub-pixel area.
it will be appreciated by those skilled in the art that, if with the pixel cell in Fig. 2 in the scan-line direction repeated arrangement, connection in Fig. 3 has just appearred, namely the grid of the thin film transistor (TFT) T12 of the second sub-pixel area L12 of the first main pixel region Z1 is connected with described second gate line G2, the grid of the thin film transistor (TFT) T22 of the second sub-pixel area L22 of the second main pixel region Z2 is connected with described first grid polar curve G1, therefore, the memory capacitance of the second sub-pixel area L12 of described the first main pixel region is by pixel electrode P12 and overlapping formation of described first grid polar curve G1 part of this sub-pixel area, the memory capacitance of the second sub-pixel area L22 of described the second main pixel region is by pixel electrode P22 and overlapping formation of described second gate line G2 part of this sub-pixel area.
That is to say, the grid of the thin film transistor (TFT) of the second main pixel region of the pixel cell in the present embodiment with which gate line is connected, and depends on the range of definition of pixel cell, in the present embodiment, this is not done restriction.
Concrete, take dot structure shown in Figure 2 as example, in conjunction with vertical view and the sectional view of dot structure, its structure is elaborated, Fig. 4 is the vertical view of this dot structure, Fig. 5 is the sectional view in this dot structure A-A ' zone, and Fig. 6 is the sectional view in this dot structure B-B ' zone.
As shown in Figure 4 and Figure 5, A-A ' zone is the overlapping region of pixel electrode and gate line, the second sub-pixel L12 and the 3rd sub-pixel L13 intersection as the first main pixel region Z1, overlapping by pixel electrode P12 and second gate line G2 part, form the memory capacitance of the second sub-pixel L12, perhaps the first sub-pixel L21 of the second main pixel region Z2 and the second sub-pixel L22 intersection, overlapping by pixel electrode P22 and first grid polar curve G1 part, forms the memory capacitance of the second sub-pixel L22.
Concrete, in the sectional view in A-A ' zone, comprise from the bottom to top: the first substrate (not shown), be positioned at the lip-deep gate line 31 of first substrate, be positioned at the lip-deep first medium layer 32 of gate line 31, be positioned at the lip-deep second medium layer 33 of first medium layer 32, be positioned at the lip-deep pixel electrode 34 of second medium layer 33.First substrate in the present embodiment can be glass substrate, and pixel electrode 34 can in manufacture craft, be data line layer between first medium layer 32 and second medium layer 33 for the ITO electrode, does not just have data line in A-A ' zone.
And, A-A ' in the present embodiment is if the zone is positioned at the second sub-pixel L12 and the 3rd sub-pixel L13 intersection of the first main pixel region Z1, gate line 31 is second gate line G2, and pixel electrode 34 is pixel electrode P12, and this moment, Fig. 5 was the left view in A-A ' zone; If A-A ' zone is positioned at the first sub-pixel L21 and the second sub-pixel L22 intersection of the second main pixel region Z2, gate line 31 is first grid polar curve G1, and pixel electrode 34 is pixel electrode 22, and this moment, Fig. 5 was the right view in A-A ' zone.
As shown in Figure 6, B-B ' zone is the overlapping region of pixel electrode and pixel concentric line, as the 3rd sub-pixel L13 of the first main pixel region Z1 and the pixel concentric line com2 overlapping region of next pixel cell.
Concrete, in the sectional view in B-B ' zone, comprise from the bottom to top: the first substrate (not shown), be positioned at the lip-deep pixel concentric line 35 of first substrate, be positioned at the lip-deep first medium layer 32 of pixel concentric line 35, be positioned at the lip-deep second medium layer 33 of first medium layer 32, be positioned at the lip-deep pixel electrode 34 of second medium layer 33.Pixel concentric line 35 in the present embodiment is positioned on same metal level with the gate line 31 in Fig. 5, and both forms in same photoetching process.Due to pixel concentric line 35 can with the memory capacitance of the corresponding sub-pixel area of the overlapping formation of the pixel electrode that is positioned at its both sides, so the both sides of pixel concentric line 35 tops all has pixel electrode area.
In theory, in the present embodiment, the arrangement mode of three data lines also is not specifically limited, generally, the arrangement mode of data line can be divided into three kinds of situations, concrete, the first arrangement mode as shown in Figures 2 and 3, the first main pixel region Z1 is between described the first data line D1 and the second data line D2, the described second main pixel region Z2 is between described the second data line D2 and the 3rd data line D3;
In the second arrangement mode, the described second main pixel region Z2 is between the second data line D2 and the 3rd data line D3, the first main pixel region Z1 is positioned at the outside of the first data line D1, and the outside of described the first data line D1 is the first data line D1 side of the second data line D2 dorsad; Certainly, in the arrangement mode in Fig. 8 can be also the first main pixel region Z1 between the first data line D1 and the second data line D2, the second main pixel region Z2 is positioned at the outside of the 3rd data line D3.
In the third arrangement mode, the first main pixel region Z1 is positioned at the outside of the first data line D1, and the second main pixel region Z2 is positioned at the outside of the 3rd data line D3, and the outside of described the 3rd data line D3 is the 3rd data line D3 side of the second data line D2 dorsad.
In the actual fabrication process, if realize the second and the third data line arrangement mode, need to be across the problem of data line connection owing to existing, therefore need to form again one the 3rd dielectric layer on the data line layer surface, and form one the 3rd metal level on this dielectric layer surface, by the mode of punching on the 3rd dielectric layer, the connection by the 3rd metal level realizes that the thin film transistor (TFT) source electrode is connected with respective data lines and connects across data line, and this metal level can be positioned at same metal level with pixel electrode.In order to simplify manufacture craft, preferably adopt the first data line arrangement mode in the present embodiment.
in addition, need to prove, for the liquid crystal indicator that adopts the TN type of drive, in prior art, the memory capacitance of each sub-pixel area is formed with concentric line is overlapping accordingly by the pixel electrode of sub-pixel area, as shown in Figure 7, dot structure figure for the liquid crystal indicator of available technology adopting TN type of drive, similar in the generation type of pixel cell and the present embodiment in Fig. 7, a pixel cell comprises 2 main pixel regions, each main pixel region comprises 3 sub-pixel area L1, L2 and L3, each pixel cell comprises 3 concentric line com1, com2 and com3, article 2, gate lines G 1 and G2, wherein a side of 2 gate lines is respectively followed a concentric line, has certain interval W between gate line and its concentric line of following, the width of gap W and concentric line is approximate, covered by black matrix" district BM between the W of gap, and because gate line and concentric line are light tight setting, thereby cause the reduction of aperture opening ratio.
In the present embodiment, the dot structure figure of the liquid crystal indicator of employing TN type of drive as shown in Figure 8, owing to having omitted 2 concentric lines in a pixel cell, compare with Fig. 7, the concentric line com2 and the com3 that follow 2 gate lines have namely been removed, the light tight zone of having reduced concentric line com2 and com3 on the one hand, also reduced simultaneously the black matrix area at W place, gap, thereby liquid crystal indicator more of the prior art has improved aperture opening ratio.
In addition, in the present embodiment, for the liquid crystal indicator that adopts the TN type of drive, described sub-pixel area is rectangular region, and the long limit of described rectangular region is parallel with gate line.
And for the liquid crystal indicator that adopts IPS or FFS type of drive, described dot structure can adopt single domain pattern, two domain mode or multidomain pattern.When described dot structure adopted the single domain pattern, described sub-pixel area was rectangular region, and the long limit of described rectangular region is parallel with gate line; When described dot structure adopted two domain mode, described sub-pixel area was the herringbone zone, and described pixel electrode is the herringbone electrode, and the multidomain Pattern Class of the pixel electrode shape during the multidomain pattern and conventional liquid crystal indicator seemingly repeats no more here.
It will be appreciated by those skilled in the art that, for the liquid crystal indicator that adopts IPS or FFS type of drive, when adopting the dot structure of single domain pattern, direction of an electric field is single, liquid crystal arrangement mode in pixel region is consistent, GTG can occur in some specific angle and reverse phenomenon; And the dot structure of the two domain modes of employing or multidomain pattern, direction of an electric field and liquid crystal arrangement mode have symmetrical structure, can improve the GTG of liquid crystal display under with great visual angle to reverse phenomenon, thereby improve the visual angle.The present embodiment is take 2 main pixel regions as a recurring unit, each main pixel region comprises three sub-pixel area, preferred a kind of red sub-pixel district R, green time pixel region G, blue sub-pixels district B of being combined as, namely a minimum recurring unit comprises pixel region 6 times.a minimum recurring unit comprises two gate lines, three data lines, six thin film transistor (TFT)s, and every data line drives pixel region two times, two times pixel region is controlled by different gate lines respectively, adopt this dot structure, it is the screen of m * n for resolution, its gate line that needs is the 2m bar, its data line that needs is the 3n/2 bar, like this, every gate line driving time shorten to the horizontal use of perpendicular screen that single grid drives the pixel horizontal mode 1/2nd, TFT common when resolution is higher also can reach the driving requirement, be suitable for widespread use, and, the transversely arranged dot structure that the bigrid that the embodiment of the present invention provides drives is more suitable for showing in 3D.
Further, the present embodiment is in a pixel cell, reduced by two concentric lines than prior art, namely only keep along the concentric line between every 2 pixel cells of data line direction arrangement, in the embodiment of the present invention, the memory capacitance of a certain sub-pixel area is mainly by the pixel electrode of this sub-pixel area and overlapping formation of gate line of non-this sub-pixel area, thereby can omit the concentric line of gate line adjacent position, owing to having omitted the shading line and having reduced the quantity of concentric line, thereby improved the aperture opening ratio of liquid crystal indicator.
The transversely arranged dot structure that the above-mentioned bigrid that provides based on an embodiment in the present invention drives, another embodiment of the present invention also provides a kind of liquid crystal indicator, comprise: first substrate, second substrate and the liquid crystal layer between first substrate and second substrate, wherein, comprise on described first substrate:
The transversely arranged dot structure that above-mentioned bigrid drives, above-mentioned pixel cell is the array repeated arrangement;
An edge concentric line that is parallel to described gate line, be positioned at one side that described first substrate does not arrange the pixel concentric line, overlapping with pixel electrode and this edge concentric line part of this edge concentric line next-door neighbour's the 3rd sub-pixel area, form the memory capacitance of the 3rd sub-pixel area.
In the present embodiment, first substrate can be the TFT substrate, and second substrate can be colored filter (Color Filter, CF) substrate.
need to prove, difference according to the type of drive that adopts, the structure of this liquid crystal indicator is also different, if the liquid crystal indicator of TN type of drive, second substrate also has a common electrode layer on the one side of liquid crystal layer, this common electrode layer and be positioned between pixel electrode on first substrate and produce electric field drives turning to of liquid crystal, if the liquid crystal indicator of IPS type of drive drives turning to of liquid crystal by concentric line and the electric field between pixel electrode that is positioned on first substrate, this concentric line is generally lighttight metal wire, if the liquid crystal indicator of FFS type of drive, except concentric line, also be provided with public electrode on first substrate, drive turning to of liquid crystal by the electric field between public electrode and pixel electrode, this public electrode generally adopts the ITO material of printing opacity to make, and this public electrode can be positioned on same conductive layer with pixel electrode, also can be positioned on different conductive layers, if both on same conductive layer, both alternately, if both be positioned on different conductive layers, the position of the conductive layer at public electrode and pixel electrode place can exchange, in this case, public electrode can be structure as a whole or be and pixel electrode strip electrode alternately.
Based on dot structure and the liquid crystal indicator of above embodiment, another embodiment of the present invention provides the method for making of above-mentioned liquid crystal indicator, specifically can be referring to Fig. 4-Fig. 6, and the method comprises the following steps:
Step 1: the first substrate (not shown) is provided, and this first substrate can be glass substrate;
step 2: form a plurality of gate lines 31 that are parallel to each other on described first substrate, a plurality of pixel concentric lines 35 and an edge concentric line (not shown), described a plurality of gate line, a plurality of pixel concentric lines and an edge concentric line form in same lithography step, and be formed on same conductive layer, it is the first metal layer, wherein, described edge concentric line is positioned at one side that described first substrate does not arrange the pixel concentric line, overlapping with pixel electrode and this edge concentric line part of this edge concentric line next-door neighbour's the 3rd sub-pixel area, form the memory capacitance of the 3rd sub-pixel area,
Step 3: form first medium layer 32 on described a plurality of gate lines, a plurality of pixel concentric line and concentric line surface, an edge;
Step 4: form semiconductor layer on described first medium layer surface, a plurality of data lines that are parallel to each other on described semiconductor layer surface, data line is formed on the second metal level, and described semiconductor layer comprises the structures such as silicon island, similar with conventional liquid crystal indicator, be not described in detail here;
Step 5: form second medium layer 33 on described data line surface, form the through hole (not shown) at the second medium layer region that is positioned on the drain surface of thin film transistor (TFT);
Step 6: form data line and pixel electrode 34 above described second medium layer 33, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole, and described pixel electrode 34 is preferably the ITO electrode;
Wherein, in described pixel cell, the pixel concentric line part of the pixel electrode of the first sub-pixel area and this pixel cell is overlapping, forms the memory capacitance of the first sub-pixel area;
The gate line of the gate line offside that the grid of the pixel electrode of described the second sub-pixel area and the thin film transistor (TFT) corresponding with it is electrically connected to, namely overlapping with the gate line part that is not electrically connected to the grid of the thin film transistor (TFT) of this sub-pixel area, form the memory capacitance of the second sub-pixel area;
The pixel concentric line part of the pixel electrode of described the 3rd sub-pixel area and next pixel cell is overlapping, form the memory capacitance of the 3rd sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
After forming pixel electrode, inject liquid crystal between first substrate and second substrate, form liquid crystal layer, carry out afterwards the connection of external control circuit, complete the making of liquid crystal indicator, the manufacture craft of the liquid crystal indicator of the present embodiment is identical with common process, and difference only is the distribution of concentric line, gate line and pixel electrode, and concrete manufacture craft is repeated no more here.
For the liquid crystal indicator of different driving pattern, its method for making is also different, and for the liquid crystal indicator of IPS and TN type of drive, the manufacturing process of the lip-deep said structure of array base palte is similar, the different just shapes of pixel electrode.
For adopting FFS type of drive liquid crystal indicator, need to increase by a common electrode layer on the basis of IPS structure, its dot structure figure as shown in Figure 9, for common electrode layer and the pixel electrode layer liquid crystal indicator on same conductive layer not, the ITO electrode that described public electrode can be structure as a whole or with described pixel electrode strip electrode alternately.And different from above description on method for making is that the process that forms pixel electrode above described second medium layer is specially:
Form the lamination that is formed by pixel electrode (as shown in Pixel-ITO in figure), the 3rd dielectric layer and public electrode (as shown in COM-ITO in figure) on described second medium layer surface;
Wherein, if described pixel electrode between described the 3rd dielectric layer and second medium layer, described public electrode is positioned on described the 3rd dielectric layer surface, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole;
If described public electrode is between described the 3rd dielectric layer and second medium layer, described pixel electrode is positioned on described the 3rd dielectric layer surface, also comprise after forming described the 3rd dielectric layer, at the second medium layer and the 3rd dielectric layer zone formation through hole that are positioned on the drain surface of thin film transistor (TFT).
In other embodiments, pixel electrode layer also can and data line layer between directly conducting, perhaps both be produced on same conductive layer, and be electrically connected between data line layer and common electrode layer, concrete connected mode can be peripheral by wire connection data line layer and common electrode layer in the viewing area.
More than that pixel electrode layer and common electrode layer are positioned at structure on different conductive layers and the introduction of method, for the liquid crystal indicator that adopts the IPS type of drive, in the time of on both being positioned at same conductive layer, the process that forms pixel electrode above described second medium layer is specially:
Form pixel electrode and public electrode on described second medium layer surface, described pixel electrode and public electrode are positioned on same conductive layer and alternately, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole, and described pixel electrode and public electrode can be the ITO electrode of strip.
In this instructions, various piece adopts the mode of going forward one by one to describe, and what each part stressed is and the difference of other parts that between various piece, identical similar part is mutually referring to getting final product.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from the spirit or scope of the present invention, realization in other embodiments.Therefore, the present invention will can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (11)
1. the transversely arranged dot structure that bigrid drives, is characterized in that, comprising:
By along two adjacent pixel cells that main pixel region forms of first direction, wherein, each main pixel region comprises respectively the first sub-pixel area, the second sub-pixel area, the 3rd sub-pixel area that is arranged in order along second direction, and described first direction is substantially vertical with described second direction;
Six thin film transistor (TFT)s are arranged at respectively in corresponding sub-pixel area;
The pixel electrode that is arranged in each sub-pixel area and is electrically connected to the drain electrode of corresponding thin film transistor (TFT), described pixel electrode covers on the photic zone of sub-pixel area;
Be parallel to described first direction, and be arranged at respectively two gate lines between interior adjacent two sub-pixel area of each main pixel region;
Be parallel to described second direction, and be arranged at respectively between two main pixel regions of described pixel cell or be arranged at three data lines outside two main pixel regions;
Be parallel to a pixel concentric line of described gate line, the pixel electrode part of this pixel concentric line and the first sub-pixel area is overlapping, forms the memory capacitance of this sub-pixel area;
Wherein, every data line is electrically connected to the source electrode of two thin film transistor (TFT)s respectively, and the thin film transistor (TFT) that different data lines is electrically connected to is different; The grid of two thin film transistor (TFT)s that are electrically connected to from the same data line is electrically connected to different gate line respectively;
The gate line part of the gate line offside that the grid of the pixel electrode of the second sub-pixel area and the thin film transistor (TFT) corresponding with it is electrically connected to is overlapping, forms the memory capacitance of this sub-pixel area;
The pixel concentric line part of the pixel electrode of the 3rd sub-pixel area and next pixel cell is overlapping, forms the memory capacitance of this sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
2. the transversely arranged dot structure of bigrid driving according to claim 1, is characterized in that, for the liquid crystal indicator that adopts the TN type of drive, described sub-pixel area is rectangular region, and the long limit of described rectangular region is parallel with gate line.
3. the transversely arranged dot structure of bigrid driving according to claim 1, is characterized in that, for the liquid crystal indicator that adopts IPS or FFS type of drive, described dot structure adopts single domain pattern, two domain mode or multidomain pattern.
4. the transversely arranged dot structure of bigrid driving according to claim 3, is characterized in that, when described dot structure adopted the single domain pattern, described sub-pixel area was rectangular region, and the long limit of described rectangular region is parallel with gate line;
When described dot structure adopted two domain mode, described sub-pixel area was the herringbone zone, and described pixel electrode is the herringbone electrode.
5. the transversely arranged dot structure of bigrid driving according to claim 1, is characterized in that, two gate lines comprise: first grid polar curve and second gate line; Described two main pixel regions comprise: the first main pixel region and the second main pixel region;
The grid of the thin film transistor (TFT) of the first sub-pixel area in two main pixel regions in described pixel cell all is connected with described first grid polar curve;
The grid of the thin film transistor (TFT) of the second sub-pixel area of described the first main pixel region is connected with described first grid polar curve, the grid of the thin film transistor (TFT) of the second sub-pixel area of described the second main pixel region is connected with described second gate line, the pixel electrode of the second sub-pixel area of described the first main pixel region and described second gate line part are overlapping, form the memory capacitance of this sub-pixel area, the pixel electrode of the second sub-pixel area of described the second main pixel region and described first grid polar curve part are overlapping, form the memory capacitance of this sub-pixel area;
The grid of the thin film transistor (TFT) of the 3rd sub-pixel area in two main pixel regions in described pixel cell all is connected with described second gate line.
6. the transversely arranged dot structure of bigrid driving according to claim 5, is characterized in that, described three data lines comprise: tactic the first data line, the second data line and the 3rd data line;
The described first main pixel region is between described the first data line and the second data line, and the described second main pixel region is between described the second data line and the 3rd data line.
7. a liquid crystal indicator, is characterized in that, comprising:
First substrate, second substrate and the liquid crystal layer between first substrate and second substrate;
Wherein, comprise on described first substrate:
The transversely arranged dot structure that the described bigrid of claim 1-6 any one drives, described pixel cell is the array repeated arrangement;
An edge concentric line that is parallel to described gate line, be positioned at one side that described first substrate does not arrange the pixel concentric line, overlapping with pixel electrode and this edge concentric line part of this edge concentric line next-door neighbour's the 3rd sub-pixel area, form the memory capacitance of the 3rd sub-pixel area.
8. the method for making of a liquid crystal indicator as claimed in claim 7, is characterized in that, comprising:
First substrate is provided;
Form a plurality of gate lines, a plurality of pixel concentric line and edge concentric line that is parallel to each other on described first substrate, described a plurality of gate line, a plurality of pixel concentric line and an edge concentric line form in same lithography step, and be formed on same conductive layer, wherein, described edge concentric line is positioned at one side that described first substrate does not arrange the pixel concentric line, overlapping with pixel electrode and this edge concentric line part of this edge concentric line next-door neighbour's the 3rd sub-pixel area, form the memory capacitance of the 3rd sub-pixel area;
Form the first medium layer on described a plurality of gate lines, a plurality of pixel concentric line and concentric line surface, an edge;
Form semiconductor layer, a plurality of data lines that are parallel to each other on described semiconductor layer surface on described first medium layer surface;
Form the second medium layer on described data line surface, form through hole at the second medium layer region that is positioned on the drain surface of thin film transistor (TFT);
Form pixel electrode above described second medium layer, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole;
Wherein, in described pixel cell, the pixel concentric line part of the pixel electrode of the first sub-pixel area and this pixel cell is overlapping, forms the memory capacitance of the first sub-pixel area;
The gate line part of the gate line offside that the grid of the pixel electrode of described the second sub-pixel area and the thin film transistor (TFT) corresponding with it is electrically connected to is overlapping, forms the memory capacitance of the second sub-pixel area;
The pixel concentric line part of the pixel electrode of described the 3rd sub-pixel area and next pixel cell is overlapping, form the memory capacitance of the 3rd sub-pixel area, described next pixel cell be on second direction with the 3rd sub-pixel area next-door neighbour's of this pixel cell pixel cell.
9. the method for making of liquid crystal indicator according to claim 8, is characterized in that, for adopting FFS type of drive liquid crystal indicator, the process that forms pixel electrode above described second medium layer is specially:
Form the lamination that is formed by pixel electrode, the 3rd dielectric layer and public electrode on described second medium layer surface;
Wherein, if described pixel electrode between described the 3rd dielectric layer and second medium layer, described public electrode is positioned on described the 3rd dielectric layer surface, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole;
If described public electrode is between described the 3rd dielectric layer and second medium layer, described pixel electrode is positioned on described the 3rd dielectric layer surface, also comprise after forming described the 3rd dielectric layer, at the second medium layer and the 3rd dielectric layer zone formation through hole that are positioned on the drain surface of thin film transistor (TFT).
10. the method for making of liquid crystal indicator according to claim 9, is characterized in that, the ITO electrode that described public electrode is structure as a whole or with described pixel electrode strip electrode alternately.
11. the method for making of liquid crystal indicator according to claim 8 is characterized in that, for adopting IPS type of drive liquid crystal indicator, the process that forms pixel electrode above described second medium layer is specially:
Form pixel electrode and public electrode on described second medium layer surface, described pixel electrode and public electrode are positioned on same conductive layer and alternately, described pixel electrode is electrically connected to the drain electrode of thin film transistor (TFT) by described through hole.
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