CN103165560B - Substrate and semiconductor structure using it - Google Patents

Abstract

A substrate and a semiconductor structure using the same are provided. The substrate comprises a base material, a plating line, m routing lines and a concave part. The substrate has a packaging unit area. The plated line is disposed adjacent to an edge of the package unit region. m wires are formed in the packaging unit areas, n wires of the m wires extend to the electroplating wire, wherein m is a positive integer equal to or larger than 2, and n is selected from one of 1 to (m-1). The concave part cuts off the m wires to electrically isolate the wires.

Description

Substrate and semiconductor structure using it

technical field

The present invention relates to a substrate and a semiconductor structure using the same, and more particularly to a substrate in which not all traces are connected to plating lines and a semiconductor structure using the same.

Background technique

Traditional strip substrates are usually electroplated with a pad layer on the traces before singulation, and then cut. However, after dicing, all traces have a line segment remaining as an electroplating connection, and these remaining line segments lead to increased line signal loss.

Contents of the invention

The invention relates to a substrate and a semiconductor structure using the same, which can improve the problem of circuit signal loss.

According to an embodiment of the present invention, a substrate and a semiconductor structure using the same are provided. The substrate includes a base material, an electroplating line, m traces and a recess. The substrate has an encapsulation unit area. The plating line is disposed adjacent to the edge of the packaged cell area. M lines are formed in these packaging unit areas, and n lines in the m lines extend to the plating line, wherein m is a positive integer equal to or greater than 2, and n is selected from 1 to (m-1 ) one of the values. The recessed portion electrically isolates the m wires.

According to another embodiment of the present invention, a substrate and a semiconductor structure using the same are provided. The semiconductor structure includes a substrate, a chip and an electrical connector. The substrate includes a base material, m traces and a recess. The substrate has an encapsulation unit area. m lines are formed in these package unit areas, and n lines among the m lines extend to the plating line, wherein m is a positive integer equal to or greater than 2, and n is selected from 1 to (m-1) one of the values of . The recessed portion electrically isolates the m wires. The chip is arranged on the substrate. The electrical connector electrically connects the chip and the m wires.

In order to make the above content of the present invention more obvious and easy to understand, the following specific examples are given in conjunction with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1A illustrates a top view of a semiconductor structure according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view of FIG. 1A along the direction 1B-1B'.

FIG. 1C is a cross-sectional view of FIG. 1A along the direction 1C-1C'.

FIG. 1D is a cross-sectional view of FIG. 1A along the direction 1D-1D'.

FIG. 2 illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention.

FIG. 3 illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention.

FIG. 4 illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention.

FIG. 5A illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention.

Fig. 5B is a cross-sectional view along the direction 5B-5B' in Fig. 5A.

FIG. 6 illustrates a top view of a semiconductor structure according to another embodiment of the present invention.

FIG. 7 is a signal test diagram of the semiconductor structure of FIG. 1 .

8A to 8E are diagrams illustrating a fabrication process of a semiconductor structure according to an embodiment of the present invention.

Description of main component symbols:

100, 200, 300, 400, 500: Semiconductor structures

110: Substrate

110u, 111u, 112u: upper surface

111: Substrate

111b: lower surface

111s: edge side

112: Routing group

112e: trace extension

112p: pad part

112t, 112t’: wiring

112v, 112v’: via hole

1121: Line segment

113: Depressed part

114: connecting line

115: Plating line

120: chip

120R: chip setting area

120u: active surface

130: electrical connector

140: Encapsulation

140R: package unit area

150: protective layer

150a: opening

C1, C2: curve

detailed description

Please refer to FIG. 1A , which illustrates a top view of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure 100 includes a substrate 110 , a chip 120 , a plurality of electrical connectors 130 , a package 140 ( FIG. 1D ), and a protective layer 150 .

The substrate 110 includes a base material 111 ( FIG. 1B ), several trace groups 112 and several recesses 113 . The material of the substrate 111 can be selected from organic materials, ceramic materials, silicon substrates or metals. In addition, the substrate 111 can be a single-layer or multi-layer circuit substrate.

The substrate 111 has an edge side 111s. Each trace group 112 is formed on the substrate 111 and includes m traces 112t. In this example, four wire groups 112 are taken as an example, which are respectively adjacent to four sides of the chip 120 ; however, several wire groups 112 may also be adjacent to a single side of the chip 120 . In addition, the number of wire groups 112 can also be less than or more than four.

In each wire group 112, the number m of wires 112t is a positive integer greater than 2, and its upper limit depends on the actual wire layout, which is not limited by the embodiment of the present invention. N of the m traces 112t extend to the corresponding edge side 111s, wherein n is selected from a value from 1 to (m−1). That is to say, at least one but not all of the traces 112t need to extend to the edge side 111s of the substrate 111 , thereby reducing signal loss. When the number of traces 112t connected to the edge side 111s is less, the signal loss is less. In this example, the trace 112t' extends to the edge side 111s as an example. In addition, the numbers of the wires 112t in each wire group 112 can be different or completely the same.

Each trace group 112 includes a plurality of via holes 112v extending between the upper surface 111u ( FIG. 1B ) and the lower surface 111b ( FIG. 1B ) of the substrate 111 to electrically connect multiple layers of the substrate 111 The circuit layer or electrically connects the upper surface 111u and the lower surface 111b of the substrate 111 . The distances between at least two of the via holes 112v and the edge side 111s may be the same or different, and their positions may be determined by the circuit layout, which is not limited by the embodiment of the present invention. The wire 112t' is connected to the via hole 112v', and the signal can be transmitted between the chip 120 and the via hole 112v' through the wire 112t'. The trace segment 1121 between the via hole 112v' and the edge side 111s is a plating circuit, which has no substantial circuit function. In this example, among all the vias 112v of the wiring group 112 corresponding to the via 112v', the via hole closest to the edge side 111s is the via hole closest to the edge side 111s. The length of 1121 can be shortened to reduce signal loss. When the length of the trace segment 1121 is shorter, the signal loss is less.

In each trace group 112, a single recess 113 passes through all the traces 112t to electrically isolate these traces 112t. For example, each of the m traces 112t includes a pad portion 112p and a trace extension portion 112e, each trace extension portion 112e extends from the corresponding pad portion 112p to the concave portion 113 and communicates with other trace extension portions 112e through the depression Section 113 is electrically isolated. In addition, the concave portion 113 can be formed by laser, knife or etching.

Please refer to FIG. 1B (the package body 140 is not shown), which shows a cross-sectional view of FIG. 1A along the direction 1B-1B'. The concave portion 113 extends from the upper surface 112u of the wire extending portion 112e through the entire wire extending portion 112e and a partial thickness of the substrate 111 to completely cut off the wire extending portion 112e. The passivation layer 150 (such as a solder resist layer) covers the traces 112t and has at least one opening 150a. In this example, the area of a single opening 150 a corresponds to a single wiring group 112 , but multiple openings 150 a may also correspond to a single wiring group 112 . The pad portion 112p and the wire extension portion 112e of each of the m lines 112t are exposed from the opening 150a. In this way, during the forming process of forming the recessed portion 113, the recessed portion 113 can pass through the opening 150a to cut off the exposed portion. The trace extension part 112e. Since the pad portion 112p is exposed from the opening 150a, the electrical connector 130 ( FIG. 1D ) can be connected to the pad portion 112p through the opening 150a.

Please refer to FIG. 1C (the package body 140 is not shown), which shows a cross-sectional view of FIG. 1A along the direction 1C-1C'. The area of the opening 150 a of the protection layer 150 is larger than the distribution range of the m traces 112 t, and the m traces 112 t are exposed, so that the recess 113 can pass through and cut off all the exposed trace extensions 112 e.

Please refer to FIG. 1D, which shows a cross-sectional view of FIG. 1A along the direction 1D-1D'. The concave portion 113 is located between the chip 120 and the edge side 111s of the substrate 110 . The chip 120 is disposed on the substrate 110 with its active surface 120u facing upwards, and is electrically connected to the pad portion 112p of the trace 112t through the electrical connector 130 . In this example, the electrical connector 130 is wire-bonded. In another example, the chip 120 may be a flip chip, which is disposed on the upper surface 110u of the substrate 110 with its active surface 120u facing downward and is electrically connected to the pad of the trace 112t through at least one bump. Section 112p.

In this example, the wiring group 112 ( FIG. 1A ) is formed on the upper surface 111u of the substrate 111 , but in another example, it can also be formed on the upper surface 111u and the lower surface 111b at the same time.

The package body 140 is formed on the upper surface 110u of the substrate 110 and covers the chip 120 and the electrical connector 130 . The package body 140 may include Novolac-based resin, epoxy-based resin, silicone-based resin or other suitable encapsulating agents. The package body 140 may also include a suitable filler, such as powdered silicon dioxide. The package body 140 can be formed by several packaging techniques, such as compression molding, injection molding or transfer molding.

Please refer to FIG. 2 , which shows a partial top view of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 200 includes a substrate 110 , a chip 120 , a plurality of electrical connectors 130 , a package 140 (not shown) and a protection layer 150 . The substrate 110 includes a base material 111 (not shown in FIG. 2 ), several trace groups 112 and a recess 113 . In this example, at least two wiring groups 112 are exposed through the opening 150 a of the passivation layer. In each trace group 112 , the number m of traces 112t is greater than 2, and n traces 112t of them extend to the corresponding edge side 111s, and n is selected from a value from 1 to (m−1). The rest of the features of each routing group 112 have been described above, and will not be repeated here. In addition, in each trace group 112 , the concave portion 113 cuts off all the traces 112t to electrically isolate these traces 112t.

Please refer to FIG. 3 , which illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 300 includes a substrate 110 , several electrical connectors 130 of a chip 120 , a package 140 (not shown) and a protection layer 150 . The substrate 110 includes a base material 111 (not shown in FIG. 3 ), at least one wire group 112 , a recessed portion 113 and a connection wire 114 . The trace group 112 includes several traces 112t, and the trace extension 112e connects the connecting wire 114 and the pad portion 112p, wherein the concave portion 113 passes through the trace extending portion 112e to electrically isolate the pad portion 112p and the connecting wire 114 . According to this principle, the concave portion 113 cuts off all the wires 112t to electrically isolate these wires 112t.

Please refer to FIG. 4 , which illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention. Different from the structure in FIG. 3 , the connecting wire 114 in this example can be covered by a protective layer 150 .

Please refer to FIG. 5A , which illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 400 includes a substrate 110 , a chip 120 , a plurality of electrical connectors 130 , a package 140 (not shown) and a protection layer 150 . The substrate 110 includes a base material 111 (shown in FIG. 5B ), at least one wire group 112 , a concave portion 113 and a plurality of connecting wires 114 , and each connecting wire 114 extends from the corresponding wire group 112 to the concave portion 113 .

Please refer to FIG. 5B, which shows a cross-sectional view along the direction 5B-5B' in FIG. 5A. The two connection lines 114 extend oppositely from the two adjacent pads 112p to the recessed portion 113 therebetween, so as to electrically isolate the two adjacent pads 112p via the recessed portion 113 therebetween.

Please refer to FIG. 6 , which illustrates a partial top view of a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 500 includes a substrate 110 , a chip 120 , a plurality of electrical connectors 130 , a package 140 (not shown) and a protection layer 150 . The substrate 110 includes a base material 111 , a single wire group 112 and a single recess 113 , wherein the wire group 112 includes several wires 112 surrounding the chip 120 . The protective layer 150 has a single opening 150a (such as the ring-shaped area of the thick solid line), which surrounds the chip 120 and exposes all the wires 112, so that in the process of forming a single recess 113, the recess 113 can be cut through the opening 150a. All the wires 112 are electrically isolated from each other. In this example, the annular concave portion 113 can be formed by single cutting (such as single-feed) or divided cutting (such as multiple-feed). Although the recessed portion 113 in this example is described as a closed ring, in another example, the recessed portion 113 can also be an open annular recessed portion formed by several separated sub-recessed portions. However, as long as the recessed portion 113 can cut off the electrical connections of all the wires 112t, the embodiment of the present invention does not limit the design of the recessed portion 113 . In addition, in this example, there may be only one trace 112t' extending to the edge side 111s, which greatly reduces the signal loss.

Please refer to FIG. 7 , which shows a signal test diagram of the semiconductor structure in FIG. 1 . Curve C1 represents the signal loss curve of the trace 112t of the semiconductor structure 100 of this example, and curve C2 represents the signal loss curve of the conventional semiconductor structure where all the traces extend to the edge side 111s. Compared with the curve C2 , since not all the wires 112t extend to the edge side 111s in the semiconductor structure 100 of this example, the signal loss (curve C1 ) is significantly reduced.

Please refer to FIGS. 8A to 8E , which illustrate a manufacturing process diagram of a semiconductor structure according to an embodiment of the present invention.

As shown in FIG. 8A, a substrate 110' is provided. The substrate 110' is, for example, a long substrate, which includes a base material 111, at least one wire group 112, at least one connecting wire 114, and at least one plating wire 115.

The substrate 111 has at least one packaging unit region 140R. In the subsequent singulation process, at least one semiconductor structure 100 can be cut along the edge of the packaging unit region 140R. In addition, the base material 111 has at least one chip placement region 120R, and the subsequent chips 120 can be arranged corresponding to the chip placement region 120R.

In each trace group 112 , the number m of traces 112t is greater than 2, and n traces 112t of them extend to the corresponding edge side 111s, and n is selected from a value from 1 to (m−1). That is, at least one but not all of the traces 112t can extend to the edge side 111s of the substrate 111 to be directly electrically connected to the plating line 115 . In this example, the wiring 112t' is directly electrically connected to the plating line 115 as an example. In addition, the traces 112t, the connecting wires 114 and the plating wires 115 can be formed together in the same process, but this is not intended to limit the embodiment of the present invention.

Each connection wire 114 is connected to all the wires 112 t in the corresponding wire group 112 , so that the wires 112 t not connected to the electroplating wire 115 can be indirectly electrically connected to the electroplating wire 115 via the connecting wire 114 .

The plating line 115 is disposed adjacent to the edge of the packaging unit area 140R, and extends between two adjacent packaging unit areas 140R. The plurality of electroplating lines 115 are electrically connected to each other and to an electroplating electrode (not shown). In this way, in the subsequent electroplating process, all the traces 112t directly or indirectly connected to the electroplating lines 115 can be electrically connected to the electroplating electrodes through the electroplating lines 115, and then a pad layer (not shown) can be electroplated on on the pad portion 112p of the trace 112t. The pad layer facilitates the connection of the subsequently formed electrical connector 130 to the pad portion 112p.

As shown in FIG. 8B, after the process of electroplating the pad layer is completed, for example, laser, knife, etching or other suitable material removal techniques can be used to form the recess 113 and pass through the connection line 114, so as to remove the entire connection line 114, And cut off the electrical connections of all the m wires 112t. In this example, the concave portion 113 can be formed by cutting once; however, it can also be formed by cutting in stages.

Then, the recessed portion 113 may be cleaned using, for example, deionized water to remove impurities generated during the cutting process.

As shown in FIG. 8C, at least one chip 120 can be disposed on the upper surface 110u of the substrate 110 by using, for example, surface mount technology (Surface Mounted Technology, SMT), wherein at least one chip 120 is disposed in the corresponding chip placement area 120R. .

In FIG. 8C , wire-bonding technology can be used to form at least one electrical connection 130 , such as a bonding wire, connecting the active surface 120u of the chip 120 and the pad portion 112p of the wiring 112t of the substrate 110 .

As shown in FIG. 8D , for example, compression molding, injection molding or transfer molding can be used to form the package body 140 to cover the chip 120 .

As shown in FIG. 8E , a singulation step is performed to form at least one semiconductor structure 100 . For example, a knife or a laser may be used to form at least one dicing line P along the edge of the package unit region 140R (FIG. 8C) through the package body 140 and the substrate 110 to form at least one semiconductor structure 100 as shown in FIG. 1D.

The manufacturing methods of the other semiconductor structures 200 , 300 , 400 and 500 are similar to the manufacturing method of the semiconductor structure 100 , and will not be repeated here.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (11)

1. a substrate, it is characterised in that including:

One base material, has an encapsulation unit district；

One plating line, the edge in this encapsulation unit district neighbouring is arranged；

M bar cabling, is formed in this encapsulation unit district, and the n bar cabling in this m bar cabling extends to this plating Line, wherein m is the positive integer equal to or more than 2, and n is selected from a wherein numerical value of 1 to (m-1)；And

One depressed part, electrically isolates this m bar cabling,

Wherein this m bar cabling respectively includes a connection pad portion and a cabling extension, and this substrate further includes a connecting line, This cabling extension connects this connecting line and this connection pad portion, and this depressed part passes through this cabling extension to electrically isolate This connection pad portion and this connecting line.

2. substrate as claimed in claim 1, it is characterised in that this depressed part is through respectively this m bar cabling and is somebody's turn to do The segment thickness of base material.

3. substrate as claimed in claim 1, it is characterised in that further include:

One protective layer, covers this m bar cabling, and has a perforate；

Wherein, this connection pad portion and this depressed part expose from this perforate.

4. substrate as claimed in claim 1, it is characterised in that this cabling extension extends to from this connection pad portion This depressed part.

5. substrate as claimed in claim 1, it is characterised in that this base material has a chip setting area, and this is recessed Sunken portion is positioned between this chip setting area and this plating line.

6. substrate as claimed in claim 1, it is characterised in that further include:

Several cabling groups, respectively this cabling group includes this m bar cabling.

7. substrate as claimed in claim 1, it is characterised in that further include:

Several vias, respectively this m bar cabling is connected to the via of correspondence, wherein extends to being somebody's turn to do of this plating line The via that the one of n bar cabling is connected is the via in those vias near this plating line.

8. a semiconductor structure, it is characterised in that including:

One substrate, including:

One base material, has a side, edge；

M bar cabling, is formed on this base material, and this cabling of n bar in this m bar cabling extends to being somebody's turn to do of correspondence Side, edge, wherein m is the positive integer equal to or more than 2, and n is selected from a wherein numerical value of 1 to (m-1)； And

One depressed part, electrically isolates this m bar cabling；

One chip, is located on this substrate；And

One is electrically connected with part, is electrically connected with this chip and this m bar cabling,

Wherein this m bar cabling respectively includes a connection pad portion and a cabling extension, and this substrate further includes a connecting line, and this is walked Line extension connects this connecting line and this connection pad portion, and this depressed part connects to electrically isolate this through this cabling extension Pad portion and this connecting line.

9. semiconductor structure as claimed in claim 8, it is characterised in that this depressed part is walked through respectively this m bar Line and the segment thickness of this base material.

10. semiconductor structure as claimed in claim 9, it is characterised in that further include:

One protective layer, covers this m bar cabling, and has a perforate；

Wherein, respectively this m bar cabling includes a connection pad portion, and this connection pad portion and this depressed part expose from this perforate.

11. semiconductor structures as claimed in claim 8, it is characterised in that further include:

Several vias, respectively this m bar cabling is connected to the via of correspondence, wherein extends to this side, edge The via that the one of this n bar cabling is connected is the via in those vias near this side, edge.