CN103165484A - Stacked package and manufacturing method thereof - Google Patents
Stacked package and manufacturing method thereof Download PDFInfo
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- CN103165484A CN103165484A CN2013101097141A CN201310109714A CN103165484A CN 103165484 A CN103165484 A CN 103165484A CN 2013101097141 A CN2013101097141 A CN 2013101097141A CN 201310109714 A CN201310109714 A CN 201310109714A CN 103165484 A CN103165484 A CN 103165484A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 173
- 229910000679 solder Inorganic materials 0.000 claims abstract description 100
- 239000000463 material Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 238000004806 packaging method and process Methods 0.000 claims description 20
- 238000005538 encapsulation Methods 0.000 description 49
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 20
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000010949 copper Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- 238000011161 development Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000010030 laminating Methods 0.000 description 6
- 239000006071 cream Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910001092 metal group alloy Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
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- 229910001020 Au alloy Inorganic materials 0.000 description 1
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- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A stacked package and a method of manufacturing the same. The method comprises the following steps. A package structure is formed, and the method comprises the following steps. A first substrate is provided. The first substrate comprises a first surface and a second surface opposite to the first surface. A chip is disposed on the first surface of the first substrate. A plurality of conductive balls are disposed on the first surface of the first substrate. A package body is formed to cover the first surface of the first substrate, the chip and the conductive balls. The package body is provided with a plurality of openings and exposes the conductive balls. A second substrate including a lower surface and an upper surface opposite to the lower surface is formed. A plurality of conductive posts are formed to protrude from a first dielectric surface of a dielectric structure. Forming a plurality of conductive contacts exposed on a second dielectric surface of the dielectric structure. The first dielectric surface is opposite the second dielectric surface. The upper surface of the second substrate includes a second dielectric surface. The conductive posts and the conductive contacts are electrically connected to each other. The conductive balls of the package structure and the conductive posts of the second substrate are physically and electrically connected by a plurality of solder materials.
Description
Technical field
The invention relates to the encapsulation of a kind of stacking type and manufacture method thereof, particularly relevant for encapsulating and manufacture method via solder material physical connection and the conducting sphere that the is electrically connected encapsulating structure stacking type with the conductive pole of second substrate.
Background technology
Electronic product becomes and becomes increasingly complex, and for example requires at least the part of electronic product strengthen function and have reduced size.Although it is clear and definite strengthening function and having the benefit that reduced size brings, yet realizes that these benefits can produce some problems.Particularly, electronic product need to be established highdensity semiconductor element in limited space content usually.For example, in mobile phone, personal digital assistant, portable computer and other Portable consumer products in order to accommodating processor, memory, and the free space of other active members or passive device in be restricted.Relatively, packed semiconductor element usually can provide reluctantly the protection of opposing environmental condition and provide input and the electric connection of output.Semiconductor component packing in semiconductor component packaging structure, can be taken valuable space extra in electronic product.Therefore, reduce the shared footprint area (Footprint Area) of semiconductor component packaging structure and become very strong trend.The method a kind of about this subject under discussion forms the stacking type encapsulation that presents with PoP (package-on-package) structure.
General stacking type encapsulation can be through many techniques.For instance, form scolder (solder) afterwards on substrate, carry out electroplating technology to form re-wiring layer (Re-Distribution Layer; RDL).Yet, the liquid medicine that the scolder that exposes easily is subject to using in electroplating process is stung erosion and is attacked, make structure be damaged, this can cause electrical problem and reduce product yield, in addition, formerly need before technical formation re-wiring layer good chip first is formed on substrate, if the yield loss (yield loss) that therefore produces when forming the rerouting circuit, loss simultaneously has been formed on the chip on substrate, causes cost significantly to improve.
Summary of the invention
The present invention is relevant for a kind of stacking type encapsulation and manufacture method thereof.The yield of stacking type encapsulation is high.
According to a scheme of the present invention, a kind of manufacture method of stacking type encapsulation is proposed, comprise the following steps.Form an encapsulating structure, method comprises the following steps.One first substrate is provided.First substrate comprises a second surface of a first surface and relative first surface.Configuration one chip on the first surface of first substrate.Several conducting spheres of configuration on the first surface of first substrate.Form a packaging body, coat first surface, chip and the conducting sphere of first substrate.Packaging body has several openings and exposes conducting sphere.Formation comprises a second substrate of relative a lower surface and a upper surface, and method comprises the following steps.Form one first dielectric surface that several conductive poles protrude from a dielectric structure.Form one second dielectric surface that several conductive junction points are exposed to dielectric structure.The first dielectric surface is with respect to the second dielectric surface.The upper surface of second substrate comprises the second dielectric surface.Conductive pole and conductive junction point be electrically connect each other.Via several solder material physical connections and be electrically connected the conducting sphere of encapsulating structure and the conductive pole of second substrate.
According to of the present invention one another scheme, a kind of stacking type encapsulation is proposed, comprise an encapsulating structure, a second substrate and several solder materials.Encapsulating structure comprises a first substrate, a chip and a packaging body.First substrate comprises a second surface of a first surface and relative first surface.Chip configuration is at the first surface of first substrate.Conducting sphere is configured in the first surface of first substrate and around chip.The first surface of packaging body coats first substrate, chip and conducting sphere.Second substrate comprises the upper surface in the face of a lower surface of encapsulating structure and relative lower surface.Second substrate comprises a dielectric layer, several conductive poles and several conductive junction points.Dielectric layer has a dielectric surface.Dielectric surface is the part of the lower surface of second substrate.Conductive pole protrudes from the dielectric surface of dielectric layer.Conductive junction point is exposed to the upper surface of second substrate.Conductive pole and conductive junction point be electrically connect each other.The solder material physical connection also is electrically connected the conducting sphere of encapsulating structure and the conductive pole of second substrate.
For there is better understanding above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and cooperation accompanying drawing are described in detail below:
Description of drawings
Fig. 1 illustrates the encapsulating structure according to the stacking type encapsulation of an embodiment.
Fig. 2 illustrates the encapsulating structure according to the stacking type encapsulation of an embodiment.
Fig. 3 illustrates the encapsulating structure according to the stacking type encapsulation of an embodiment.
Fig. 4 illustrates the second substrate according to the stacking type encapsulation of an embodiment.
Fig. 5 illustrates the stacking type encapsulation according to an embodiment.
Fig. 6 illustrates the stacking type encapsulation according to an embodiment.
Fig. 7 illustrates the second substrate according to the stacking type encapsulation of an embodiment.
Fig. 8 illustrates the stacking type encapsulation according to an embodiment.
Fig. 9 illustrates the stacking type encapsulation according to an embodiment.
Figure 10 illustrates the second substrate according to the stacking type encapsulation of an embodiment.
Figure 11 illustrates the stacking type encapsulation according to an embodiment.
Figure 12 illustrates the stacking type encapsulation according to an embodiment.
Figure 13 illustrates the stacking type encapsulation according to an embodiment.
Figure 14 illustrates the second substrate according to the stacking type encapsulation of an embodiment.
Figure 15 illustrates the stacking type encapsulation according to an embodiment.
Figure 16 illustrates the stacking type encapsulation according to an embodiment.
Figure 17 illustrates the second substrate according to the stacking type encapsulation of an embodiment.
Figure 18 illustrates the stacking type encapsulation according to an embodiment.
Figure 19 illustrates the stacking type encapsulation according to an embodiment.
Figure 20 illustrates the second substrate according to the stacking type encapsulation of an embodiment.
Figure 21 illustrates the stacking type encapsulation according to an embodiment.
Figure 22 illustrates the stacking type encapsulation according to an embodiment.
Figure 23 illustrates the stacking type encapsulation according to an embodiment.
Figure 24 A to Figure 24 F illustrates the manufacture method according to encapsulating structure in an embodiment.
Figure 25 A to Figure 25 I illustrates the manufacture method according to second substrate in an embodiment.
Figure 26 A to Figure 26 K illustrates the manufacture method according to second substrate in an embodiment.
Symbol description:
102,202,302: encapsulating structure;
103: active surface;
104: chip;
105: conductive unit;
106: solder ball;
108: first substrate;
110,118,123: the surface;
112,116,122: conductive pad;
114: encapsulated layer;
120,220: conducting sphere;
124: packaging body;
440,442,444,550,552,554,466,470,574,580,586: dielectric layer;
436,736: lower surface; 126: opening;
128: solder layer;
430,530,630,730,830,930: second substrate;
432,532: conductive structure;
434,534: dielectric structure;
435,735: conductive junction point;
436,536: dielectric surface;
437,737: line layer;
438,538: conductive pole;
439,739: upper surface;
546,846: solder film;
648,948: the scolder lid;
456,556: glue-line;
458,558,464,468,572,576,578,582,584: conductive layer;
460,560: carrier.
Embodiment
Fig. 1 illustrates the encapsulating structure 102 according to the stacking type encapsulation of an embodiment.Above-mentioned encapsulating structure 102 comprises first substrate 108, chip 104, a plurality of solder ball 106 and a packaging body 124, and chip 104 and a plurality of solder ball 106 are positioned on the surface 110 of first substrate 108.
Please refer to Fig. 1, conducting sphere 120 is configured on conductive pad 122 on the surface 110 of first substrate 108.In this embodiment, the material of conducting sphere 120 is scolder, and around chip 104.In an embodiment, for instance, the particle diameter of conducting sphere 120 can be 20um～150um.Spacing between conducting sphere 120 (pitch) can be 0.1mm～0.5mm.The material of conductive pad 122 can comprise the alloy of metal such as copper, gold or above-mentioned metal etc.Packaging body 124 coats surface 110, conducting sphere 120, the chip 104 and encapsulated layer 114 of first substrate 108.Packaging body 124 has the opening 126 that exposes conducting sphere 120.In other words, conducting sphere 120 is the surfaces 123 that are exposed to packaging body 124.In an embodiment, for instance, the degree of depth of opening 126 can be 20um～60um.Solder layer 128 is configured on the conducting sphere 120 that the opening 126 of packaging body 124 exposes.
The encapsulating structure 202 of Fig. 2 is with the difference of the encapsulating structure 102 of Fig. 1, is to have omitted the solder layer 128 in Fig. 1.In this embodiment, the material of conducting sphere 120 is scolder.
The encapsulating structure 302 of Fig. 3 is with the difference of the encapsulating structure 202 of Fig. 2, and the material of conducting sphere 220 comprises metal.In an embodiment, the material of conducting sphere 220 is alloys of copper, gold or above-mentioned metal.In other embodiment, also can use other suitable metal materials.
The encapsulating structure of embodiment is not limited to Fig. 1 to structure shown in Figure 3.Please refer to Fig. 3, in other embodiment, for instance, also configurable solder layer (not shown) is on the conducting sphere 220 (for example alloy of the metal of copper, gold or above-mentioned metal) that the opening 126 of packaging body 124 exposes.
Fig. 4 illustrates the second substrate 430 according to the stacking type encapsulation of an embodiment.Second substrate 430 comprises upper surface 439, lower surface 436 and line layer 437, and line layer 437 comprises conductive structure 432 and dielectric structure 434, and wherein conductive structure 432 is formed in dielectric structure 434, and wherein line layer 437 can be one or more layers structure.The lower surface 436 of second substrate 430 comprises the dielectric surface of dielectric structure 434 and protrudes from the conductive pole 438 of dielectric surface, the upper surface 439 of second substrate 430 comprises dielectric surface and the conductive junction point 435 of dielectric structure 434, and the conductive structure 432 that wherein conductive pole 438 and conductive junction point 435 can be by line layers 437 is electrically connect each other.Conductive junction point 435 can comprise contact pad.In an embodiment, for instance, the width of conductive pole 438 (diameter) is 15um～120um.The material of conductive structure 432, conductive junction point 435, conductive pole 438 comprises the alloy of metal such as copper, gold or above-mentioned metal etc.Dielectric structure 434 can comprise dielectric layer 440 and dielectric layer 442.Conductive structure 432 can be formed on dielectric layer 440.Line layer 437 can comprise re-wiring layer (Re-Distribution Layer; RDL).In an embodiment, for instance, the thickness of second substrate 430 can be 60um～200um.The conductive junction point 435 of second substrate 430 upper surfaces 439 can with at least one chip electrically connect, the method for electrically connect is for example by covering crystalline substance or routing mode.
Fig. 5 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 102 physical connections of Fig. 1 and be electrically connected to the second substrate 430 of Fig. 4, wherein the lower surface 436 of second substrate 430 is the surfaces 123 in the face of encapsulating structure 102.Please refer to Fig. 5, in embodiment, after can touching the solder layer 128 of encapsulating structure 102 at the conductive pole 438 with second substrate 430, carry out the reflow step, so that conductive pole 438 physical connections and be electrically connected to solder layer 128 and conducting sphere 120.In this embodiment, solder layer 128 comprises for example scolding tin of solder material with conducting sphere 120.In an embodiment, because solder layer 128 is soft tin creams, therefore make second substrate 430 near in the process of encapsulating structure 102, conductive pole 438 except can with the surface engagement of solder layer 128, also can imbed a little further solder layer 128, make technique that larger nargin be arranged.In an embodiment, for instance, the thickness of stacking type encapsulation can be 230um～600um.
In embodiment, after being formed separately encapsulating structure 102 and second substrate 430, just carry out the Connection Step of conductive pole 438 and solder layer 128, therefore can be before Connection Step, first respectively to encapsulating structure 102 and second substrate 430 carry out testing electrical property confirm encapsulating structure 102 and 430 of second substrates do not have good electrically, and then carry out Connection Step.In addition, because encapsulating structure 102 and second substrate 430 are to separate manufacturing, so the solder material of encapsulating structure 102 (conducting sphere 120 and solder layer 128, scolding tin for example) can't be subject to the technogenic influence of the plated material (for example conductive structure 432, and material can comprise the alloy of metal such as copper, gold or above-mentioned metal etc.) of second substrate 430.So, yield that can improving product, in addition, with conductive pole and the solder layer electrically connect as the up and down encapsulating structure, with respect to up and down all with the connected mode of tin ball can improve the tin ball at engaging process because melting causes bridge joint (bridge) phenomenon, the problem of the short circuit that produces (short).
In an embodiment, for instance, can second substrate 430 dorsad the upper surface 439 of encapsulating structure 102 via the glue-line (not shown), second substrate 430 is adhered to the carrier (not shown), to improve the structural strength of second substrate 430 in being connected to encapsulating structure 102 processes.Can after the step of carrying out the reflow solder material, remove glue-line and carrier.Solder ball 462 is configurable on conductive pad 116.
In an embodiment, for instance, with encapsulating structure 102 physical connections of Fig. 1 and after being electrically connected to the second substrate 430 of Fig. 4, can continue to stack other device on the conductive junction point 435 of the upper surface 439 of second substrate 430, for example by covering crystal grain that crystalline substance or routing mode be electrically connected, wire etc.This concept can be applied to other embodiment, repeats no more afterwards.
Fig. 6 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 202 physical connections of Fig. 2 and be electrically connected to the second substrate 430 of Fig. 4.Please refer to Fig. 6, in embodiment, the conducting sphere 120 (material is scolder) that can touch at the conductive pole 438 with second substrate 430 encapsulating structure 202 afterwards, carries out the reflow step, so that conductive pole 438 physical connections and be electrically connected to conducting sphere 120.
In embodiment, after being formed separately encapsulating structure 202 and second substrate 430, just carry out the Connection Step of conductive pole 438 and conducting sphere 120, therefore can be before Connection Step, first respectively to encapsulating structure 202 and second substrate 430 carry out testing electrical property confirm encapsulating structure 202 and 430 of second substrates do not have good electrically, and then carry out Connection Step.In addition, because encapsulating structure 202 and second substrate 430 are to separate manufacturing, therefore the solder material (conducting sphere 120) of encapsulating structure 202 can't be subject to the technogenic influence of the plated material (conductive structure 432, material can comprise metal such as copper etc.) of second substrate 430.So, can reduce the loss of good chip and the yield of improving product, in addition, with conductive pole and the solder layer electrically connect as the up and down encapsulating structure, with respect to up and down all with the connected mode of tin ball can reduce the tin ball at engaging process because melting causes bridge joint (bridge) phenomenon, the problem of the short circuit that produces (short).
The second substrate 530 of Fig. 7 is with the difference of the second substrate 430 of Fig. 4, and solder film 546 is formed on the surface of lower surface 436 that conductive pole 438 is exposed to second substrate 530.
Fig. 8 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 102 physical connections of Fig. 1 and be electrically connected to the second substrate 530 of Fig. 7.Please refer to Fig. 8, in embodiment, can be after the solder film 546 on the conductive pole 438 of second substrate 530 be touched the solder layer 128 of encapsulating structure 102, carry out the reflow step, so that solder film 546, solder layer 128 and conducting sphere 120 (solder material) merge, and physical connection and be electrically connected at conductive pole 438, to reach physics and the electric connection of encapsulating structure 102 and second substrate 530.In embodiment, after being formed separately encapsulating structure 102 and second substrate 530, just carry out the Connection Step of solder film 546 and solder layer 128, the benefit of bringing and the related description of Fig. 5 are similar, repeat no more in this.
Fig. 9 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 202 physical connections of Fig. 2 and be electrically connected to the second substrate 530 of Fig. 7.Please refer to Fig. 9, in embodiment, can be at the conducting sphere 120 (material is scolder) that the solder film 546 on the conductive pole 438 of second substrate 530 is touched encapsulating structure 202 afterwards, carry out the reflow step, so that solder film 546 merges with conducting sphere 120, and physical connection and be electrically connected at conductive pole 438, to reach physics and the electric connection of encapsulating structure 202 and second substrate 530.In embodiment, after being formed separately encapsulating structure 202 and second substrate 530, just carry out the Connection Step of solder film 546 and conducting sphere 20 (solder material), the benefit of bringing and the related description of Fig. 6 are similar, repeat no more in this.
The second substrate 630 of Figure 10 is with the difference of the second substrate 430 of Fig. 4, and scolder lid 648 is formed on the end surface of conductive pole 438.
Figure 11 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 102 physical connections of Fig. 1 and be electrically connected to the second substrate 630 of Figure 10.Please refer to Figure 11, in embodiment, can be after the lid of the scolder on the conductive pole 438 of second substrate 630 648 be touched the solder layer 128 of encapsulating structure 102, carry out the reflow step, so that scolder lid 648, solder layer 128 and conducting sphere 120 (solder material) merge, and physical connection and be electrically connected at conductive pole 438, to reach physics and the electric connection of encapsulating structure 102 and second substrate 630.In embodiment, after being formed separately encapsulating structure 102 and second substrate 630, just carry out the Connection Step of scolder lid 648 and solder layer 128, the benefit of bringing and the related description of Fig. 5 are similar, repeat no more in this.
Figure 12 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 202 physical connections of Fig. 2 and be electrically connected to the second substrate 630 of Figure 10.Please refer to Figure 12, in embodiment, can be at the conducting sphere 120 (material is scolder) that the lid of the scolder on the conductive pole 438 of second substrate 630 648 is touched encapsulating structure 202 afterwards, carry out the reflow step, so that scolder lid 648 merges with conducting sphere 120, and physical connection and be electrically connected at conductive pole 438, to reach physics and the electric connection of encapsulating structure 202 and second substrate 630.In embodiment, after being formed separately encapsulating structure 202 and second substrate 630, just carry out the Connection Step of scolder lid 648 and conducting sphere 120 (solder material), the benefit of bringing and the related description of Fig. 6 are similar, repeat no more in this.
Figure 13 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 302 physical connections of Fig. 3 and be electrically connected to the second substrate 630 of Figure 10.Please refer to Figure 13, in embodiment, scolder on the conductive pole 438 of second substrate 630 lid 648 conducting spheres 220 (material is for example copper of metal) that touch encapsulating structure 302 afterwards, can carried out the reflow step, with physical connection and be electrically connected at conductive pole 438 and conducting sphere 220.
In embodiment, after being formed separately encapsulating structure 302 and second substrate 630, just carry out Connection Step, therefore can be before Connection Step, first respectively to encapsulating structure 302 and second substrate 630 carry out testing electrical property confirm encapsulating structure 302 and 630 of second substrates do not have good electrically, and then carry out Connection Step.So, can reduce the loss of good chip and the yield of improving product.
The second substrate 730 of Figure 14 is with the difference of the second substrate 430 of Fig. 4, and line layer 737 comprises conductive structure 532 and dielectric structure 534, and wherein conductive structure 532 is formed in dielectric structure 534, and wherein line layer 737 can be one or more layers structure.The lower surface 736 of second substrate 730 comprises the dielectric surface of dielectric structure 534 and protrudes from the conductive pole 538 of dielectric surface, the upper surface 739 of second substrate 730 comprises dielectric surface and the conductive junction point 735 of dielectric structure 534, and the conductive structure 532 that wherein conductive pole 538 and conductive junction point 735 can be by line layers 737 is electrically connect each other.The material of conductive structure 532, conductive junction point 735, conductive pole 538 comprises metal such as copper etc.Dielectric structure 534 can comprise dielectric layer 550, dielectric layer 552 and dielectric layer 554.In an embodiment, for instance, the thickness of second substrate 730 can be 60um～200um.The conductive junction point 735 of second substrate 730 upper surfaces 739 can with at least one chip electrically connect, the method for electrically connect is for example by covering crystalline substance or routing mode.
Figure 15 illustrates the stacking type encapsulation according to an embodiment.Be wherein with encapsulating structure 102 physical connections of Fig. 1 and be electrically connected to the second substrate 730 of Figure 14.Please refer to Figure 15, in embodiment, after can touching the solder layer 128 of encapsulating structure 102 at the conductive pole 538 with second substrate 730, carry out the reflow step, so that conductive pole 538 physical connections and be electrically connected to solder layer 128 and conducting sphere 120.In this embodiment, solder layer 128 comprises solder material with conducting sphere 120.In embodiment, after being formed separately encapsulating structure 102 and second substrate 730, just carry out the Connection Step of conductive pole 538 and solder layer 128, the benefit of bringing and the related description of Fig. 5 are similar, repeat no more in this.In an embodiment, for instance, the thickness of stacking type encapsulation can be 230um～600um.
Figure 16 illustrates the stacking type encapsulation according to an embodiment.Be wherein with encapsulating structure 202 physical connections of Fig. 2 and be electrically connected to the second substrate 730 of Figure 14.Please refer to Figure 16, in embodiment, the conducting sphere 120 (material is scolder) that can touch at the conductive pole 538 with second substrate 730 encapsulating structure 202 afterwards, carries out the reflow step, so that conductive pole 538 physical connections and be electrically connected to conducting sphere 120.In embodiment, after being formed separately encapsulating structure 202 and second substrate 730, just carry out the Connection Step of conductive pole 538 and conducting sphere 120, the benefit of bringing and the related description of Fig. 6 are similar, repeat no more in this.
The second substrate 830 of Figure 17 is with the difference of the second substrate 730 of Figure 14, and solder film 846 is formed on the surface of lower surface 536 that conductive pole 538 is exposed to second substrate 730.
Figure 18 illustrates the stacking type encapsulation according to an embodiment.Be wherein with encapsulating structure 102 physical connections of Fig. 1 and be electrically connected to the second substrate 830 of Figure 17.Please refer to Figure 18, in embodiment, can be after the solder film 846 on the conductive pole 538 of second substrate 830 be touched the solder layer 128 of encapsulating structure 102, carry out the reflow step, so that solder film 846, solder layer 128 and conducting sphere 120 (solder material) merge, and physical connection and be electrically connected at conductive pole 538, to reach physics and the electric connection of encapsulating structure 102 and second substrate 830.In embodiment, after being formed separately encapsulating structure 102 and second substrate 830, just carry out the Connection Step of solder film 846 and solder layer 128, the benefit of bringing and the related description of Fig. 8 are similar, repeat no more in this.
Figure 19 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 202 physical connections of Fig. 2 and be electrically connected to the second substrate 830 of Figure 17.Please refer to Figure 19, in embodiment, can be at the conducting sphere 120 (material is scolder) that the solder film 846 on the conductive pole 538 of second substrate 830 is touched encapsulating structure 202 afterwards, carry out the reflow step, so that solder film 846 merges with conducting sphere 120, and physical connection and be electrically connected at conductive pole 538, to reach physics and the electric connection of encapsulating structure 202 and second substrate 830.In embodiment, after being formed separately encapsulating structure 202 and second substrate 830, just carry out the Connection Step of solder film 846 and conducting sphere 120 (solder material), the benefit of bringing and the related description of Fig. 6 are similar, repeat no more in this.
The second substrate 930 of Figure 20 is with the difference of the second substrate 730 of Figure 14, and scolder lid 948 is formed on the end surface of conductive pole 538.
Figure 21 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 102 physical connections of Fig. 1 and be electrically connected to the second substrate 930 of Figure 20.Please refer to Figure 21, in embodiment, can be after the lid of the scolder on the conductive pole 538 of second substrate 930 948 be touched the solder layer 128 of encapsulating structure 102, carry out the reflow step, so that scolder lid 948, solder layer 128 merge with conducting sphere 120 (solder material), and physical connection be electrically connected at conductive pole 538 to reach physics and the electric connection of encapsulating structure 102 and second substrate 930.In embodiment, after being formed separately encapsulating structure 102 and second substrate 930, just carry out the Connection Step of scolder lid 948 and solder layer 128, the benefit of bringing and the related description of Fig. 5 are similar, repeat no more in this.
Figure 22 illustrates the manufacture method according to the stacking type encapsulation of an embodiment.Be wherein with encapsulating structure 202 physical connections of Fig. 2 and be electrically connected to the second substrate 930 of Figure 20.Please refer to Figure 22, in embodiment, can be at the conducting sphere 120 (material is scolder) that the lid of the scolder on the conductive pole 538 of second substrate 930 948 is touched encapsulating structure 202 afterwards, carry out the reflow step, so that scolder lid 948 merges with conducting sphere 120, and physical connection and be electrically connected at conductive pole 538, to reach physics and the electric connection of encapsulating structure 202 and second substrate 930.In embodiment, after being formed separately encapsulating structure 202 and second substrate 930, just carry out the Connection Step of scolder lid 948 and conducting sphere 120 (solder material), the benefit of bringing and the related description of Fig. 6 are similar, repeat no more in this.
Figure 23 illustrates the stacking type encapsulation according to an embodiment.Be wherein with encapsulating structure 302 physical connections of Fig. 3 and be electrically connected to the second substrate 930 of Figure 20.Please refer to Figure 23, in embodiment, scolder on the conductive pole 538 of second substrate 930 lid 948 conducting spheres 220 (material is for example copper of metal) that touch encapsulating structure 302 afterwards, can carried out the reflow step, with physical connection and be electrically connected at conductive pole 538 and conducting sphere 220.
In embodiment, after being formed separately encapsulating structure 302 and second substrate 930, just carry out Connection Step, therefore can be before Connection Step, first respectively to encapsulating structure 302 and second substrate 930 carry out testing electrical property confirm encapsulating structure 302 and 930 of second substrates do not have good electrically, and then carry out Connection Step.So, can reduce the loss of good chip and the yield of improving product.
Figure 24 A to Figure 24 F illustrates the manufacture method according to encapsulating structure in an embodiment.
Please refer to Figure 24 A, first substrate 108 is provided.Form conductive pad 112,116,122 on first substrate 108.
Please refer to Figure 24 B, utilize crystalline substance (flip chip) technology of covering, solder ball 106 is configured between conductive pad 122 on chip 104 and first substrate 108, and solder ball 106 is carried out the reflow step to connect chip 104 and conductive pad 122.Encapsulated layer 114 envelopes are formed between chip 104 and first substrate 108.
Please refer to Figure 24 C, conducting sphere 120 is configured on conductive pad 122 on first substrate 108, and carries out the reflow step.
Please refer to Figure 24 D, can utilize the mode of vacuum lamination (vacuum lamination), be configured in packaging body 124 on first substrate 108 and cover conducting sphere 120.Be the embodiment of scolder with respect to conducting sphere 120, conducting sphere (for example sign in Fig. 3 220) for metal for example the embodiment of copper have higher structural strength, therefore more can not be out of shape in the process of laminating packaging body 124.Can toast (baking) step to packaging body 124.
Please refer to Figure 24 E, can utilize the mode of laser, hole from the surface 123 of packaging body 124, expose the opening 126 of conducting sphere 120 with formation.Be the embodiment of scolder with respect to conducting sphere 120, conducting sphere (for example sign in Fig. 3 220) for metal for example copper embodiment have higher structural strength, therefore more can not be damaged in the process of laser.In an embodiment, for instance, the degree of depth of opening 126 is 20um～60um.
Please refer to Figure 24 F, can utilize the mode of printing, tin cream (solder paste) is inserted the opening 126 of packaging body 124, to form the solder layer 128 of position on conducting sphere 120.Because tin cream matter is soft, therefore in certain embodiments, even tin cream is not aimed in the process of inserting opening 126 and is printed on conducting sphere 120, tin cream also can slide into along the sidewall of opening 126 conducting sphere 120, in other words, the formation of solder layer 128 can be stood larger deviation of the alignment, so process margin is large, and also can save the use amount of material.Moreover because opening 126 can form larger size (diameter), for example 20um～150um, therefore can have larger technique form (process window) in the process of print solder paste.In an embodiment, solder layer 128 can't fill up the volume of opening 126 fully, so can prevent the conductive pole of second substrate (not shown) after imbedding solder layer 128, solder layer 128 is squeezed and overflows opening 126, and the problem of bridge joint occurs between material.In an embodiment, for instance, solder layer 128 be account for opening 126 volume 20%～80%.In an embodiment, after forming solder layer 128, can carry out the reflow step.
Figure 25 A to Figure 25 I illustrates the manufacture method according to second substrate in an embodiment.
Please refer to Figure 25 A, utilize glue-line 456 that conductive layer 458 is pasted on carrier 460.In an embodiment, the material of conductive layer 458 comprises metal, is for example Copper Foil (Cu foil).The thickness of conductive layer 458 can be 3um.Glue-line 456 can comprise the separation glued membrane.
Please refer to Figure 25 B, can form dielectric layer 440 on conductive layer 458.In an embodiment, for instance, the formation method of dielectric layer 462 can comprise green paint (solder resist) lamination or be coated on conductive layer 458, then exposes, development step comes patterning, and can carry out baking procedure.
Please refer to Figure 25 C, can utilize the mode of deposition, with conductive layer 464 for example Seed Layer (seed layer) be formed on conductive layer 458 and dielectric layer 440.In an embodiment, before forming conductive layer 464, can carry out alligatoring (desmear) step to the surface of dielectric layer 440.
Please refer to Figure 25 D, form dielectric layer 466 on conductive layer 464.Dielectric layer 466 can comprise photoresistance.The formation method of dielectric layer 466 can comprise laminating film (dry film), then exposes, development step comes patterning.
Please refer to Figure 25 E, can utilize the mode of plating, form conductive layer 444 from conductive layer 464.The material of conductive layer 444 can comprise metal such as copper etc.Then, remove the conductive layer 464 of dielectric layer 466 and dielectric layer 466 belows.
Please refer to Figure 25 F, form dielectric layer 442 on conductive layer 444 and dielectric layer 440.The formation method of dielectric layer 442 can comprise that the lamination dielectric film on conductive layer 444 and dielectric layer 440, then forms opening to expose conductive layer 444.
Please refer to Figure 25 G, can utilize the mode of deposition, with conductive layer 468 for example Seed Layer be formed on conductive layer 444 and dielectric layer 440.In an embodiment, before forming conductive layer 468, can carry out the alligatoring step to the surface of dielectric layer 440.
Please refer to Figure 25 H, form dielectric layer 470 on conductive layer 468.Dielectric layer 470 can comprise photoresistance.The formation method of dielectric layer 470 can comprise laminating film, then exposes, development step comes patterning.
Please refer to Figure 25 I, can utilize the mode of plating, form conductive layer from conductive layer 468, to form conductive structure 432 and conductive pole 438.Then, remove the conductive layer 468 of dielectric layer 470 and dielectric layer 470 belows.Can be from glue-line 456 from transfer body 460, and conductive layer 458 is removed, to form second substrate 430 as shown in Figure 4.
Figure 26 A to Figure 26 K illustrates the manufacture method according to second substrate in an embodiment.
Please refer to Figure 26 A, utilize glue-line 556 that conductive layer 558 is pasted on carrier 560.In an embodiment, the material of conductive layer 558 comprises metal, is for example Copper Foil (Cu foil).The thickness of conductive layer 558 can be 3um.Glue-line 556 can comprise the separation glued membrane.
Please refer to Figure 26 B, can form dielectric layer 550 on conductive layer 558.In an embodiment, for instance, the formation method of dielectric layer 550 can comprise presses green enamelled coating or be coated on conductive layer 558, then exposes, development step comes patterning, and can carry out baking procedure.
Please refer to Figure 26 C, can utilize the mode of deposition, with conductive layer 572 for example Seed Layer be formed on conductive layer 558 and dielectric layer 550.In an embodiment, before forming conductive layer 572, can carry out the alligatoring step to the surface of dielectric layer 550.Form dielectric layer 574 on conductive layer 572.Dielectric layer 574 can comprise photoresistance.The formation method of dielectric layer 574 can comprise laminating film, then exposes, development step comes patterning.
Please refer to Figure 26 D, can utilize the mode of plating, form conductive layer 576 from conductive layer 572.The material of conductive layer 576 can comprise metal such as copper etc.Then, remove the conductive layer 572 of dielectric layer 574 and dielectric layer 574 belows.
Please refer to Figure 26 E, can utilize the mode of vacuum lamination, dielectric layer 552 is configured on conductive layer 576 and dielectric layer 550.Can carry out baking procedure to dielectric layer 552.Can utilize the mode of laser, dielectric layer 552 is holed, expose the opening of conductive layer 576 with formation.
Please refer to Figure 26 F, can utilize the mode of deposition, with conductive layer 578 for example Seed Layer be formed on conductive layer 576 and dielectric layer 552.In an embodiment, before forming conductive layer 578, can carry out the alligatoring step to the surface of dielectric layer 552.
Please refer to Figure 26 G, form dielectric layer 580 on conductive layer 578.Dielectric layer 580 can comprise photoresistance.The formation method of dielectric layer 580 can comprise laminating film, then exposes, development step comes patterning.
Please refer to Figure 26 H, can utilize the mode of plating, form conductive layer 582 from conductive layer 578.The material of conductive layer 582 can comprise metal such as copper etc.Then, remove the conductive layer 578 of dielectric layer 580 and dielectric layer 580 belows.
Please refer to Figure 26 I, can form dielectric layer 554 on conductive layer 582 and dielectric layer 552.In an embodiment, for instance, the formation method of dielectric layer 554 can comprise to be pressed green enamelled coating or be coated on conductive layer 582 and dielectric layer 552, then exposes, development step comes patterning, and can carry out baking procedure.
Please refer to Figure 26 J, can utilize the mode of deposition, with conductive layer 584 for example Seed Layer be formed on conductive layer 582 and dielectric layer 554.In an embodiment, before forming conductive layer 584, can carry out the alligatoring step to the surface of dielectric layer 554.Form dielectric layer 586 on conductive layer 584.Dielectric layer 586 can comprise photoresistance.The formation method of dielectric layer 586 can comprise laminating film, then exposes, development step comes patterning.
Please refer to Figure 26 K, can utilize the mode of plating, form conductive layer from conductive layer 584, to form conductive structure 532 and conductive pole 538.The material of conductive structure 532 can comprise metal such as copper etc.Then, remove the conductive layer 584 of dielectric layer 586 and dielectric layer 586 belows.Can be from glue-line 556 from transfer body 560, and conductive layer 558 is removed, to form second substrate 730 as shown in figure 14.
In sum, although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347532A (en) * | 2013-07-31 | 2015-02-11 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| WO2016049940A1 (en) * | 2014-10-03 | 2016-04-07 | Intel Corporation | Overlapping stacked die package with vertical columns |
| CN105632939A (en) * | 2015-12-24 | 2016-06-01 | 合肥祖安投资合伙企业(有限合伙) | Packaging structure with redistribution layer and manufacturing method thereof |
| TWI550791B (en) * | 2014-01-16 | 2016-09-21 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN109637995A (en) * | 2013-09-03 | 2019-04-16 | 日月光半导体制造股份有限公司 | Board structure, encapsulating structure and its manufacturing method |
| CN113675152A (en) * | 2021-07-22 | 2021-11-19 | 日月光半导体制造股份有限公司 | Semiconductor package structure and method of forming the same |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11018056B1 (en) * | 2019-11-01 | 2021-05-25 | Micron Technology, Inc. | Encapsulated solder TSV insertion interconnect |
| US10998271B1 (en) | 2019-11-01 | 2021-05-04 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
| US11088114B2 (en) | 2019-11-01 | 2021-08-10 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
| US11404386B2 (en) | 2020-08-28 | 2022-08-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200425449A (en) * | 2003-05-02 | 2004-11-16 | Advanced Semiconductor Eng | Stacked flip chip package |
| US20080142943A1 (en) * | 2006-12-18 | 2008-06-19 | Hyun Joung Kim | Integrated circuit package system with thermo-mechanical interlocking substrates |
| US20100171205A1 (en) * | 2009-01-07 | 2010-07-08 | Kuang-Hsiung Chen | Stackable Semiconductor Device Packages |
| US7851894B1 (en) * | 2008-12-23 | 2010-12-14 | Amkor Technology, Inc. | System and method for shielding of package on package (PoP) assemblies |
| CN102637678A (en) * | 2011-02-15 | 2012-08-15 | 欣兴电子股份有限公司 | Package stack device and method for fabricating the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI492349B (en) * | 2010-09-09 | 2015-07-11 | 矽品精密工業股份有限公司 | Chip scale package structure and fabrication method thereof |
| CN102915984A (en) * | 2012-09-20 | 2013-02-06 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
-
2013
- 2013-03-29 CN CN201310109714.1A patent/CN103165484B/en active Active
- 2013-03-29 CN CN201610668668.2A patent/CN106229270A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200425449A (en) * | 2003-05-02 | 2004-11-16 | Advanced Semiconductor Eng | Stacked flip chip package |
| US20080142943A1 (en) * | 2006-12-18 | 2008-06-19 | Hyun Joung Kim | Integrated circuit package system with thermo-mechanical interlocking substrates |
| US7851894B1 (en) * | 2008-12-23 | 2010-12-14 | Amkor Technology, Inc. | System and method for shielding of package on package (PoP) assemblies |
| US20100171205A1 (en) * | 2009-01-07 | 2010-07-08 | Kuang-Hsiung Chen | Stackable Semiconductor Device Packages |
| CN102637678A (en) * | 2011-02-15 | 2012-08-15 | 欣兴电子股份有限公司 | Package stack device and method for fabricating the same |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347532A (en) * | 2013-07-31 | 2015-02-11 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN104347532B (en) * | 2013-07-31 | 2017-08-04 | 日月光半导体制造股份有限公司 | Semiconductor package and method of manufacturing the same |
| CN109637995A (en) * | 2013-09-03 | 2019-04-16 | 日月光半导体制造股份有限公司 | Board structure, encapsulating structure and its manufacturing method |
| TWI550791B (en) * | 2014-01-16 | 2016-09-21 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
| WO2016049940A1 (en) * | 2014-10-03 | 2016-04-07 | Intel Corporation | Overlapping stacked die package with vertical columns |
| US10256208B2 (en) | 2014-10-03 | 2019-04-09 | Intel Corporation | Overlapping stacked die package with vertical columns |
| US10629561B2 (en) | 2014-10-03 | 2020-04-21 | Intel Corporation | Overlapping stacked die package with vertical columns |
| CN105632939A (en) * | 2015-12-24 | 2016-06-01 | 合肥祖安投资合伙企业(有限合伙) | Packaging structure with redistribution layer and manufacturing method thereof |
| CN113675152A (en) * | 2021-07-22 | 2021-11-19 | 日月光半导体制造股份有限公司 | Semiconductor package structure and method of forming the same |
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|---|---|
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| CN103165484B (en) | 2016-09-07 |
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