CN106941101A - Package substrate and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a packaging substrate and a manufacturing method thereof. The packaging substrate comprises: a conductor layer, including at least one metal trace; a conductive connection unit, located on the conductor layer; a circuit chip, having at least one external pin pad, and arranged on the conductive connection unit; and a mold compound layer, covering the conductor layer, the conductive connection unit and the circuit chip; wherein the conductive connection unit is used to connect one of the at least one external pin pad and one of the at least one metal trace.

Description

Packaging substrate and manufacturing method thereof

technical field

The invention relates to a packaging substrate and a manufacturing method thereof, belonging to the technical field of semiconductors.

Background technique

The new generation of electronic products not only pursues light, thin, small and high density, but also tends to develop towards high power; therefore, the integrated circuit (Integrated Circuit, IC) technology and its back-end chip packaging technology have also been developed to meet this new trend. Performance specifications for a generation of electronic products. Embedded component technology, in which circuit chips are embedded in packaging substrates, has become the research and development focus of manufacturers in this field in recent years because of its advantages of reducing noise interference and product size reduction on packaging substrate products. In the prior art, the circuit chips or crystal grains are usually embedded in the molding compound as the main body of the packaging substrate, and then the wiring layer as the circuit layout of the packaging substrate is fabricated.

However, most of the wiring layers are thin lines with narrow width, and the manufacturing process is difficult, so that when the wiring layer has a manufacturing defect, the circuit chip or crystal grain must also be scrapped. In addition, once the circuit chip or die is buried in the packaging substrate, the electrical connection between the circuit chip or die and the external circuit will become difficult to handle, for example, additional laser opening, dielectric material lamination Combined processing and electrical connection circuits with complex structures will increase manufacturing costs and reduce product yields. Therefore, it is necessary to develop a new packaging substrate technology to address and improve the above-mentioned problems.

Contents of the invention

To achieve this purpose, the present invention provides a packaging substrate, which includes: a wire layer including at least one metal wire; a conductive connection unit located on the wire layer; a circuit chip with at least one external pad, and disposed on the conductive connection unit; and a mold compound layer covering the wire layer, the conductive connection unit and the circuit chip; wherein the conductive connection unit is used to connect one of the at least one external pad with the at least one One of the metal traces.

In one embodiment, the conductive connection unit is a metal pillar.

In one embodiment, the conductive connection unit is a solder bump.

In one embodiment, the packaging substrate further includes a heat sink disposed on the circuit chip and connected to the circuit chip.

In one embodiment, the package substrate further includes a metal carrier plate disposed under the wire layer.

In another aspect, the present invention provides a method for manufacturing a packaging substrate, the steps of which include: providing a carrier board; forming a first wire layer on the carrier board, so that the first wire layer includes at least one first metal wire ; forming a conductive connection unit on the first wire layer; setting a circuit chip with at least one external pad on the conductive connection unit, so that the conductive connection unit connects one of the at least one external pad and the at least one one of the first metal traces; and forming a mold compound layer on the circuit chip so that the mold compound layer fills the space between the circuit chip and the carrier board.

In one embodiment, the conductive connection unit is a first metal pillar.

In one embodiment, the conductive connection unit is a solder bump.

In one embodiment, the method further includes: removing a portion of the mold compound layer to expose the upper surface of the circuit chip; and removing the carrier plate.

In one embodiment, the method further includes: disposing a heat sink on the circuit chip, so that the heat sink is connected to the upper surface of the circuit chip.

In one embodiment, the method further includes: forming a second wiring layer on the mold compound layer, such that the second wiring layer includes at least a second metal trace; forming a conductive column layer on the second wiring layer On, the conductive pillar layer includes at least one second metal pillar; and a dielectric material layer is formed on the mold compound layer, and the dielectric material layer covers all the at least one second metal pillar on the mold compound layer. The metal wiring and the at least one second metal pillar.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a package substrate according to a first embodiment of the present invention.

2-6 are cross-sectional views of various manufacturing steps of the package substrate according to the first embodiment of the present invention.

7A and 7B are schematic cross-sectional views of a packaging substrate according to a second embodiment of the present invention.

8-10 are cross-sectional views of various manufacturing steps of the packaging substrate according to the third embodiment of the present invention.

Explanation of reference signs: 100, 200, 300—package substrate; 110—loading board; 120—first wire layer; 121-125—first metal wiring; 130, 131-134—conductive connection unit; 140—circuit chip ;141～144—external pad; 150—molding compound layer; 160—heat sink; 170—second wire layer; 171～174—second metal trace; 180—conductive column layer; 181～184—metal pillar ; 190—Layer of dielectric material.

detailed description

In order to have a better understanding of the features, objectives and functions of the present invention, the embodiments of the present invention will be described in detail below with reference to the drawings. Throughout the description and drawings, the same element number will be used to designate the same or similar elements.

In the description of various embodiments, when an element is described as being "above/on" or "below/under" another element, it means that it is directly or indirectly on or under the other element, It may contain other elements set in between; by "directly" I mean that no other intervening elements are set in between. Descriptions such as "above/up" or "below/under" are described with reference to the drawings, but include other possible changes in direction. The terms "first", "second", and "third" are used to describe various elements, and these elements are not limited by such predicates. For the convenience and clarity of illustration, the thickness or size of each element in the drawings is expressed in an exaggerated, omitted or approximate manner, and the size of each element is not entirely its actual size.

FIG. 1 is a schematic cross-sectional view of a packaging substrate 100 according to a first embodiment of the present invention. The packaging substrate 100 includes: a first wire layer 120 , a conductive connection unit 130 , a circuit chip 140 and a molding compound layer 150 . The first wire layer 120 represents the circuit layout of the packaging substrate 100, which includes at least one first metal wire; the conductive connection unit 130 is formed on the first wire layer 120, and its number can be more than one; the circuit chip 140 is disposed on the conductive connection unit 130, and the circuit chip 140 has at least one external pad; for the convenience of illustration, as shown in the example shown in FIG. wires (numbered 121-125 from left to right), the number of the conductive connection units 130 is four (numbered 131-134 from left to right), and the circuit chip 140 has four external pads (numbered from left to right The numbers are 141-144), but the number is not limited thereto, and depends on the needs of the circuit layout of the packaging substrate 100 . Each conductive connecting unit 131-134 is used to connect one of the external pads 141-144 with one of the first metal traces 121-125; for example, the conductive connecting unit 131 connects the external pad 141 and The first metal trace 121, the conductive connection unit 132 connects the external pad 142 and the first metal trace 122, the conductive connection unit 133 connects the external pad 143 and the first metal trace 123, the conductive The connection unit 134 connects the external pad 144 and the first metal trace 124 . In addition, the molding compound layer 150 covers the first wire layer 120 , the conductive connection unit 130 and the circuit chip 140 , and the part beyond the upper surface of the circuit chip 140 can be used as the outermost protective layer of the packaging substrate 100 .

The composition material of this first wire layer 120 can be the combination or alloy of copper (Cu), nickel (Ni), tin (Sn) and nickel/gold (Ni/Au), and it can be in electrolytic plating (Electrolytic plating), sputtering After the metal film is formed by (Sputtering coating) or evaporation (Evaporation), it is fabricated by a patterning process of Photolithography as one of the circuit layout layers of the packaging substrate 100 . In this embodiment, the first wire layer 120 has five first metal wires 121 - 125 , as shown in FIG. 1 .

The circuit chip 140 is an active device. In this embodiment, the fabrication of the circuit chip 140 may be applied to a semiconductor wafer (wafer) by an integrated circuit (IC) process, and cut into dies, and pre-connected with external pads ( For example, conductive pins, conductive pads, or conductive bumps) will be embedded in the package substrate 100 using embedded device technology. Thereby, the noise interference received by the packaging substrate product can be effectively reduced and the size of the finished product can be reduced, so that it can be applied to an application processor (Application processor) and a power management chip of a portable device. As shown in FIG. 1, the circuit chip 140 has four external pads 141-144. When it is arranged on the conductive connection unit 130, these external pads 141-144 can be self-aligned (Self-alignment). 144 respectively connects the conductive connecting units 131 - 134 without using precise alignment technology.

In order to allow the circuit chip 140 to be connected to the first wire layer 120 without using precise alignment technology, in this embodiment, a conductive connection unit with a columnar structure or a bump structure is fabricated on the first wire layer 120 131-134, such as copper pillars (Cu pillar) or solder bumps (solder bump), so that the external pads 141-144 of the circuit chip 140 can be easily self-aligned to the conductive connection units 131-134, then The manufacturing cost of the packaging substrate can be effectively reduced. In this embodiment, a single conductive connection unit 130 (or, the conductive connection units 131-134) is used to connect one of the external pads 141-144 and the first metal traces 121-125. one of. As shown in FIG. 1, the conductive connection unit 131 connects the external pad 141 and the first metal trace 121, the conductive connection unit 132 connects the external pad 142 and the first metal trace 122, and the conductive connection unit 133 connects the external pad 143 and the first metal trace 123, and the conductive connection unit 134 connects the external pad 144 and the first metal trace 124, so that the circuit chip 140 can be designed according to the circuit design of the package substrate 100 And connected to the first wire layer 120 .

The molding compound layer 150 can be made by molding technology of encapsulating colloid, for example, compression molding (Compression Molding), and the composition material of encapsulating colloid can be phenolic-based resin (Novolac-Based Resin), epoxy-based resin (Epoxy-based resin) Based Resin), or silicone-based resin (Silicone-Based Resin) and other insulating materials, but not limited thereto. The molding compound layer 150 covers the circuit chip 140 and fills the space between the circuit chip 140 and the first wiring layer 120 , so that the packaging substrate 100 forms an electronic component or product with a stable structure. In addition, the portion of the mold compound layer 150 beyond the upper surface of the circuit chip 140 can also be used as an outer protective layer of the package substrate 100 to protect the package substrate 100 from external environment or subsequent processes (such as soldering). of possible harm.

In this embodiment, the packaging substrate 100 can be used as a substrate of a flip chip chip scale package (FCCSP) applied to molded interconnect substrate technology. In addition, the single wire of the circuit layout of the packaging substrate in this embodiment may also be a stacked structure of multiple wire layers, for example, two, three or more layers of wire layers.

The following describes the manufacturing process of the packaging substrate 100 according to the embodiment of the present invention. Please refer to FIGS. 2-6 and FIG. 1 , which respectively correspond to cross-sectional views of the packaging substrate in each process step of the packaging substrate 100 of the above-mentioned embodiment.

First, as shown in FIG. 2, a carrier board 110 is provided, which can be a substrate of conductive material, for example, a metal substrate or a substrate of dielectric material coated with a conductive layer on the surface, for carrying or supporting the packaging substrate 100. Subsequent processes, for example, fabricating the conductive lines of the packaging substrate 100 . The above-mentioned metal substrates include iron (Fe), copper (Cu), nickel (Ni), tin (Sn), aluminum (Al), nickel/gold (Ni/Au) and combinations or alloys thereof, but the present invention does not limit.

Next, as shown in FIG. 2 , a first wire layer 120 is formed on the carrier board 110 such that the first wire layer 120 includes at least one first metal wire. For example, we can use a photosensitive photoresist material to form a photoresist film on the carrier board 110 first, and then pattern it through a lithographic etching process to form a metal plating resist layer, and then electroplate a metal film on it. A pattern of metal traces is formed on the carrier board 110 . Alternatively, we can use a non-photosensitive dielectric material, first form a dielectric film on the carrier plate 110, then pattern the dielectric film by laser transfer technology, and then evaporate or sputter metal film on it, and finally remove the dielectric film by lift-off, while leaving the pattern of the metal wiring on the carrier board 110 . In this embodiment, the wire layer 120 has five first metal wires 121 - 125 , and the composition material thereof may be a combination or alloy of copper, nickel, tin, and nickel/gold.

Next, the at least one conductive connection unit 130 is formed on the first wiring layer 120 . As shown in FIG. 4A, the at least one conductive connection unit 130 includes four conductive connection units 131-134 with a bump structure, such as solder bumps, for connecting the circuit chip 140 to the The first wire layer 120 . However, the number of the at least one conductive connection unit 130 is not limited thereto, and depends on the requirements of the circuit layout of the packaging substrate 100 or the number of external pads of the circuit chip 140 . In another embodiment, the conductive connection units 131'˜134' can also be columnar structures, as shown in FIG. 4B, for example, copper columns, aluminum columns, nickel columns, tin columns or alloy columns, preferably copper pillars. In order to avoid too many details, the second half of this specification uses the conductive connection units 131-134 as bump structures (as shown in FIG. 4A ) to illustrate related embodiments, but readers should understand that these embodiments also It is also applicable to the case where the conductive connecting units 131 ′˜ 134 ′ are columnar structures (as shown in FIG. 4B ).

Next, a circuit chip 140 with at least one external pad is arranged on the at least one conductive connection unit 130 (in this embodiment, the circuit chip 140 has four external pads 141-144, as shown in FIG. 5 , But the present invention is not limited thereto), so that each external pad 141 - 144 is connected to one of the at least one external pad 141 - 144 and one of the at least one first metal trace 121 - 125 . The circuit chip 140 is an active component made by an integrated circuit (IC) process, and is a chip cut into a die form, and has been pre-connected with external pads (for example, conductive pins, conductive pads) or conductive bumps) can be embedded in the packaging substrate 100 by using embedded device technology. When the circuit chip 140 is installed on the conductive connection unit 130, the external pads 141-144 can be easily placed on the conductive connection units 131-134, for example, self-alignment (self-alignment), and Precision alignment techniques need not be used. In this embodiment, the conductive connection unit 131 connects the external pad 141 and the first metal trace 121, the conductive connection unit 132 connects the external pad 142 and the first metal trace 122, and the conductive connection unit 133 connects the external pad 143 and the first metal trace 123, and the conductive connection unit 134 connects the external pad 144 and the first metal trace 124, so that the circuit chip 140 can be designed according to the circuit design of the package substrate 100 And connected to the first wire layer 120 .

Next, as shown in FIG. 6 , a mold compound layer 150 is formed on the circuit chip 140 such that the mold compound layer 150 fills the space between the circuit chip 140 and the carrier plate 110 . The molding compound layer 150 can be made by the molding technique of encapsulating colloid, for example, compression molding method, and the composition material of encapsulating colloid can be insulating materials such as phenolic (Novolac)-based resin, epoxy-based resin, or silicon-based resin, but This is not the limit. The molding compound layer 150 covers the circuit chip 140 and fills the space between the circuit chip 140 and the first wiring layer 120 , so that the packaging substrate 100 forms an electronic component or product with a stable structure. In addition, the part of the molding compound layer 150 beyond the upper surface of the circuit chip 140 can also be used as an outer protective layer of the package substrate 100 to protect the package substrate 100 from the external environment or subsequent processes (such as soldering). of possible harm. So far, the basic circuit of the packaging substrate 100 has been completed, and the carrier board 110 can be removed first, as shown in FIG. 1 .

Embedded component technology, in which circuit chips are embedded in packaging substrates, has become the research and development focus of manufacturers in this field in recent years because of its advantages of reducing noise interference and product size reduction on packaging substrate products. Taking the packaging substrate of FIG. 1 as an example, in the prior art, the circuit chip 140 is usually first embedded in the main body of the packaging substrate 100 (molding compound layer 150), and then the first wiring layer 120 as the circuit layout of the packaging substrate is fabricated. Most of the first wiring layer 120 is a thin circuit with a narrow width, and the manufacturing process is difficult, so that when the first wiring layer 120 has a manufacturing defect, the circuit chip 140 must also be scrapped. In addition, once the circuit chip 140 is embedded in the packaging substrate 100, the electrical connection between the circuit chip 140 and the external circuit will become difficult to handle, for example, additional laser opening, dielectric material layer lamination, etc. The processing process and the electrical connection circuit with complex structure will increase the manufacturing cost and reduce the product yield.

In contrast, the technology of the present invention, as described in the process steps of the above embodiment, is to complete the first wiring layer 120 as the circuit layout of the packaging substrate before the circuit chip 140 is embedded in the packaging substrate 100, and then the circuit chip 140 is bonded connected to the first wire layer 120 , and finally the mold compound layer 150 is injected into the mold to complete the package substrate 100 shown in FIG. 1 . Therefore, the thin circuit (the first wiring layer 120 ) with a narrower width and higher manufacturing process difficulty will be manufactured first, and the first wiring layer 120 can also include the electrical connection circuit between the circuit chip 140 and the external circuit and be fabricated at the same time. Complete or no additional processing; therefore, can reduce manufacturing costs and improve product yield.

According to the above-mentioned embodiments, the packaging substrate shown in FIG. 6 can be further developed into a product with higher-order functions. For example, FIG. 7A is a schematic cross-sectional view of a packaging substrate 200 according to a second embodiment of the present invention. After the process of the above-mentioned first embodiment proceeds to the step of FIG. 6 , the mold compound layer 150 can be removed from top to bottom to expose the upper surface of the circuit chip 140; for example, the mold compound layer 150 can be removed by grinding. The upper half of the circuit wafer 140 is used as the grinding stop point. Therefore, since the upper surface of the circuit chip 140 is exposed, it is beneficial to the heat dissipation effect of the circuit chip 140 . In another embodiment, a heat sink (Heat sink) 160 can be further arranged on the circuit chip 140, so that the heat sink 160 is connected to the circuit chip 140 to enhance the heat dissipation effect of the circuit chip 140, as shown in FIG. 7B shown. For example, the heat sink 160 is directly pasted on the upper surface of the circuit chip 140 by pasting.

In addition, since the carrier board 110 used in the above embodiments is a conductive substrate, no matter it is a whole metal substrate or a dielectric substrate with a conductive layer plated on the surface, the carrier board 110 can also be used to provide the The circuit chip 140 is used for heat dissipation, and it is reserved for the process after FIG. 6 . For example, FIGS. 8-10 are schematic cross-sectional views of the package substrate 300 corresponding to subsequent manufacturing steps according to the third embodiment of the present invention. When the above-mentioned first embodiment proceeds to the step of FIG. 6, if the carrier board 110 is intended to be used as a heat sink, the first wire layer 120 can be used as a heat sink for transferring the heat generated by the circuit chip 140 to the carrier board 110. path. In this embodiment, we can make the circuit layout layer of the package substrate separately on the molding compound layer 150; therefore, as shown in FIG. 8, a second wire layer 170 can be formed on the molding compound layer 150, so that The second wire layer 170 includes at least one second metal wire; for example, the second wire layer 170 has four second metal wires 171-174. The wire layer 120, but not limited thereto.

Next, as shown in FIG. 9, a conductive column layer 180 can be formed on the second wire layer 170, and the conductive column layer 180 includes at least one metal column; for example, the conductive column layer 180 has four metal columns 181 ˜184, which respectively correspond to the second metal wires 171-174.

Next, as shown in FIG. 10 , a dielectric material layer 190 is formed on the mold compound layer 150 such that the dielectric material layer 190 covers the second metal traces 171-174 on the mold compound layer 150 and the metal pillars 181-184. The manufacturing method and composition material of the dielectric material layer 190 can refer to the mold compound layer 150 as shown in the steps in Figure 6, but it is not limited thereto.

In addition, we can use the package substrate 100 in FIG. 1 as a basis for further applications according to different requirements or uses. For example, make solder balls (Solder ball) under the package substrate 100 to connect external circuits; overlay the package substrate 100 with Surface-Mount Technology (SMT) components or other circuit chips or Die: stack other packaging substrates above or below the packaging substrate 100 to form a multi-layer packaging substrate.

The above embodiments are only exemplary, and do not constitute any limitation to the scope of the present invention. Those skilled in the art should understand that the details and forms of the technical solutions of the present invention can be modified or replaced without departing from the spirit and scope of the present invention, but these modifications and replacements all fall within the protection scope of the present invention.

Claims (11)

1. a kind of package substrate, it is characterised in that include：

One conductor layer, includes an at least metal routing；

One conductive connecting elements, on the conductor layer；

One circuit chip, with least one external foot pad, and is arranged on the conductive connecting elements；With And

One conductive film, coats the conductor layer, the conductive connecting elements and the circuit chip；

Wherein, the conductive connecting elements to connect at least one external foot pad one of them with this extremely One of them of a few metal routing.

2. package substrate as claimed in claim 1, it is characterised in that the conductive connecting elements are a gold medal Belong to column.

3. package substrate as claimed in claim 1, it is characterised in that the conductive connecting elements are a weldering Tin projection thing.

4. package substrate as claimed in claim 1, it is characterised in that further include a fin, it sets It is placed on the circuit chip, and connects the circuit chip.

5. package substrate as claimed in claim 1, it is characterised in that further include a metal loading plate, It is arranged under the conductor layer.

6. a kind of preparation method of package substrate, it is characterised in that step is included：

(A) loading plate is provided；

(B) conductor layer No.1 is formed on the loading plate so that the conductor layer No.1 includes at least one First metal routing；

(C) conductive connecting elements are formed on the conductor layer No.1；

(D) set a circuit chip with least one external foot pad on the conductive connecting elements, make Obtain the conductive connecting elements connect at least one external foot pad one of them with this at least one One of them of first metal routing；And

(E) conductive film is formed on the circuit chip, and make it that the conductive film fills The space filled out between the circuit chip and the loading plate.

7. preparation method as claimed in claim 6, it is characterised in that the conductive connecting elements are one the One columnar metal thing.

8. preparation method as claimed in claim 6, it is characterised in that the conductive connecting elements are a weldering Tin projection thing.

9. preparation method as claimed in claim 6, it is characterised in that further include：

(F1) conductive film of part is removed, to expose the upper surface of the circuit chip；And

(F2) loading plate is removed.

10. preparation method as claimed in claim 9, it is characterised in that further include：

One fin is set on the circuit chip so that the fin connects the upper table of the circuit chip Face.

11. preparation method as claimed in claim 6, it is characterised in that further include：

(H1) one second conductor layer is formed on the conductive film so that second conductor layer is included At least one second metal routing；

(H2) conductive posts are formed on second conductor layer, the conductive posts include at least one second Columnar metal thing；And

(H3) dielectric materials layer is formed on the conductive film, and causes the dielectric materials layer bag Cover at least one second metal routings all on the conductive film with this at least 1 the Two columnar metal things.