CN103150988A - Display panel and driving method thereof - Google Patents

Abstract

The invention provides a display panel, which includes a first display part, a second display part and a data driver. The first display part includes a plurality of first scan lines and a plurality of first data lines, and the first scan lines are used to transmit a plurality of first scan signals sequentially. The second display part includes a plurality of second scan lines and a plurality of second data lines. The second scan lines are arranged in parallel with the first scan lines in the direction in which the first scan signals are transmitted, and when the first scan signals are transmitted sequentially, and then used to transmit a plurality of second scanning signals sequentially. The data driver includes a plurality of data output pins, wherein each of the data output pins is electrically connected to one of the first data lines and one of the second data lines.

Description

Display panel and driving method thereof

technical field

The invention relates to an electronic device, in particular to a display panel.

Background technique

Due to the development of display technology in recent years, display panels have been widely used in various electronic devices, such as computers, televisions, mobile phones, and the like.

A conventional display panel includes a data driver, a scan driver, data lines, scan lines, and a display portion. The data lines and the scan lines are arranged alternately to divide the display part into a plurality of pixels. When updating the picture, the scan driver sequentially sends scan signals to each scan line to sequentially turn on each row of pixels, and the data driver sequentially sends data signals to each row of pixels according to the turned on display area.

However, as the resolution of the display panel increases, the design of the data driver becomes more complicated, and the number of required data lines gradually increases. The complexity of the data driver will increase the difficulty in its implementation, and the increase in the number of data lines will increase the load of the data driver, which will delay the data signal and eventually lead to the deterioration of the display quality.

Therefore, above-mentioned problem has the necessity of urgent solution.

Contents of the invention

One aspect of the present invention is a display panel including a first display unit, a second display unit, and a data driver. The first display part includes a plurality of first scan lines and a plurality of first data lines. The first scan lines are used to sequentially transmit a plurality of first scan signals, and the first data lines and the first scan lines are arranged alternately. The second display unit is arranged in parallel with the first display unit. The second display part includes a plurality of second scan lines and a plurality of second data lines. The second scanning line is different from the first scanning line, and is arranged in parallel with the first scanning line in the direction in which the first scanning signal is transmitted, and is used to sequentially transmit a plurality of second scanning lines after the first scanning signal is transmitted sequentially Signal. The second data lines and the second scan lines are arranged alternately. The data driver includes a plurality of data output pins, wherein each of the data output pins is electrically connected to one of the first data lines and one of the second data lines.

Another aspect of the present invention is a driving method of a display panel, the driving method includes: providing a display panel, the display panel includes a first display part, a second display part and a data driver, the first display part includes a plurality of first Scanning lines and a plurality of first data lines, the first scanning lines and the first data lines are arranged alternately and used to transmit a plurality of first scanning signals, the second display part includes a plurality of second scanning lines and a plurality of second data lines, The second scanning line is different from the first scanning line and the second data line is arranged in a staggered manner. The second scanning line is arranged in parallel with the first scanning line in the direction in which the first scanning signal is transmitted. The data driver includes a plurality of data output pins, Each of the data output pins is electrically connected to one of the first data lines and one of the second data lines; the first scanning signal is sequentially transmitted to the first display part through the first scanning line; sequentially transmit a plurality of second scanning signals to the second display part; and output a plurality of data signals through the data output pin of the data driver, and transmit the data signals to the first display part and the second display part through the first and second data lines Display section.

Description of drawings

Fig. 1a is a schematic diagram of a display panel according to an embodiment of the present invention;

Fig. 1b is a timing diagram of the operation of the display panel in Fig. 1a;

Fig. 2a is a schematic diagram of a display panel according to an embodiment of the present invention;

Fig. 2b is a timing diagram of the operation of the display panel in Fig. 2a;

Fig. 2c is a schematic diagram of the multitasking circuit in Fig. 2a.

reference sign

100, 200: display panel 110: first display part

120: Second display unit 130: Data driver

140: first gate driver 150: second gate driver

260: Multitasking circuit S_1－S_n: Scanning line

S_n+1-S_2n: scan line D_1-D_m: data line

D_m+1-D_2m: data line pin_1-pin_m: output data pin

M11-M1m: the first switch M21-M2m: the second switch

SW1: The first control line SW2: The second control line

frame: picture period T1: first conduction period

T2: Second conduction period Td: Time delay

Ts1: pixel charging time Tp: preparation time

Detailed ways

The following will clearly illustrate the spirit of the disclosure with the accompanying drawings and detailed descriptions. Any person of ordinary skill in the art can change and modify the technology taught by the disclosure after understanding the preferred embodiments of the disclosure. , without departing from the spirit and scope of this disclosure.

As used herein, "connection" may refer to two or more elements in direct physical or electrical contact with each other, or indirect physical or electrical contact with each other, and "connection" may also refer to two or more elements Components operate or act on each other.

FIG. 1 a is a schematic diagram of a display panel 100 according to an embodiment of the present invention. The display panel 100 includes a first display part 110 , a second display part 120 , a data driver 130 , a first gate driver 140 and a second gate driver 150 . The first display portion 110 and the second display portion 120 may each include a plurality of pixels arranged in a matrix, and these pixels may display a picture according to the data signal output by the data driver 130, and the first display portion 110 and the second display portion 120 can be arranged side by side and display different parts of the same picture (for example: displaying the left half and right half of the same picture respectively).

The first display portion 110 may include a plurality of scan lines S_1 , S_2 , . . . , S_n and a plurality of data lines D_1 , D_2 , . . . , D_m. The data lines D_1 , D_2 , . . . , D_m are arranged alternately with the scan lines S_1 , S_2 , . . . , S_n.

The scan lines S_1, S_2, . The data signals output by 130 are sequentially written into each row of pixels of the first display portion 110 through the data lines D_1 , D_2 , . . . , D_m.

The second display portion 120 includes a plurality of scan lines S_n+1, S_n+2, . . . , S_2n and a plurality of data lines D_m+1, D_m+2, . . . , D_2m. The data lines D_m+1, D_m+2, . . . , D_2m and the scan lines S_n+1, S_n+2, . The scanning lines S_n+1, S_n+2, ..., S_2n are arranged in parallel with the scanning lines S_1, S_2, ..., S_n in the direction in which the first scanning signal is transmitted, that is, the scanning lines S_n+1 and the scanning lines S_1 are arranged in parallel. Arranged in the second display portion 120 , the scan line S_n+2 is arranged in parallel with the scan line S_2 in the second display portion 120 , and so on. The scan lines S_n+1, S_n+2, . . . , S_2n and the scan lines S_1, S_2, . . . , S_n are different from each other and not connected. In other words, the scan lines S_1 , S_2 , . . . , S_n and the scan lines S_n+1 , S_n+2 , .

The scan lines S_n+1, S_n+2, . The output data signal can be sequentially written into each row of pixels of the second display part 120 through the data lines D_m+1, D_m+2, ..., D_2m, and the switch in this embodiment is an example of a thin film transistor, but not This is the limit.

The data driver 130 includes a plurality of data output pins pin_1, pin_2, . . . , pin_m, wherein each of the data output pins pin_1, pin_2, . One of the data lines D_m+1, D_m+2, ..., D_2m; that is, the data output pin pin_1 can be connected to the data line D_1 and the data line D_m+1, and the data output pin pin_2 can be connected to the data line D_2 And data line D_m+2, and so on. In addition, the data driver 130 may be implemented as an integrated circuit in actual operation, but is not limited thereto.

Also refer to FIG. 1b, which is a timing diagram of the operation of the display panel 100 in FIG. 1a. As shown in FIG. 1a and FIG. 1b, the scan line S_1 can first transmit the first scan signal to the first row of pixels of the first display portion 110, so that the data signal output by the data driver 130 passes through the data lines D_1, D_2, . . . D_m is respectively written into the first row of pixels of the first display part 110, and then the scan line S_2 can transmit another first scan signal to the second row of pixels of the first display part 110, so that the data signal output by the data driver 130 Data lines D_1 , D_2 , . . . , D_m are respectively written into the pixels in the second row of the first display portion 110 , and so on. After the scan line S_n transmits the first scan signal to the last row of pixels of the first display part 110, the scan line S_n+1 can then transmit the second scan signal to the first row of pixels of the second display part 120, so that the data driver 130 The output data signals are respectively written into the first row of pixels of the second display part 110 through the data lines D_m+1, D_m+2, ..., D_2m, and then the scan line S_n+2 can transmit the second scan signal to the second display The second row of pixels of the second display part 120, so that the data signals output by the data driver 130 are respectively written into the second row of pixels of the second display part 120 through the data lines D_m+1, D_m+2, ..., D_2m, and so on .

It should be noted that, in the above operations, the data lines D_1, D_2, . . . , D_m and the data lines D_m+1, D_m+2, . The portion 110 and the second display portion 120 determine which row of pixels is written into the data signal according to the scanning signals transmitted by the scanning lines S_1, S_2, . . . , S_n and the scanning lines S_n+1, S_n+2, . Each row of pixels in the first display portion 110 can be sequentially written with a data signal during the first conduction period T1, and each row of pixels in the second display portion 120 can be sequentially written into data signals during the second conduction period T2. data signal.

Through the above-mentioned setting and operation, the output data pins pin_1, pin_2, . Complexity in design. In addition, through the arrangement of the first display portion 110 and the second display portion 120, the scan lines S_1, S_2, . . . , S_n and the scan lines S_n+1, S_n+2, . The display portion 110 and the second display portion 120, in this way, each row of pixels only needs to be provided with one scan line, so while reducing the total number of output data pins pin_1, pin_2, . . . , pin_m of the data driver 130, the display can be further improved. The aperture ratio of the pixels in the panel 100 , for example, compared with the pixel with a plurality of scan lines arranged on a single row of pixels, the single row of pixels in the display panel 100 has a better aperture ratio.

In addition, because the high frequency signal is easily affected by the capacitance, the voltage level of the signal is insufficient. Therefore, in some embodiments of the present invention, the duration of each scan signal may include a preparation time and a pixel charging time. Taking the scan signal of the scan line S_1 as an example, the preparation time may be Tp, and the pixel charging time may be Ts1. The preparation time Tp can allow sufficient time for the scan signal to transition (for example, charging from a low potential to a high potential or discharging a high potential to a low potential). In this way, the transistor in the pixel can have enough time to process data during the pixel charging time. write.

Furthermore, in some embodiments of the present invention, the scanning signals transmitted by the scanning lines S_1, S_2, ..., S_2n are respectively generated within a frame period (frame), and any two adjacent first scanning signals and any two adjacent first scanning signals Adjacent second scan signals have a time delay Td with each other. The so-called frame period here may be a period of updating a full frame, and in some cases, a frame period of the display panel 100 may be 1/60 second, that is, the full frame is updated 60 times per second. In addition, in some embodiments, the length of the above time delay Td may be equal to the pixel charging time Ts1 of the scan signal of the scan line S_1 .

In addition, in some embodiments of the present invention, the first gate driver 140 is disposed on one side of the first display portion 110, is electrically connected to the scan lines S_1, S_2, . . . , S_n, and is used to sequentially generate the first scan signals. . The second gate driver 150 is disposed on one side of the second display portion, electrically connected to the scan lines S_n+1, S_n+2, . . . , S_2n, and used for sequentially generating second scan signals. In some embodiments, the first gate driver 140 is electrically connected to the second gate driver 150, and used as a gate driver circuit, so that the second gate driver 150 can continue the first gate driver 140 to generate the first Two scan signals. In actual operation, the first gate driver 140 and the second gate driver 150 can be realized by a shift register circuit (shift register), but not limited thereto.

In view of the above, an embodiment of the present invention is a display panel provided with two display parts, wherein the scanning lines distributed on different display parts are arranged side by side and separated from each other, and there is no physical direct connection relationship, and the scanning signal They are transmitted to different display parts through scanning lines on different display parts respectively. Since the scan lines distributed on different display parts and parallel to each other can respectively turn on or turn off a part number (for example: half) of the pixels, such setting can effectively reduce the load of the separate scan lines. In addition, compared with the display panels using multitasking circuits, the display panels in some of the above embodiments do not have multitasking circuits, so there is no need to quickly switch the high-frequency signals of the multitasking circuits, and the charging of each row of pixels in the display panel The time is not reduced due to the fast switching of the multitasking circuit, so it can be manufactured in an amorphous silicon (a-si) manufacturing process with low electron mobility.

FIG. 2a is a schematic diagram of a display panel 200 according to an embodiment of the present invention. The display panel 200 includes a first display portion 110 , a second display portion 120 and a data driver 130 . The structures of the first display unit 110 , the second display unit 120 and the data driver 130 in the display panel 200 are substantially the same as the corresponding structures in the display panel 100 , so details will not be repeated here.

As shown in the figure, compared with the embodiment shown in FIG. 1a, the display panel 200 further includes a multitasking circuit 260, and the multitasking circuit 260 is electrically connected to the data output pins pin_1, pin_2, . . . , pin_m and The data lines D_1 , D_2 , . . . , D_2m are used for selectively conducting the data output pins pin_1 , pin_2 , . In actual operation, the multitasking circuit 260 can be realized by multiple switches.

Through the above-mentioned setting and operation, each output pin pin_1, pin_2, ..., pin_m of the data driver 130 can be connected to multiple data lines but only conduct with a single data line at the same time, which can greatly reduce the number of data output connections. The pins pin_1 , pin_2 , . . . , pin_m can also significantly reduce the load of the data driver 130 to ensure the picture quality of the display panel.

In one embodiment of the present invention, when the scan lines S_1, S_2, . , D_2, ..., D_m, when the second scan lines S_1, S_2, ..., S_n sequentially transmit the second scan signal, the multiplexing circuit 260 turns on the data output pins pin_1, pin2, ..., pin_m and the second data line D_m+1, D_m+2, ..., D_2m.

FIG. 2b is a timing diagram of the operation of the display panel 200 in FIG. 2a. As shown in FIG. 2a and FIG. 2b, the multitasking circuit 260 can connect the output pins pin_1, pin_2, . . . , pin_m of the data driver 130 to the data lines D_1, D_2, . D_m are respectively connected and simultaneously disconnected from the second data lines D_m+1, D_m+2, ..., D_2m, and the output pins pin_1, pin_2, ..., pin_m of the data driver 130 are connected to the data lines D_m during the second conduction period T2 +1, D_m+2, . . . , D_2m are respectively connected and simultaneously disconnected from the data lines D_1, D_2, . In this way, each row of pixels in the first display portion 110 and the second display portion 120 can be sequentially written with data signals.

FIG. 2c is a schematic diagram of the multiplexing circuit 260 in FIG. 2a. The multitasking circuit 260 may include a plurality of first switches M11, M12, . . . , M1m, and a plurality of second switches M21, M22, . . . , M2m. The first switches M11 , M12 , . . . , M1m are electrically connected between the data output pins pin_1 , pin_2 , . . . , pin_m and the data lines D_1 , D_2 , . The second switches M21 , M22 , . . . , M2m are electrically connected between the data output pins pin_1 , pin_2 , . . . , pin_m and the data lines D_m+1 , D_m+2 , . In some embodiments, the first switches M11, M12, . . . The second control line SW2 controls.

Referring again to FIG. 2b, in the first conduction period T1 in a frame period frame, the control signal transmitted by the first control line SW1 can turn on the first switches M11, M12, . . . , M1m to turn on the data output pin pin_1. , pin2, ..., pin_m and data lines D_1, D_2, ..., D_m. During the second conduction period T2 in a frame period, the control signal transmitted by the second control line SW2 can turn on the second switches M21, M22, . . . , M2m to turn on the data output pins pin_1, pin_2, . pin_m and data lines D_m+1, D_m+2, ..., D_2m. It should be noted that when the control signal transmitted by the first control line SW1 turns on the first switches M11, M12, ..., M1m, the control signal transmitted by the second control line SW2 can close the second switches M21, M22, ..., M2m, to disconnect the data output pins pin_1, pin_2, ..., pin_m and the data lines D_m+1, D_m+2, ..., D_2m, and vice versa, so as to avoid the simultaneous connection of the data output pins pin_1, pin_2, ...pin_m (or transmit data signals) to the data lines D_1 , D_2 , . . . , D_m and the data lines D_m+1 , D_m+2 , .

In view of the above, some embodiments of the present invention use the multi-tasking circuit to conduct only one data line at a time, so that the load of the data driver can be reduced. In addition, compared with conventional display panels using multi-tasking circuits, in some embodiments of the present invention, the control signals of the multi-tasking circuits roughly correspond to half a picture period, so the frequency of these control signals is lower and the power consumption Lower, and less likely to reduce the charging time of the pixel when switching.

Another aspect of the present invention is a method for driving a display panel. This driving method can be used to drive a display panel whose structure is the same as or similar to that of FIG. 1a or FIG. 2a. For the convenience of description, the following driving methods are described by taking the embodiments shown in FIGS. 1 a to 1 b and FIGS. 2 a to 2 c as examples, but are not limited to these illustrated embodiments.

It should be noted that, unless otherwise stated, the steps in the following driving method do not have a specific order. In addition, the following steps may also be executed at the same time, or may overlap in execution time.

In an embodiment of the present invention, the driving method includes the following steps: (a) providing a display panel 100, the display panel 100 includes a first display portion 110, a second display portion 120, and a data driver 130, and the first display portion 110 includes a plurality of The first scan lines S_1, S_2, ..., S_n and a plurality of first data lines D_1, D_2, ..., D_m, the first scan lines S_1, S_2, ..., S_n are interlaced with the first data lines D_1, D_2, ..., D_m Configured and used to transmit a plurality of first scan signals, the second display portion 110 includes a plurality of second scan lines S_n+1, S_n+2, ..., S_2n and a plurality of second data lines D_m+1, D_m+2, ... , D_2m, the second scan lines S_n+1, S_n+2, ..., S_2n are different from the first scan lines S_1, S_2, ..., S_n and interlaced with the second data lines D_m+1, D_m+2, ..., D_2m Configuration, the second scanning lines S_n+1, S_n+2, ..., S_2n are arranged in parallel with the first scanning lines S_1, S_2, ..., S_n in the direction of transmission of the first scanning signal, and the data driver 130 includes a plurality of data output interfaces Each of the data output pins pin_1, pin_, ..., pin_m is electrically connected to one of the first data lines D_1, D_2, ..., D_m and the second data lines D_m+1, D_m+2, ... , one of D_2m; (b) sequentially transmit the first scanning signal to the first display part 110 through the first scanning lines S_1, S_2, ..., S_n; (c) through the second scanning lines S_n+1, S_n+2, ..., S_2n sequentially transmit a plurality of second scan signals to the second display part 120; and (d) output a plurality of data signals through the data output pins pin_1, pin_2, ..., pin_m of the data driver 130, and pass through the first , the second data lines D_1 , D_2 , . . . , D_m transmit data signals to the first display portion 110 and the second display portion 120 .

Through the above-mentioned driving method, the output data pins pin_1, pin_2, . Complexity in design. In addition, only one scan line passes through each pixel, so while reducing the total number of output data pins pin_1 , pin_2 , .

In an embodiment of the present invention, the step of transmitting data signals through the first and second data lines D_1, D_2, ..., D_2m further includes: respectively passing through the first and second data lines D_1, D_2, ..., D_2m at different times The data signal is transmitted to the first display part 110 and the second display part 120 . In this way, the load of the data driver 130 on the first and second data lines D_1, D_2, . . . , D_2m can be reduced, so as to reduce the display time delay (RC delay).

In an embodiment of the present invention, the step of transmitting data signals through the first and second data lines D_1, D_2, ..., D_2m further includes: during the first conduction period T1 in a frame period frame, the first scanning line S_1 , S_2, ..., S_n sequentially transmit the first scan signal, and turn on the data output pin pin_1, pin_2, ..., pin_m and the first data line D_1, D_2, ..., D_2; and a first scan signal in the frame period During the second conduction period T2, the second scan lines S_n+1, S_n+2, ..., S_2n sequentially transmit the second scan signal, and turn on the data output pins pin_1, pin_2, ..., pin_m and the second data lines D_1, D_2, . . . , D_2, wherein the second conduction period T2 is different from the first conduction period T2.

In an embodiment of the present invention, any two adjacent first scanning signals and any two adjacent second scanning signals have a time delay (such as Td) with each other within the frame period frame.

In an embodiment of the present invention, the duration of each scanning signal may include a preparatory time, so that the scanning signal has sufficient time to transition, such as charging from a low potential to a high potential or discharging a high potential to a low potential.

In view of the above, by using the embodiments of the present invention, the number of data output pins of the data driver can be reduced by half, thereby greatly reducing the complexity of the data driver. In addition, using another embodiment of the present invention can avoid increasing the load of the data driver when reducing the data output pins of the data driver, thereby ensuring the picture quality of the display panel.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any skilled person who is familiar with the related art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the appended claims.

Claims (9)

1. a display panel, is characterized in that, comprising:

One first display part comprises:

Many the first sweep traces are in order to sequentially to transmit a plurality of the first sweep signals; And

Many the first data lines, interconnected with those first sweep traces;

One second display part configures side by side with this first display part, comprising:

Many the second sweep traces, different with those first sweep traces, configure side by side with those first sweep traces on the direction that those first sweep signals transmit, and those first sweep signals after sequentially transmitting in order to sequentially to transmit a plurality of the second sweep signals; And

Many the second data lines, interconnected with those second sweep traces; And

One data driver comprises a plurality of data output connecting pins, and wherein each in those data output connecting pins all is electrically connected one of those the first data lines with those the second data lines one.

2. display panel according to claim 1, is characterized in that, also comprises:

One multiplexing circuitry is electrically connected between those data output connecting pins and those first, second data lines of this data driver, in order to those data output connecting pins of conducting optionally and those first, second data lines one of them.

3. display panel according to claim 2, it is characterized in that, when those first sweep traces sequentially transmit those first sweep signals, this multiplexing circuitry is in order to those data output connecting pins of conducting and those first data lines, when those second sweep traces sequentially transmitted those second sweep signals, this multiplexing circuitry was in order to those data output connecting pins of conducting and those second data lines.

4. display panel according to claim 2, is characterized in that, this multiplexing circuitry also comprises:

A plurality of the first switches, be electrically connected at respectively those data output connecting pins and those the first data lines between, and in first conduction period of 1 in the period of picture in order to respectively those data output connecting pins of conducting and those first data lines; And

A plurality of second switches, be electrically connected at respectively those data output connecting pins and those the second data lines between, and in this second conduction period of 1 in period of picture in order to respectively those data output connecting pins of conducting and those second data lines, wherein this second conduction period is different from this first conduction period.

5. display panel according to claim 1, is characterized in that, also comprises:

One first grid driver is disposed at a side of this first display part, is electrically connected at those the first sweep traces, and in order to sequentially to produce those the first sweep signals; And

One second grid driver is disposed at a side of this second display part, is electrically connected at those the second sweep traces, and in order to sequentially to produce those the second sweep signals;

Wherein those first, second sweep signals produce in the period at a picture, and wantonly two adjacent those first sweep signals and wantonly two those adjacent second sweep signals have time delay mutually.

6. the driving method of a display panel, is characterized in that, comprising:

one display panel is provided, this display panel comprises one first display part, one second display part and a data driver, this first display part comprises many first sweep traces and many first data lines, those first sweep traces and those the first data lines are interconnected and in order to transmit a plurality of the first sweep signals, this second display part comprises many second sweep traces and many second data lines, those second sweep traces and those the first sweep traces are different and those second data lines are interconnected, those second sweep traces configure side by side with those first sweep traces on the direction that those first sweep signals transmit, this data driver comprises a plurality of data output connecting pins, each in those data output connecting pins all is electrically connected one of those the first data lines with those the second data lines one,

Sequentially transmit those first sweep signals to this first display part by those first sweep traces;

Sequentially transmit a plurality of the second sweep signals to this second display part by those second sweep traces; And

By a plurality of data-signals of those data output connecting pin outputs of this data driver, and transmit those data-signals to this first display part and this second display part by those first, second data lines.

7. driving method according to claim 6, is characterized in that, the step that transmits those data-signals by those first, second data lines also comprises:

Transmit those data-signals to this first display part and this second display part at different time by those first, second data lines respectively.

8. driving method according to claim 7, is characterized in that, the step that transmits those data-signals by those first, second data lines also comprises:

In first conduction period of 1 in the period of picture, those first sweep traces sequentially transmit those the first sweep signals, and those data output connecting pins of conducting and those first data lines; And

In this second conduction period of 1 in period of picture, those second sweep traces sequentially transmit those the second sweep signals, and those data output connecting pins of conducting and those second data lines, and wherein this second conduction period is different from this first conduction period.

9. driving method according to claim 8, is characterized in that, this picture in the period wantonly two adjacent those first sweep signals and wantonly two those adjacent second sweep signals mutually have the time and postpone.

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