CN103137202B - Memory and method for inducing hot carrier injection into selected memory cell of NAND gate series - Google Patents

Abstract

The present invention relates to a memory and a method for selecting a memory cell of a NAND gate series that induces hot carrier injection. The memory comprises a plurality of memory cells arranged in series in a semiconductor body, such as a NAND gate series, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The programming operation is based on controlling the carrier flow between a first semiconductor body region on the first side of the selected memory cell in the NAND gate series and a second semiconductor body region on the second side of the selected memory cell in the NAND gate series. A programming potential higher than the hot carrier injection barrier is applied to the selected memory cell, and then the drain-to-source voltage of the selected memory cell and the carrier flow in the selected memory cell reach a level sufficient to support hot carrier injection, which is controlled by a combination of a switching memory cell adjacent to the selected memory cell and a regulation of the source terminal voltage applied to the NAND gate series.

Description

Memory and Method for Selecting Memory Cells by Inducing Hot Carrier Injection NAND Gate Series

technical field

The present invention relates to a flash memory technology, in particular to a memory suitable for low-voltage programming and erasing operations in a NAND gate configuration and a selected memory cell that induces hot carrier injection into a series of NAND gates Methods.

Background technique

Flash memory is a type of non-volatile integrated circuit memory technology. Traditional flash memory uses floating gate memory cells. As the density of memory devices increases, the floating gate memory cells get closer together, and the interaction of charges stored in adjacent floating gates will cause problems, thus forming a limit, making the use of floating gate flash memory density Unable to raise. Another type of memory cell used in flash memory is called a charge-trapping memory cell, which uses a charge-trapping layer instead of a floating gate. Charge-trapping memory cells use charge-trapping materials, which do not cause mutual influence between individual memory cells like floating gates, and can be applied to high-density flash memories.

A typical charge storage memory cell comprises a field effect transistor (FET) structure comprising a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure comprising tunneling dielectric layer, charge storage layer (floating gate or dielectric layer), and barrier dielectric layer. Earlier conventional designs such as SONOS devices, in which the source, drain and channel are formed on a silicon substrate (S), the tunneling dielectric layer is formed of silicon oxide (O), and the charge storage layer is formed of silicon nitride ( N), the barrier dielectric layer is formed of silicon oxide (O), and the gate is polysilicon (S).

Flash memory devices are typically implemented using a NAND gate or a NOR gate (NOR) architecture, but other architectures are also possible, including an AND gate (AND) architecture. This NAND gate architecture is particularly favored for its high density and high speed in data storage applications. The NOR architecture is suitable for other applications such as programmable storage because random access is an important functional requirement. In a NAND architecture, the programming process typically relies on Fowler-Nordheim (FN) tunneling and requires high voltages, typically on the order of 20 volts, and high voltage transistors to handle them. This additional high-voltage transistor, along with the transistors used for logic and other data flow in the same integrated circuit, adds to the complexity of the process. This will increase the manufacturing cost of the device.

It can be seen that the above-mentioned existing memory device obviously still has inconveniences and defects in product structure, method and use, and needs to be further improved urgently. In order to solve the above-mentioned existing problems, relevant manufacturers have tried their best to find a solution, but no applicable design has been developed for a long time, and general products and methods do not have appropriate structures and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new memory and induce thermal carrier injection and a method of selecting memory cells in series with NAND gates, so that programming operations can be performed using low voltage in the NAND gate (NAND) architecture, and realize It is one of the current important research and development topics, and it has also become a goal that the industry needs to improve.

Contents of the invention

The purpose of the present invention is to overcome the defects of existing memory devices, and provide a new memory and a method for selecting memory cells induced by thermal carrier injection and NAND gate series. The technical problem to be solved is to use It can effectively reduce the programming voltage by using hot carrier injection, which is very suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. According to a memory proposed by the present invention, it includes: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, the word lines in the plurality of word lines and the corresponding plurality of memory cells and the control circuit is coupled to the plurality of bit lines, so as to be suitable for programming a selected memory cell among the plurality of memory cells corresponding to a selected word line by using the following steps: in a biasing one of the first and second sides of the plurality of memory cells to a drain terminal voltage during a programming interval, and biasing the other of the first and second sides to a source terminal voltage to control conductance during the programming interval ; Applying a drain end conduction voltage to a word line between the selected word line and one of the first and second sides during the programming interval; applying a source end conduction voltage to during the programming interval a word line between the selected word line and the other of the first and second sides; applying a programming voltage to the selected word line during the programming interval; and applying a programming voltage during the programming interval A switching voltage is applied to selected memory cells corresponding to the selected word line and selected memory cells adjacent to the selected word line.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the above-mentioned memory, wherein the conduction voltage of the source terminal changes during the programming interval, so that hot carrier injection occurs in the selected memory cell during a part of the programming interval to set the selected memory cell to a Programming critical class.

The aforementioned memory, wherein the step of biasing the other of the first and second sides to a source terminal voltage includes applying a rapidly decreasing voltage for a period of time during the programming interval.

The aforementioned memory also includes a first switching transistor (GSL) between a reference line and the first side of the plurality of memory cells, and a second switching transistor (SSL) between a first bit line and the first side of the plurality of memory cells. between the second sides of the plurality of memory cells, and wherein biasing the other of the first and second sides to a source terminal voltage includes setting the source terminal voltage to an initial level that is less than a threshold voltage, the threshold voltage is higher or lower than a gate voltage and a source terminal voltage applied to a corresponding one of the first and second switching transistors such that the corresponding switching transistor remains off for an initial portion of the programming interval, and rapidly reducing the source terminal voltage from the initial stage to one or more stages exceeding the threshold voltage less than the gate voltage during a subsequent portion of the programming interval such that the corresponding switching transistor is turned on during the programming interval .

The aforementioned memory, wherein the plurality of memory cells are arranged in a series of NAND gates.

The aforementioned memory also includes a first switching transistor (GSL) between a reference line and the first side of the plurality of memory cells, and a second switching transistor (SSL) between a first bit line and the first side of the plurality of memory cells. between the second sides of the plurality of memory cells, and wherein the control circuit turns on the first switching transistor during the programming interval and turns on the second switching transistor after an initial portion of the programming interval.

The aforementioned memory further includes a plurality of second memory cells coupled to the plurality of word lines, and wherein the control circuit applies the source terminal voltage to the second memory cells of the plurality of memory cells via the first bit line. side, apply the drain terminal voltage to the first side of the plurality of memory cells via the reference line, and apply a voltage equal to or close to ground via the second bit line at least during the initial portion of the programming interval A voltage is applied to the second sides of the plurality of second memory cells to suppress hot carrier injection.

The aforementioned memory further includes a plurality of second memory cells coupled to the plurality of word lines, and wherein the control circuit applies the source terminal voltage to the second memory cells of the plurality of memory cells via the first bit line. side, apply the drain terminal voltage to the first side of the plurality of memory cells through the reference line, and apply a voltage that is the same as or close to the drain terminal voltage to the plurality of second memory cells through the second bit line the second side to suppress hot carrier injection.

The aforementioned memory also includes: a first switching transistor (GSL) between a reference line and the first side of the plurality of memory cells, and a second switching transistor (SSL) on a first bit line Between the second side of the plurality of memory cells; and a plurality of second memory cells coupled to the plurality of word lines, a corresponding first switching transistor between the reference line and the plurality of second memory cells between a first side of a second memory cell, and a corresponding second switching transistor between a second bit line and a second side of the plurality of second memory cells; wherein the bias voltage is the first and second sides The other to a source terminal voltage includes setting the source terminal voltage to an initial stage that is less than a threshold voltage that is higher or lower than the gate applied to a corresponding one of the first and second switching transistors voltage such that the corresponding switching transistor remains off during an initial portion of the programming interval, and the source terminal voltage rapidly decreases from the initial stage to a value exceeding the value less than the gate voltage during a subsequent portion of the programming interval. The threshold voltage of the voltage makes the corresponding switching transistor turn on in the programming interval; and wherein the control circuit applies a voltage that is the same as or close to the initial stage to the plurality of second bit lines through the second bit line during the programming interval The second side of the memory cell is used to suppress hot carrier injection.

The aforementioned memory further includes a plurality of second memory cells coupled to the plurality of word lines and a second bit line, and wherein the control circuit suppresses hot carrier injection of the plurality of second memory cells.

The aforementioned memory, wherein the plurality of memory cells are arranged into a common source NAND gate flash memory array.

The aforementioned memory, wherein the plurality of memory cells are arranged as a virtual grounded NAND flash memory array.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A kind of memory proposed according to the present invention, it comprises: a series of NAND gates, it comprises a plurality of memory cells arranged in series in a semiconductor main body; Lines are coupled to the corresponding memory cells of the plurality of memory cells; and the control circuit is coupled to the plurality of word lines, so as to be suitable for using the following steps to control the memory cells of the plurality of memory cells corresponding to a selected word line A selected memory cell is programmed: by applying a switching voltage to a word line adjacent to the selected word line to control the conductance of the series of NAND gates to induce an equivalent source in the series of NAND gates In a first semiconductor body region on one side of a selected memory cell, and the induced equivalent drain is in a second semiconductor body region on the other side of the selected memory cell of the NAND series; in a floating the first semiconductor body region during an initial portion of the programming interval, and biasing the first semiconductor body region to a source terminal voltage during a subsequent portion of the programming interval; biasing the second semiconductor body region to a a drain terminal voltage; and applying a programming potential greater than a hot carrier injection barrier level to the selected memory cell during the programming interval.

The purpose of the present invention and its technical problems are solved by adopting the following technical solutions in addition. A method for inducing hot carrier injection into a selected memory cell in a NAND gate series of a NAND gate array according to the present invention includes the following steps: by applying a switching voltage to the selected word line An adjacent word line controls the conductance of the NAND series to induce an equivalent source in a first semiconductor body region on one side of a selected memory cell of the NAND series, and induces an equivalent The drain is in a second semiconductor body region on the other side of the selected memory cell of the NAND series; floating the first semiconductor body region during an initial portion of a programming interval, and during the programming interval and biasing the first semiconductor body region to a source terminal voltage; biasing the second semiconductor body region to a drain terminal voltage; and applying a hot carrier injection barrier greater than a hot carrier injection barrier during the programming interval The programming potential of the class is applied to the selected memory cell.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned method of inducing hot carrier injection into a selected memory cell in a NAND gate series of a NAND gate array, wherein the NAND gate series in the NAND gate array includes a first switching transistor in between a bit line or reference line and a first side of the NAND series, and a second switching transistor between the bit line or reference line and a second side of the NAND series , and wherein: biasing the second semiconductor body region to a drain terminal voltage includes turning on the first switching transistor in the series of NAND gates, including the selected memory cell, and applying the drain terminal voltage via the first switching transistor to the first side of the NAND series; floating the first semiconductor body region includes keeping the second switching transistor off by setting the corresponding bit line or reference line to an initial voltage and setting the second switching transistor to a gate voltage such that the second switching transistor is off during the initial portion of the programming interval; and biasing the first semiconductor body region includes applying a reduced voltage to the corresponding bit line or reference line such that the second switching transistor is turned on during the subsequent portion of the programming interval.

The aforementioned method of inducing hot carrier injection into a selected memory cell in a NAND series of a NAND array includes suppressing hot carrier injection in at least one unselected NAND series.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. A kind of memory proposed according to the present invention, it comprises: a series of NAND gates, it comprises a plurality of memory cells arranged in series in a semiconductor main body; The lines are coupled to the corresponding memory cells of the plurality of memory cells; and the control circuit is coupled to the plurality of word lines, so as to be suitable for using the following steps to control the memory cells of the plurality of memory cells corresponding to a selected word line Programming a selected memory cell: blocking carriers on a first semiconductor body region on a first side of a selected memory cell of the NAND series and a second side of the selected memory cell of the NAND series flow between a second semiconductor body region on the side; boost the first semiconductor body region to a boosted voltage level by capacitive coupling; bias the second semiconductor body region to a drain terminal voltage level; apply a programming potential greater than a hot carrier injection barrier level to the selected memory cell; and enabling carrier flow from the second semiconductor body region by coupling the second semiconductor body region to a source terminal voltage to the selected memory cell to cause hot carrier generation.

The purpose of the present invention and the solution to its technical problems are also achieved by the following technical solutions. A method for inducing thermal carrier injection into a selected memory cell in a NAND series of a NAND gate array according to the present invention comprises the following steps: blocking carriers in a selection of the NAND series Flow between a first semiconductor body region on a first side of a memory cell and a second semiconductor body region on a second side of the selected memory cell of the NAND series; during an initial portion of a programming interval boosting the first semiconductor body region to a boosted voltage level by capacitive coupling; biasing the second semiconductor body region to a drain terminal voltage level; applying a hot carrier injection greater than one during the programming interval programming potential of the disabled level to the selected memory cell; and enabling carriers to flow from the second semiconductor body by coupling the second semiconductor body region to a source terminal voltage during a subsequent portion of a programming interval Region flows to the selected memory cell to cause hot carrier generation.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned method of inducing hot carrier injection into a selected memory cell in a NAND gate series of a NAND gate array includes applying a switching voltage to a selected memory cell in the NAND series adjacent to the selected memory cell. memory cells.

The aforementioned method of inducing hot carrier injection into a selected memory cell in a NAND gate series of a NAND gate array, wherein the NAND gate series in the NAND gate array includes a first switching switch at between a bit line or reference line and a first side of the series of NAND gates, and a second switch between the bit line or reference line and a second side of the series of NAND gates , and wherein the voltage boosting includes: turning on the first switching switch in the NAND series, including isolating the selected memory cell from the first semiconductor body region, and applying a turn-on voltage to the NAND series The word line coupled to the first side of the selected memory cell, and turning on the second switch includes applying the drain terminal voltage to the second semiconductor body region through the second switch; and wherein the enabling It includes turning on the first switch.

In the aforementioned method of inducing hot carrier injection into a selected memory cell in a NAND gate series of a NAND gate array, wherein the first switching switch includes a switching transistor, and includes applying a gate voltage to the switching and setting the source terminal voltage to an initial stage which is less than a threshold voltage which is higher or lower than the gate voltage applied to the switching transistor body such that the corresponding switching transistor is in the programming interval remains off for an initial portion of the programming interval, and rapidly reduces the source terminal voltage from the initial stage to a threshold voltage that exceeds the threshold voltage less than the gate voltage during a subsequent portion of the programming interval.

The aforementioned method of inducing hot carrier injection into a selected memory cell in a NAND series of a NAND array includes suppressing hot carrier injection in at least one unselected NAND series.

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from above technical scheme, main technical contents of the present invention are as follows:

To achieve the above object, the present invention provides a memory device configured for low-voltage operation, which includes a plurality of memory cells arranged in series in a semiconductor body, such as a NAND series that can be applied to a NAND array , there are a plurality of word lines coupled with corresponding memory cells. control circuitry coupled to the plurality of bit lines and the semiconductor body adapted to program a selected memory cell by injection of hot carriers onto a target memory cell using controlled word line voltages , referred to here as the switching voltage V-SWL. A source terminal voltage is applied to one side of the string, which is a common ground or other specific voltage as the source terminal voltage. The side where the source terminal voltage is applied to the selected memory cell during programming is called "equivalent source terminal" or "equivalent source terminal" herein. A drain-source terminal voltage V _D is applied to the other side of the series, which is a supply potential commonly referred to in the industry as VDD or VCC, or other specific voltages as the drain terminal voltage. The side where the drain terminal voltage is applied to the selected memory cell during programming is called "equivalent drain terminal" or "equivalent drain terminal" herein. To control the conductance of the switched memory cell, V-SWL is set to a bias condition during a portion of the programming interval to establish a condition in the body adjacent to the target cell to support sufficient thermoelectric field (drain-to-source voltage) and sufficient channel An electric current is applied to the target memory cell, wherein a programming voltage is applied to the target memory cell to induce hot carrier injection. Hot carrier injection using this procedure can be implemented using a control circuit, which implements a programming voltage to the selected word line (corresponding to the target memory cell) during the programming interval, and applies a switching voltage V-SWL to the selected word The adjacent word lines on the equivalent source side of the line apply the turn-on voltage to the other word lines.

During the programming interval, the selected word line is biased with a programming voltage sufficient to overcome the channel hot carrier barrier level. However, this programming voltage can be much smaller than that required for typical FN programming. Word lines corresponding to a plurality of memory cells receive a turn-on voltage which is lower than the programming voltage to suppress interference from other memory cells. The switching voltage in the programming interval is also similarly lower than the programming voltage to suppress the interference of the switching memory cells.

For a NAND series embodiment, a first switch (ground select switch or bottom bit line switch) is provided at a first end of the plurality of transistors, and a second switch (tandem select switch) switches (or top bit line toggle switches) are provided at a second terminal of the plurality of transistors. In this embodiment, the control circuit operates to turn on one of the first and second toggle switches at the drain terminal during the programming interval and to turn off the source terminal for an initial portion of the programming interval when the boosting of the source terminal occurs. The other of the first and second switches is then turned on at the source end of the switch to enable current to flow in the semiconductor body. A gate voltage is received via a toggle switch at the source end of a select line (eg, string select line SSL or ground select line GSL), and the bit line or reference line connected to the toggle switch is initially set to a voltage less than the threshold voltage such that the The switch remains closed, the threshold voltage is above or below the gate voltage, and then the voltage on the bit line or reference line is rapidly reduced beyond the threshold voltage below the gate voltage to a source terminal potential to enable current flow.

A selection line parallel to the plurality of word lines (eg, a string selection line SSL or a ground selection line GSL) may be coupled to the first and second switches. When the selected memory cell is adjacent to one of these selection lines, then the switching voltage V-SWL can be applied to the switch instead of the memory cell. Alternatively, a dummy word line can be added to the string that operates to receive V-SWL to program the first or last cell in the string of NAND gates.

A plurality of second memory cells coupled to the same plurality of word lines, such as a parallel series of NAND gates on an unselected bit line, the control circuit is operable to suppress or prevent Hot carrier injection.

In addition, in order to achieve the above object, the present invention also provides a method for inducing hot carrier injection of a selected memory cell in the NAND series of a NAND gate array for programming, which is based on the use of V-SWL adjacent The memory cell is selected to cause the flow of carriers and thermoelectric field. A programming potential above the hot carrier injection barrier level is applied to the selected memory cell, and then a drain-to-source voltage is passed through the selected memory cell and carriers in the selected memory cell flow to a level sufficient to support the hot carrier Injected classes.

Furthermore, in order to achieve the above object, the present invention provides a method for inducing thermal carrier injection into a selected memory cell in a NAND gate series of a NAND gate array, so as to block the carrier in the memory cell. flowing between a first semiconductor body region on a first side of a selected memory cell of the NAND series and a second semiconductor body region on a second side of the selected memory cell of the NAND series; Boosting the first semiconductor body region to a boosted voltage level by capacitive coupling during an initial portion of a programming interval; and biasing the second semiconductor body region to a drain terminal voltage level. applying a programming potential greater than a hot carrier injection barrier level to the selected memory cell during the programming interval; then during a subsequent portion of a programming interval by connecting the second semiconductor body region to a source terminal voltage coupling, enabling carrier flow from the second semiconductor body region to the selected memory cell to cause hot carrier generation.

By virtue of the above-mentioned technical solution, the memory and the method of selecting memory cells for inducing hot carrier injection into NAND gate series of the present invention have at least the following advantages and beneficial effects: an innovative programming mechanism described in the present invention can use hot-carrier sub-injection to effectively lower the programming voltage. Furthermore, this technique is not sensitive to the coupling ratio (GCR) of the memory cell gate. Therefore, it can solve the problem of low gate coupling ratio (GCR) caused by the continuous shrinking size and increasing density of memory cells. In addition, relatively low word line voltages can be used, so that interference from unselected memory packets can be suppressed. Furthermore, the process can also be simplified in some embodiments because the high voltage required for conventional FN operation can be eliminated or used in less stringent applications.

To sum up, the present invention relates to a memory and a method for selecting memory cells induced by hot carrier injection into a series of NAND gates. The memory includes a plurality of memory cells arranged in series in a semiconductor body, such as a series of NAND gates, and has a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The programming operation is based on controlling a first semiconductor body region between a first side of the selected memory cell in the NAND series and a second semiconductor body region on the second side of the selected memory cell in the NAND series. Carrier flow in the semiconductor body region. applying a programming potential higher than the hot carrier injection barrier to the selected memory cell, and then reaching a level sufficient to support hot carrier injection through the drain-to-source voltage of the selected memory cell and carrier flow in the selected memory cell The stage is controlled by a combination of switching cells adjacent to the selected cell and regulation of the voltage applied to the source terminal of the NAND gate train. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited, and in conjunction with the accompanying drawings, the detailed description is as follows.

Description of drawings

1A and 1B are schematic cross-sectional views showing a series of selected NAND gates and a series of non-selected NAND gates of a conventional FN tunneling programming technique.

Fig. 2 is a schematic cross-sectional diagram showing a selected NAND gate (NAND) series and its channel current and programming bias relationship diagram, which shows the use of existing conventional technology in the NAND gate (NAND) series. Problems Encountered in Inducing Hot Carrier Injection Programming.

Fig. 3 is a schematic cross-sectional view showing a selected NAND gate series and the relationship between channel current and programming bias voltage, which shows the induction of thermal carriers in a NAND gate series described in the present invention injected programming bias conditions.

4 is a layout diagram showing a common-source type NAND-type memory array operating using the programming bias described in the present invention, with a first bias condition to suppress disturbance.

FIG. 5 is a timing diagram showing an example of bit line and word line bias voltages during the hot carrier injection programming operation described in the present invention.

6 is a layout diagram showing a common source type NAND type memory array operating using the programming bias described in the present invention, with a second bias condition to suppress disturbance.

7 is a layout diagram showing a common source type NAND type memory array operating using the programming bias described in this invention, with a third bias condition to suppress disturbance.

8 is a schematic diagram showing a simplified layout of an array of NAND gates with dummy word lines adjacent to both ends of the series of NAND gates.

FIG. 9 is a schematic diagram showing a programming operation of a virtual grounded NAND memory array using the programming bias conditions described in the present invention.

FIG. 10 is a schematic block diagram showing an integrated circuit using memory cells and bias circuits according to embodiments of the present invention.

7, 8: Gate dielectric layer

9: Charge trapping structure

10: Semiconductor body

11, 19: contact

12-18: nodes

21: Ground selection line GSL

22~27: character line

28: Serial selection line SSL

30, 105: common source line CS

31: bit line

32: No bit line selected

33, 35: The semiconductor body region associated with the NAND series

100, 300: target memory cell

113, 304: switch memory cells

42: First toggle switch

43: Second toggle switch

50: Equivalent source area

51: Equivalent drain area

52: Passage area

101, 102, 103, 104, 201～207: series of NAND gates

105: common source line CS

111: Ground selection transistor

112: String selection transistor

301: first switching transistor

302: second switching transistor

310, 314, 315: regions in the semiconductor body

312: Equivalent source area

313: Equivalent drain area

500~503: source/drain series

810: integrated circuit

812: NAND gate flash memory (eg 3D)

814: Word Line/Serial Select and Ground Select Decoders and Drivers

816: character line

818: Bitline Decoder

819: Common Source Line Decoder

820: bit line

822, 826: bus

824: Sense Amplifier/Data Input Structure

830: other circuits

834: (Hot carrier injection programming and FN erasing) controller

836: Bias adjustment supply voltage

828: data input line

832: data output line

detailed description

In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the selection of memory and induced hot carrier injection NAND gate series proposed according to the present invention will be made below in conjunction with the accompanying drawings and preferred embodiments. The specific implementation, structure, method, steps, features and effects of the memory cell method are described in detail below.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of specific implementation methods, it should be possible to obtain a deeper and more specific understanding of the technical means and effects of the present invention to achieve the intended purpose. However, the attached drawings are only for reference and description, not for The invention is limited.

1A and FIG. 1B are schematic cross-sectional views showing a series of selected NAND gates (NAND) and a series of non-selected NAND gates of a conventional FN tunneling programming technique, in which multiple dielectrics are shown. Charge-trapping flash memory cells are arranged in series to form a series of NAND gates and a bias voltage for FN tunneling programming. FIG. 1A shows the bias voltages of a NAND series including target cells on a selected bit line, and FIG. 1B shows the bias voltages of a NAND series on unselected bit lines. Techniques for implementing NAND flash memory using energy gap engineering SONOS charge trapping technology are described in US Patent No. 7,315,474 to Lue, which is incorporated herein by reference. NAND cascades can be implemented using many different configurations, including FinFET technology, shallow trench isolation technology, vertical NAND technology, and more. For some examples of vertical NAND gate structures, see European Patent No. EP 2048709 by Kim et al. entitled "Non-volatile memory device, method of operating same and method of fabricating the same". Another similar structure is used in floating gate memory cells, using a conductive floating gate.

Please refer to FIG. 1A , the memory cell is shown formed on a semiconductor body 10 . For n-channel memory cells, semiconductor body 10 may be an isolated p-well located in a deep n-well region of a semiconductor wafer. Alternatively, the semiconductor body 10 may be isolated by a dielectric layer or other materials. In some embodiments p-channel memory cells may also be used, where the doping material of the semiconductor body is n-type.

A plurality of flash memory cells can be arranged in series along a bit line direction perpendicular to the word line direction. The word lines 22-27 extend through a series of parallel NAND gates. Nodes 12-18 are n-type regions in the semiconductor body (for n-channel devices) and serve as source/drain regions for memory cells. A first switch formed by metal-oxide-semiconductor transistors has a gate in the ground select line GSL 21, which is connected to the corresponding memory cell with the first word line 22 and formed by the n-type region in the semiconductor body 10. between one of the contacts 11 . This contact point 11 is connected to the common source line CS30. A second switch formed by a metal-oxide-semiconductor transistor has a gate in the string select line SSL 28, which is connected to the corresponding memory cell with the last word line 27 and formed by the n-type region in the semiconductor body 10. Between one joint 19 . This contact 19 is connected to the bit line BL31. The first and second switches in this exemplary embodiment are metal-oxide-semiconductor transistors, and in this example have gate dielectric layers 7 and 8 of silicon dioxide.

In this illustration, there are six memory cells in the string for simplicity. In a typical structure, a series of NAND gates can contain 16, 32 or more memory cells arranged in series. The word lines 22 - 27 corresponding to these memory cells have charge trapping structures 9 between the word lines and the channel region in the semiconductor body 10 . The charge trapping structures 9 in the memory cell may be dielectric charge trapping structures, floating gate charge trapping structures, or other suitable flash memory structures for programming using the techniques described herein. Furthermore, in an embodiment of the NAND flash structure a structure without junctions has been developed wherein nodes 13-17, and optionally nodes 12 and 18, can be omitted from this structure.

FIG. 1A shows a cross-sectional view of a prior art NAND architecture flash memory that induces FN tunneling to program memory cells corresponding to word lines 24 (target memory cells). A schematic diagram of the bias voltage. According to the bias shown here, the ground select line GSL is biased to about 0V and the common source line is grounded, so that the first switch corresponding to the ground select line GSL 21 is closed and the string select line SSL is biased to To about VCC and the selected bit line is also grounded, so that the second toggle switch corresponding to the string select line SSL 28 is on. Under these conditions, the semiconductor body in the region 33 associated with the NAND series is precharged to about 0V. The select word line 24 is biased to a high voltage programmable level V-PGM, which may be on the order of 20 volts in some embodiments. The unselected word lines 22, 23, 25-27 are biased to a turn-on voltage V-PASS, which is less than V-PGM by a voltage that inhibits programming of unselected cells in the string. As a result, electrons tunnel into the charge-trapping structures of selected memory cells.

FIG. 1B shows a cross-sectional view of a conventional NAND gate (NAND) architecture flash memory, which is an unselected bit line of the NAND gate series sharing word lines 22-27 in FIG. 1A A schematic diagram of the bias voltage. It can be seen from the figure that the ground select line GSL and the string select line SSL of all the word lines have the same bias voltage as shown in FIG. 1A . Similarly, the common source line 30 is also grounded. However, the unselected bit lines are biased to about the level of VCC. This closes the second toggle switch, which corresponds to the string select line SSL, and decouples the semiconductor body in region 35 from the unselected bit line BL 32 . As a result, the semiconductor body in region 35 is self-boosted by capacitive coupling from voltages applied to wordlines 22-27, which prevents charge trapping structures in memory cells sufficient to disturb unselected NAND gate trains. electric field formation. So-called Incremental Step Pulse Programming (ISSP) operation based on capacitive self-boosting is well known in the art.

FIG. 2 is a schematic cross-sectional view showing a series of selective NAND gates (NAND) and the relationship between channel current and programming bias voltage, which is a hot carrier injection programming using the prior art.

In FIG. 2, common source line CS 30 is grounded, and selected bit line 31 is also coupled to _VD . The ground select line GSL 21 is coupled to a pass voltage to turn on the first toggle switch 42 , coupling the semiconductor body to the common source line CS 30 . The string select line SSL 28 is biased to a second toggle switch 43 that is turned on by a voltage and couples the semiconductor body to the selected bit line 31, which is either _VD or the bit line programming bias coupling. The word line corresponding to the target memory cell 40 receives the programming pulse V-PGM. As a result of this programming bias, a channel current IPGM flows in the semiconductor bodies in this string, which is represented by trace 55 when fully turned on. In addition, the drain-to-source voltage across the target cell (interval 56) is small, and the voltage drop distribution along the series is from _VD to ground, ie trace 57 shown in the V _-channel diagram. As a result, the heating electric field corresponding to the drain-to-source voltage of the target memory cell in the programming interval is very small, so even if the channel current in this mode of operation is high enough, the sum of its hot carrier injection It is slow and inefficient. Therefore, hot carrier injection does not reach a critical level for NAND programming.

Figure 3 is a schematic cross-sectional view showing a selection of NAND gates (NAND) series and its relationship between channel current and programming bias, which shows the thermal load induced in a NAND series of the present invention described herein programming bias conditions for sub-implantation. It must be noted that for n-channel embodiments, this hot carrier includes electrons. For p-channel embodiments, similar biasing techniques can be applied to induce hot hole injection, where the hot carriers include holes. The embodiment described here is an n-channel, but alternative p-channel embodiments may also be referred to as hot carrier injection.

The word line coupled to the memory cell 41 adjacent to the end of the common source line CS 30 of the target memory cell 40 receives a two-stage switching voltage V-SWL arranged to cause sufficient hot carrier generation during a portion of the programming interval. Injection conditions. Under the bias conditions of a programming interval, region 51 in semiconductor body 10 is precharged by raising the common source voltage V _CS to a drain voltage V _D in response to the target word line between receiving V-PGM The turn-on voltage V-PASS (drain terminal) of all word lines between the switch 42 and the first switch 42 . The region 50 in the semiconductor body 10 is biased by capacitive self-boosting and closing the second toggle switch 43 during an initial part of the programming interval, and then via the bit line during a subsequent part of the programming interval. 31 apply a source terminal voltage and turn on the second switching switch. In this example, the bias voltage applied to the drain terminal during an initial part and a subsequent part of the programming interval is obtained by setting the gate voltage of the second switch to V _CC during the programming interval, and applying a variable voltage to Bit line 31 is achieved. Swinging the voltage in this embodiment includes setting the bit line 31 voltage to about V _CC or other voltage level less than the threshold voltage V _CC of switching transistor 43, or higher than V CC for an initial portion of the programming interval. V _CC , during which the second switching transistor 43 is turned off and the region 50 in the semiconductor body 10 is boosted due to the turn-on voltage V-PASS being applied to the drain terminal of the memory cell. Therefore, during the subsequent part of this programming interval, the bit line 31 voltage is lowered to the equivalent source voltage V _S , such as ground, which is lower than V _D , which turns on the second switching transistor 43 and the voltage V-PASS (source terminal) is coupled to the word line between the target memory cell 40 and the second switch 43 . The V-PASS (source terminal) can be the same voltage as V-PASS (drain terminal), or a different voltage, as required by a particular application or programming condition. In addition, the turn-on voltage V-PASS can vary according to the position on the string.

FIG. 3 also shows a schematic diagram showing the relationship between the voltage level and the position along the string during the programming interval. In this example, the voltage level of the equivalent drain region 51 between the first switching contact window 11 and the target memory cell 40 in this programming interval is determined by passing through the terminal of the common source line CS 30 The voltage V _CS applied by the first switch is set to be about V _D . In this example, due to the capacitive boost, in the initial part of the programming interval (which may be referred to as approximately to the left of line 65 in FIG. 3 ) between the contact window 19 of the second switching transistor 43 and the switching memory The voltage level of equivalent source region 50 between cells 41 has the voltage level represented by trace 63A. Because the second switch is closed and the voltage across the substring fluctuates very little, very little or no current flows during the initial portion of the programming interval. As a result of the drop in voltage applied to bit line 31 and the opening of the second switch, the equivalent source region 50 in the subsequent portion of this programming interval (which may be referred to as approximately to the right of line 65 in FIG. 3 ) A voltage level, having a voltage level represented by trace 63B. During the subsequent part of this programming interval, a relatively large voltage drop passes through the channel region 52 beneath the switching memory cell 41 . The current in the semiconductor body is increased to a programming current level sufficient to effectively support hot carrier injection, the level represented by trace 62 being between fully open channel current level 61 and fully closed channel current level 60 . In addition, by switching the voltage drop of the channel region 52 of the memory cell 41, as shown in the V _channel of the region 64 in the figure, most of the voltage drop between the programmed bit line voltage and the common source line voltage is absorbed, and in A thermoelectric field is generated near the target memory cell 40, which supports hot carrier injection.

In this example, as with all of the example NAND series shown here, the first and second switching switches (such as switching transistors 42, 43) are implemented using field effect transistors in series with the memory cells in the series . Of course, other switching circuits can also be used as needed. In the example shown in FIG. 3, the gate dielectric layer of the field effect transistor is a single-layer structure, and generally includes silicon oxide or nitrogen-doped silicon oxide. In other embodiments, field effect transistors switching switches (eg, 42, 43) in a string as shown in the figure may use multiple gate dielectric layers, including all charge trapping structures used in the string same gate dielectric. This solution can simplify the process of the memory cell. In such an embodiment, the first and second switches may be characterized as "memory cells". If necessary, the channel length of the field effect transistor used as the switch can be longer than the channel length of the memory cell. Because, compared to Fowler-Nordheim (FN) tunneling, with the relatively low operating voltage of the techniques described herein, disturbance of memory cells in the array can be suppressed when programming a target memory cell. In addition, because the word line voltage using this programming method is also lower than that of traditional NAND flash memory devices using Fowler-Nordham (FN) tunneling-based memory devices, through the tunnel oxide layer The vertical electric field is also small. For this reason, there is no need to use a high voltage driver, and the reliability becomes better. In addition, with the floating gate device, even if the memory cell has a lower gate coupling ratio due to device scaling, the programming speed will not be greatly reduced due to such a low gate coupling ratio. At the same time, the process can be simplified by omitting very high voltage devices as a result of using low voltage devices.

One method of inducing thermal carrier injection into a target memory cell during operation is by applying a switched word line voltage to control switching of the cell conductance at the source terminal of the target cell. The conductance is controlled enough to turn off the current in the switching memory cell so that the series of NAND gates can be separated into two regions, including an equivalent source region and an equivalent drain region. The voltage drop in the equivalent source region and the equivalent drain region is very small. As a result, most of the applied bit line voltage passes through this switching cell. In addition, the conductance is sufficient to turn on the small but sufficient current to flow through the switching cell and the target cell, where carriers are heated and injected into the charge trapping structure of the target cell.

During the programming interval when current needs to be enabled on the string, the voltage on the selected bit line and the common source line should be high enough to induce hot carriers in the target memory cell to heat the electric field. The voltage applied to the ground select line and the string select line should be high enough to fully turn on the voltage of the select bit line and the common source line. The voltages applied to the ground select line and the string select line can be different. Similarly, the voltage applied to the unselected word lines should be high enough to fully turn on the voltages applied to the selected bit lines and the common source line. It must be noted that the conduction voltage at the equivalent source terminal and the conduction voltage at the equivalent drain terminal may be different. Similarly, it can vary along the length of the string if necessary. For the word line corresponding to the memory cell to be programmed, the applied programming voltage should be high enough to cause electron injection. During a program operation, the voltage on the switched word line should fall within an operating range such that the drain-to-source voltage and program current in the target cell are high enough to generate hot carrier injection. The voltage range for a particular application can be determined experimentally or by simulation techniques.

4 is a layout diagram showing a common-source type NAND-type memory array operating using the programming bias described in the present invention, with a first bias condition to suppress disturbance. It shows the layout diagram of four series of NAND gates 101, 102, 103, 104, which are respectively connected to respective bit lines BL- 1 to BL-4 are coupled to a common source line CS105. For illustrative purposes, the bias voltages shown here are for programming a target memory cell 100 of the word line WL(i) corresponding to the NAND gate series 101 . The ground select transistor 111 is biased on the ground select line GSL such as V-GSL to precharge the equivalent source terminal of the NAND series to ground through the common source line CS 105 . String select transistor 112 is biased to a gate voltage of, for example, approximately V _CC , while the bit line voltage is biased to that previously described during the initial and subsequent portions of the programming interval. The switching memory cell 113 corresponding to the word line WL(i−1) is adjacent to the target memory cell 100 . Therefore, word line WL(i−1) receives V-SWL during the programming interval.

Alternative bias arrangements and array configurations may also be used. Figure 4 shows a representative implementation that involves biasing such that the current flow in the NAND array is from selected memory cells (lower voltage) to the common source line (higher voltage). Or alternatively, the equivalent source and equivalent drain terminal biases can be swapped.

According to one technique for suppressing disturbance of unselected memory cells, the unselected bit lines are set at a bit line voltage at or near ground such that current flow on the unselected bit lines is limited and It is not enough to program the cells that share the word line WL(i) with the target cell. It should be noted that when a target cell is on the first word line WL(1), the string select line SSL can be used to apply a switching voltage V-SWL, which is suitable as the string select transistor 112 instead of For memory cell operation. Alternatively, a dummy wordline placed between the wordline WL(0) and the string select transistor 112 as shown in the figure can be used.

FIG. 5 is a timing diagram showing an example of bit line and word line bias voltages during the hot carrier injection programming operation described in the present invention. It shows a timing diagram of an example of the bias voltage during the operation of FIG. 4 . Unselected bit lines (eg, BL-2) and common source line CS are biased to ground during this interval. The ground selection line GSL is coupled with approximately 10V. Additionally, both the equivalent source and equivalent drain terminals of the unselected word lines are coupled to approximately 10V in this example. The string select line SSL is coupled to a voltage of approximately V _CC . The selection bit line (BL-1) is coupled to _VCC or a voltage level close to it (such as the level of the string select line SSL) during the initial part of the programming interval, and then quickly drops to VCC during the subsequent part of the programming interval. to a potential of approximately ground (eg, to the right of line 500). The selected word line receives a programming pulse of approximately 14V during this exemplary programming interval. The switching voltage V-SWL is set to a level sufficient to provide current while maintaining a thermoelectric field.

When the voltage level on the bit line drops enough to cause the string select line SSL toggle switch to be turned on, current begins to flow in the series of NAND gates and then reaches the gate regulated by the voltage V-SWL applied to the switched memory cell. level, and it is sufficient to induce hot carrier injection.

Please refer to Table 1 below, which is a typical range of bias voltage levels for the erase operation.

Table 1

erase No character lines selected -8V select character line -8V toggle character line -8V No bit lines selected Floating select bit line Floating PW 12V SSL Floating GSL Floating CS Floating

6 is a layout diagram showing a common source type NAND type memory array operating using the programming bias described in the present invention, with a second bias condition to suppress disturbance. It shows the bias conditions for suppressing memory cell disturbance on unselected strings according to a second alternative implementation technique of the present invention. Therefore, FIG. 6 is a schematic circuit diagram showing that two NAND gate series 101, 102 are connected to respective bit lines BL-1, BL-2 and a common source via a series selection transistor and a ground selection transistor respectively. Layout diagram of polar line CS 105 coupling. The bias conditions shown here are for programming the target memory cell 100 of a corresponding word line WL(i) in the NAND series 101 . The ground select transistor 111 is biased to a drain terminal voltage level (ie, V _CS is set to V _D ) through the common source line CS105 and is serially coupled with the NAND gate. The string select transistor 112 couples the top of the NAND gate string to the selected bit line BL-1 by V _CC on the string select line and the two-stage voltage on the selected bit line BL-1. The switching cell 113 corresponding to the word line WL(i−1) is an equivalent source terminal adjacent to the target cell 100 . Therefore, the word line WL(i−1) receives V-SWL during the programming interval to support the hot carrier injection programming interval. Unselected bit lines are coupled to V _CS below V _CC such that both the equivalent source and equivalent drain regions are biased to one via unselected bit lines BL-2 and common source line CS 105 . common voltage.

7 is a layout diagram showing a common source type NAND type memory array operating using the programming bias described in this invention, with a third bias condition to suppress disturbance. It shows bias conditions for suppressing memory cell disturbance on unselected strings according to a third alternative implementation technique of the present invention. The target memory cell corresponding to the word line WL(i) receives the programming potential. The switching voltage is applied to the word line WL(i−1) at the bit line terminal of the NAND gate series. The bias voltage from the selected bit line is used to create a series of NAND gates between the string select switch (eg, string select transistor 112 ) and the target cell 100 during the second part of the programming interval. effective source region. The switching memory cell 113 receives a switching voltage which supplies the conductance of the switching memory cell to generate the hot carrier injection condition described previously. The unselected bit lines receive a supply potential, such as V _CC , which is held at a constant value during the programming interval to prevent current flow and cause self-boosting of the equivalent source terminals of the NAND series, thereby suppressing the unselected bit lines. Select the serial interference.

When the target memory cell for programming is the first memory cell in the NAND series, it is adjacent to the ground selection line, causing no memory cell adjacent to the equivalent source terminal of the target memory cell and can be used as a switching memory cell . Conversely, when the target cell for programming is the last cell in the NAND series, adjacent to the series select line, and the series is biased so that the equivalent source terminal is above, again causing No memory cell adjacent to the equivalent source terminal of the target memory cell can be used as a switching memory cell. In these cases, the string select line or the ground select line can control the conductance of the semiconductor body in a manner that acts as a memory cell under an appropriate bias voltage. In alternative embodiments, dummy wordlines may be used.

8 is a schematic diagram showing a simplified layout of an array of NAND gates with dummy word lines adjacent to both ends of the series of NAND gates. It shows a simplified layout of wordlines and a NAND gate array source-drain series similar to that of FIG. 3, except that the top dummy wordline TDWL adjoins the series select line SSL. As shown in the figure, the source-drain series 500-503 extend vertically on the page. The horizontal wires are located above the source-drain series 500-503. These horizontal wires include the string select line SSL, the top dummy word line TDWL, and the word lines WL(0) to WL(N-1). In addition, the horizontal wires also include a ground selection line GSL and a common source line CS. The dummy word line at the top of the string can be used to control a dummy memory cell during hot carrier injection programming as previously described.

FIG. 9 is a schematic diagram showing a programming operation of a virtual grounded NAND gate type memory array using the programming bias conditions described in the present invention. It shows the layout of seven series of NAND gates 201-207 arranged in a virtual grounded NAND gate architecture. In the virtual grounded NAND architecture described here, the bit line acts as both the bit line coupled to the sense amplifier and the reference line coupled to the reference voltage source, depending on the row position being accessed. The series of NAND gates is coupled to a corresponding set of bit lines BL- 1 to BL- 8 by a top bit line select transistor BLT and a bottom bit line select transistor BLB. For illustration, the bias voltage shown in the figure is the bias voltage for programming a target memory cell 300 corresponding to the word line WL(i) in the NAND gate series 204 . The first toggle switch transistor 301 is biased by V _CC on the bottom bit line select transistor BLB to enable two-stage operation, which applies the two-stage bit line voltage to the NAND series via bit line BL-5 204. Second toggle switch transistor 302 is biased by V-PASS on top bit line select transistor BLT to couple NAND series 204 to bit line BL-4, which is biased to as described above Common source voltage V _CS (for example, a source terminal voltage V _D ). All bit lines BL-1 to BL-3 to the left of NAND series 204 are biased to V _CS . All bit lines BL-6 through BL-8 to the right of NAND series 204 are biased to ground. The switching cell 304 corresponding to the word line WL(i+1) is adjacent to the target cell 300 . Therefore, word line WL(i+1) receives V-SWL. Region 310 in the semiconductor body is biased to an equivalent drain voltage (eg, V _CS in the embodiments of FIGS. 4 , 6 , and 7 ), thereby setting the equivalent drain region of NAND gate train 204 . On the unselected bit lines on the right, equivalent source regions 312 and equivalent drain regions 313 are biased to ground via bit lines BL-5 to BL-8 to prevent memory cells on the string from disturbed. On the unselected bit lines on the left, regions 314 and 315 are coupled to a relatively high voltage (eg, V _CS on bit lines BL-1 to BL-3) to prevent memory cells on the string from being damaged. interference. Therefore, when the switching cell 304 receives a switching voltage and the bit line voltage on the bit line BL-5 is lowered during a portion of the programming interval such that hot carrier injection occurs, the target cell 300 is programmed by hot carrier injection , while other memory cells in the array are not disturbed.

FIG. 10 is a schematic block diagram showing an integrated circuit using memory cells and bias circuits according to embodiments of the present invention. It uses the hot carrier injection programmed NAND flash memory described in the present invention. The integrated circuit 810 includes a NAND flash memory 812 using charge trapping or floating gate memory cells formed, for example, on a semiconductor substrate. A wordline (column)/string select and ground select decoder and driver (including suitable drivers) 814 is coupled to and in electrical communication with a plurality of wordlines 816, string select lines, and ground select lines along The NAND flash memory 812 is arranged in the column direction. A bitline (row) decoder (including appropriate drivers) 818 is in electrical communication with a plurality of bitlines 820 and is arranged along the row direction of the NAND flash memory 812 for self-NAND flash memory 812 The 812's memory cells read data from or write data to it. Optionally, a common source line decoder 819 is provided to support a shared word line and bit line arrangement, which can be used, for example, in three-dimensional memory architectures. Addresses are provided by bus 822 to wordline/string select and ground select decoders and drivers 814 and bitline decoders 818 . The sense amplifier/data input structure in block 824 , including current sources for read, program and erase modes, is coupled to bit line decoder 818 via data bus 826 . Data is provided to the data input line 828 by the input/output port on the integrated circuit 810 , or input to the data input structure in the sense amplifier/data input structure 824 from other internal/external data sources of the integrated circuit 810 . Other circuits 830 are included within the integrated circuit 810, such as general purpose processors or special purpose application circuits, or modules combined to provide system-on-chip functions supported by the array. Data is provided from the sense amplifiers in the sense amplifier/data input structure 824 to the integrated circuit 810 via the data output line 832 , or to other data terminals inside/outside the integrated circuit 810 .

The controller 834 used in this embodiment, using the bias adjustment state mechanism, controls the application of the bias adjustment supply voltage 836, such as read, program, erase, erase confirm and program confirm voltage or current application on the word line or bit line, and use the access control flow to control the operation of the word line/source line. The controller also applies switching sequences to induce hot carrier programming as described herein. The controller 834 can be implemented using special function logic circuits well known in the industry. In alternative embodiments, the controller 834 includes a general purpose processor, which can be used on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 834 is a combination of special purpose logic and a general purpose processor. The controller 834 can be configured to implement a method of inducing hot carrier injection into a selected memory cell in a series of NAND gates of a NAND array, comprising:

controlling the conductance of the series of NAND gates by applying a switching voltage to a word line adjacent to the selected word line to induce an equivalent source on one side of a selected memory cell of the series of NAND gates in a first semiconductor body region and induce equivalent drains in a second semiconductor body region on the other side of the selected memory cell of the NAND series;

floating the first semiconductor body region during an initial portion of a programming interval, and biasing the first semiconductor body region to a source terminal voltage during a subsequent portion of the programming interval;

biasing the second semiconductor body region to a drain terminal voltage; and

A programming potential greater than a hot carrier injection barrier level is applied to the selected memory cell during the programming interval.

Wherein the embodiment of the series of NAND gates in the NAND gate array includes a first switch between a first end of the series of NAND gates and the bit line or reference line, and a second switch interposed Between a second end of the NAND gate series and the bit line or reference line, wherein the bias includes opening a first switch that includes the selected memory cell of the NAND series, and via the first The switching switch applies the drain terminal voltage to the first semiconductor body region, and turns on the second switching switch including the selected memory cell of the NAND gate series, and applies the source terminal voltage to the second semiconductor body region through the second switching switch.

Alternatively, embodiments wherein the NAND series in the NAND array include a first switch interposed between a first end of the NAND series and the bit line or reference line, and a second A toggle switch is interposed between a second end of the NAND gate series and the bit line or reference line, wherein the bias comprises turning on a first toggle switch of a selected memory cell comprising the NAND gate series, and via The first switch applies a source terminal voltage to the first semiconductor body region, and turns on a second switch comprising the selected memory cell of the NAND series, and applies a drain terminal voltage to the second semiconductor via the second switch. subject area.

The controller 834 can be configured to implement a bias operation by closing at least one of the first or second switch on the unselected NAND series to prevent programming disturb. In addition, the controller 834 can also be configured to implement a bias operation by turning on at least one first and second switch on the unselected NAND series to prevent programming disturbance.

Other biasing schemes for this NAND tandem hot carrier injection operation are described in the descriptions of U.S. Patent Application Nos. 12/898,979 and 12/797,994, which are hereby incorporated by reference, which are related to the present invention, which are According to the use of switching memory cells and the modulation of channel current. Also used in some schemes to establish equivalent source and drain voltages. Some schemes use directly applied source and drain voltages. Some schemes use a dynamic or sweeping voltage V-SWL applied to switch memory cells.

The programming method described here includes application of the common source architecture to conventional NAND arrays and modified NAND arrays with virtual ground type architectures. For each array type, programming can be achieved by current flowing in first and second directions. According to the first current direction, the equivalent drain is located at the upper portion of the NAND series, and the equivalent source is located at the lower portion. For the second current direction, the equivalent source is located in the upper part of the NAND series, and the equivalent drain is located in the lower part.

A new inverse gate flash memory programming method is provided, which suppresses program disturb due to lower operating voltage. A new programming method allows the use of lower operating voltages based on the use of switching potentials to achieve hot carrier injection. As a result of this lower operating voltage, the driver circuit on this integrated circuit can be implemented using only a single MOSFET process without the need for an additional high voltage MOSFET process.

In addition, the word line voltage of this programming method is also lower than that required for conventional NAND flash memory FN programming. Therefore, very high voltage drive means are also not required. In addition, the vertical electric field through the tunnel oxide layer in the NAND flash memory is also smaller than that required for FN programming. The reliability of the device is also improved because of the lower electric field required.

Furthermore, lower programming and turn-on V _PASS voltages than those required for conventional FN operation result in lower wordline ILD voltages, and thus reduce wordline ILD due to shrinking wordline pitch resulting in crashes.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but if they do not depart from the content of the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims (11)

1. a kind of memory body, it is characterised in that it is included：

Multiple memory cell serial arrangements are in semiconductor main body；

A plurality of word-line, the word-line in a plurality of word-line and the memory cell in corresponding the plurality of memory cell couple；

One first switching transistor, between a reference line and the first side of the plurality of memory cell；

One second switching transistor, between one first bit line and the second side of the plurality of memory cell；And

Control circuit couples with a plurality of bit line, to be adapted to using the following steps to the plurality of note corresponding to word-line selected by one Recall one in born of the same parents selection memory cell to be programmed：

One of first and second side of the plurality of memory cell is biased at a programming section to a drain terminal voltage, and bias this One and second side another to source-side voltage to control the conductance during programming section；

Apply drain electrode end conducting voltage at the programming section between one of the selected word-line and first and second side Between word-line；

Apply source terminal conducting voltage at the programming section between the another of the selected word-line and first and second side Word-line between one；

Apply a program voltage at the programming section to the selected word-line, it applies a switching voltage to the selected word The adjoining word-line of the equivalent source side of first line, it applies conducting voltage to other word-lines；

Wherein, bias first and second side another to source-side voltage include set the source electrode terminal voltage to one at the beginning of Beginning class, it is less than a critical voltage, and the critical voltage is higher or lower than applying to pair of first and second switching transistor Answer the grid voltage and source electrode terminal voltage of one so that when this corresponds to an initial part of the switching transistor in the programming section Remain turned-off, and will quickly be reduced to one from the initial class during further part of the source electrode terminal voltage in the programming section Individual or multiple classes more than this less than the critical voltage of the grid voltage so that the corresponding switching transistor is in the programming section Middle unlatching.

2. memory body according to claim 1, it is characterised in that wherein described source terminal conducting voltage is in the programming area Between when can change so that in the part in the programming section, the injection of hot carrier occurs in the selected memory cell to set the institute Memory cell is chosen to a critical class of programming.

3. memory body according to claim 1, it is characterised in that wherein described biases the another of first and second side A period of time that the step of individual voltage to source-side is included in the programming section applies the voltage of a quick reduction.

4. memory body according to claim 1, it is characterised in that wherein described multiple memory cells are arranged to a NAND gate NAND string arranges.

5. memory body according to claim 1, it is characterised in that wherein the control circuit is opened in the programming section is somebody's turn to do First switching transistor, and second switching transistor is opened after the initial part in the programming section.

6. memory body according to claim 5, it is characterised in that also including multiple second memory cells and a plurality of word-line Coupling, and wherein the control circuit via first bit line apply the source electrode terminal voltage to the plurality of memory cell this second Side, apply the drain terminal voltage to first side of the plurality of memory cell via the reference line, and at least in the programming section The initial part when via a second bit line apply a voltage identical or close with ground voltage to the plurality of second remember The second side of born of the same parents is injected with suppressing hot carrier.

7. memory body according to claim 5, it is characterised in that also including multiple second memory cells and a plurality of word-line Coupling, and wherein the control circuit via first bit line apply the source electrode terminal voltage to the plurality of memory cell this second Side, apply the drain terminal voltage via the reference line and applied to first side of the plurality of memory cell, and via a second bit line Add a voltage identical or close with drain terminal voltage and injected to the second side of the plurality of second memory cell with suppressing hot carrier.

8. memory body according to claim 1, it is characterised in that also include：

Multiple second memory cells couple with a plurality of word-line, corresponding first switching transistor the reference line with it is the plurality of Between one first side of the second memory cell, and corresponding second switching transistor is in a second bit line and the plurality of second note Between one second side for recalling born of the same parents；

Wherein the control circuit at the programming section via the second bit line apply one it is identical with the initial class or connect Near voltage is injected to second side of the plurality of second memory cell with suppressing hot carrier.

9. memory body according to claim 1, it is characterised in that also including multiple second memory cells and a plurality of word-line And a second bit line coupling, and wherein the control circuit suppresses the hot carrier injection of the plurality of second memory cell.

10. memory body according to claim 1, it is characterised in that wherein described multiple memory cells are arranged to a common source Pole NAND gate NAND Flash memory array.

11. memory body according to claim 1, it is characterised in that wherein described multiple memory cells are arranged to one and virtually connect Ground NAND gate NAND Flash memory array.