CN102347076B - Selected Memory Hot Carrier Injection Method for Memory Elements and NAND Flash Memory - Google Patents

Abstract

The invention relates to a memory element and a memory selecting hot carrier injection method of a NAND flash memory. The memory device described herein includes a plurality of memory cells arranged in series in a semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection, which is generated by raising the channel potential to establish a heating electric field across the channel of the selected memory cell. Boosting channel hot carrier injection can be achieved by blocking current flow from the first side to the second side of selected memory cells in the nand string to self-boost a first semiconductor body region to a self-boost voltage by capacitive coupling and bias a second semiconductor body region to a reference voltage level, applying a programming potential greater than the channel hot carrier injection potential level to select memory cells to enable carriers to remain in the memory cells from the second semiconductor body region to cause hot carrier injection.

Description

Selected Memory Hot Carrier Injection Method for Memory Elements and NAND Flash Memory

technical field

The invention relates to a flash memory technology, in particular to an operation technique suitable for low-voltage programming and erasing operations in a NAND gate configuration. the

Background technique

Flash memory is a type of non-volatile integrated circuit memory technology. Traditional flash memory uses floating gate memory cells. As the density of memory devices increases, the floating gate memory cells get closer together, and the interaction of charges stored in adjacent floating gates will cause problems, thus forming a limit, making the use of floating gate flash memory density Unable to raise. Another type of memory cell used in flash memory is called a charge-trapping memory cell, which uses a charge-trapping layer instead of a floating gate. Charge-trapping memory cells use charge-trapping materials, which do not cause mutual influence between individual memory cells like floating gates, and can be applied to high-density flash memories. the

A typical charge storage memory cell comprises a field effect transistor (FET) structure comprising a source and drain separated by a channel, and a gate separated from the channel by a charge storage structure comprising tunneling dielectric layer, charge storage layer (floating gate or dielectric layer), and barrier dielectric layer. Earlier conventional designs such as SONOS devices, in which the source, drain and channel are formed on a silicon substrate (S), the tunneling dielectric layer is formed of silicon oxide (O), and the charge storage layer is formed of silicon nitride ( N), the barrier dielectric layer is formed of silicon oxide (O), and the gate is polysilicon (S). the

Flash memory devices are typically implemented using a NAND or NOR architecture, but other architectures are possible, including an AND architecture. The NAND gate architecture is particularly favored for its advantages of high density and high speed in data storage applications. The NOR gate architecture is suitable for other applications such as program storage because random access is an important functional requirement. In a NAND architecture, the programming process usually relies on Fowler-Nordheim (FN) tunneling and requires high voltages, typically on the order of 20 volts, and requires high voltage transistors to handle them. This additional high-voltage transistor, along with the transistors used for logic and other data flow in the same integrated circuit, adds to the complexity of the process. This will increase the manufacturing cost of the device. the

It can be seen that the above-mentioned existing flash memory device obviously still has inconveniences and defects in product structure and use, and needs to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable structure and method for general products and methods to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new memory element and NAND gate flash memory selection memory hot carrier injection method is one of the current important research and development topics, and it has also become a goal that the industry needs to improve. the

Contents of the invention

The purpose of the present invention is to overcome the defects existing in the existing flash memory device, and provide a new memory element and NAND gate flash memory selection memory hot carrier injection method, the technical problem to be solved is It can realize program operation with low voltage in NAND architecture, which is very suitable for practical use. the

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A memory element proposed according to the present invention includes: a plurality of memory cells connected in series in a semiconductor body, a plurality of word lines, a word line in the plurality of word lines and a corresponding word line in the plurality of memory cells The memory cell is coupled; and the control circuit is coupled to the plurality of bit lines, and a selected memory cell among the plurality of memory cells corresponding to a selected word line is programmed in the following steps: in a programming interval Applying a pass voltage to a word line on a first side of the selected word line; self-boosting a first semiconductor body region to a self-boosting voltage by capacitive coupling; during the programming interval applying a programming voltage to the selected word line; biasing a second semiconductor body region on a second side of the selected word line to a reference voltage during the programming interval; and applying a switching voltage To a word line adjacent to the selected word line, the switching voltage has a first phase and a second phase during the programming interval, so that the selected word line is connected to the selected word line in the first phase The corresponding selected memory cell is isolated from the reference voltage, and the selected memory cell is coupled to the reference voltage in the second stage. the

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures. the

In the aforementioned memory device, the selected memory cell corresponding to the selected word line is biased to the switching voltage during the second stage to perform channel hot carrier subprogramming. the

In the aforementioned memory device, the switching voltage is less than the programming voltage in the second stage. the

In the aforementioned memory element, the plurality of memory cells are arranged in a series of NAND gates. the

The aforementioned memory element further includes a first switch located between a bit line and a first side of the plurality of memory cells, and a second switch located between a reference line and a first side of the plurality of memory cells Between the two sides, and wherein the control circuit turns on the first switch and turns off the second switch in the programming interval. the

The aforementioned memory element further includes a second plurality of memory cells coupled to the plurality of word lines, and wherein the control circuit applies a voltage to a second bit line corresponding to the second plurality of memory cells to isolating a semiconductor body region of the second plurality of memory cells corresponding to the second side of the selected word line, and applying a pass voltage to the word corresponding to the second side of the selected word line word line to self-boost a semiconductor body region where the second plurality of memory cells are located to a voltage to suppress generation of hot carriers in a memory cell of the second plurality of memory cells coupled to the selected word line . the

The above-mentioned memory element further includes additional memory cells connected in series with the plurality of memory cells in the semiconductor body region and an additional word line, and the additional memory cells are placed between the plurality of memory cells and the first memory cell Between the two switches, and when the control circuit applies a pass voltage to the additional word line during the programming interval, the capacitance of the semiconductor body region on the first side of the selected word line increases.

In the aforementioned memory element, the control circuit turns on the second switch during the first phase of a portion of the switching voltage, and closes the second switching switch during at least a portion of the second phase of the switching voltage. the

The aforementioned memory element further includes a first switch located between a bit line and a first side of the plurality of memory cells, and a second switch between a reference line and a first side of the plurality of memory cells between the two sides, and wherein the control circuit turns off the first switch and turns on the second switch during the programming period. the

The aforementioned memory device further includes a second plurality of memory cells coupled to the plurality of word lines and a second bit line, and wherein the control circuit biases the second bit line during the programming interval such that in A first semiconductor body region in the second plurality of memory cells on the first side of the selected word line, and in the second plurality of memory cells on the second side of the selected word line A second semiconductor body region is biased to a reference voltage to suppress hot carrier generation. the

The above-mentioned memory element further includes additional memory cells connected in series with the plurality of memory cells in the semiconductor body region and an additional word line, and the additional memory cells are placed between the plurality of memory cells and the first memory cell Between a toggle switch, and when the control circuit applies a pass voltage to the additional word line during the programming interval, the capacitance of the semiconductor body region on the first side of the selected word line increases. the

In the aforementioned memory device, the control circuit applies a switching voltage to a plurality of word lines during the programming period. the

The aforementioned memory element, wherein the plurality of word lines includes a first group of word lines close to one end of the plurality of memory cells, and a second group of word lines close to the other end of the plurality of memory cells, and the control The circuit determines whether the selected word line is in the first group or the second group, and assigns the end of the selected word line to include the first group or the second group. the

The aforementioned memory device, wherein the plurality of memory cells connected in series in a semiconductor body are between the first and second switching transistors, and the plurality of word lines include a first string select line and a second The string selection lines are respectively coupled to the first and second switching transistors. the

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A memory element proposed according to the present invention includes: a series of NAND gates including a plurality of memory cells connected in series in a semiconductor body; a plurality of word lines, and the word lines in the plurality of word lines correspond to the corresponding The memory cells of the plurality of memory cells are coupled; and the control circuit is coupled to the plurality of bit lines to program a selected memory cell of the plurality of memory cells corresponding to a selected word line in the following steps B: blocking a first semiconductor body region between a first side of the selected memory cell of the NAND series and a second semiconductor of a second side of the selected memory cell of the NAND series carrier flow between body regions; self-pressurizing the first semiconductor body region to a self-boosting voltage by capacitive coupling; biasing the second semiconductor body region to a reference voltage; applying a thermal load greater than a injecting a programmed potential of energy barrier into the selected memory cell; and enabling flow of carriers from the second semiconductor body region to the selected memory cell to cause generation of hot carriers. the

The purpose of the present invention and its technical problems are solved by adopting the following technical solutions in addition. A hot carrier injection method for selected memory of NAND flash memory according to the present invention, which includes the following steps: blocking a first side of the selected memory cell between the NAND gate series Carrier flow between a semiconductor body region and a second semiconductor body region on a second side of the selected memory cell of the NAND series; the first semiconductor body region is self-pressurized by capacitive coupling to a self-boosting voltage; biasing the second semiconductor body region to a reference voltage; applying a programming potential greater than a hot carrier injection barrier to the selected memory cell; and enabling carriers to flow from the second The semiconductor body region flows to the selected memory cell to cause hot carrier generation. the

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures. the

The above method for selecting memory hot carrier injection of NAND flash memory includes applying a two-stage switching voltage to a memory cell adjacent to the selected memory cell in the NAND series, including a first-stage turn-off The memory cell is used to implement the blocking, and a second stage is turned on the memory cell to implement the enabling. the

In the aforementioned NAND gate flash memory selection memory hot carrier injection method, wherein the NAND gate series in the NAND gate array includes a first switching switch corresponding to a first NAND gate series. between one side and a bit line or a reference line, and a second switching switch between a second side of the plurality of memory cells and the reference line or bit line, and wherein the self-voltage boost comprising: closing the first switching switch in the series of NAND gates including the selected memory cell to isolate the first semiconductor body region and applying a pass voltage to the series of NAND gates of the selected memory cell The word line coupled to the first side turns on the second switch and applies a reference voltage to the second semiconductor body region through the second switch. the

The aforementioned hot carrier injection method for selected memory of the NAND gate flash memory includes closing the first and second switches in the series of unselected NAND gates. the

The aforementioned hot carrier injection method for the selected memory of the NAND gate flash memory includes turning on the first and second switches in the series of unselected NAND gates. the

The aforementioned NAND gate flash memory selection memory hot carrier injection method, wherein the NAND gate series of the array includes a first group of M memory cells and a second group of N memory cells, and if The selected memory cell is in the first set of M memory cells, biasing the series of NAND gates such that the first semiconductor body region includes at least the second set of N memory cells, and if the selected memory cell cell is in the second set of N memory cells, biasing the series of NAND gates such that the first semiconductor body region includes at least the first set of M memory cells. the

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from above technical scheme, main technical contents of the present invention are as follows:

The memory device described here, comprising a plurality of memory cells arranged in series in a semiconductor body, can be applied, for example, to a series of NAND gates in a NAND array, with a plurality of word lines coupled to corresponding memory cells . Control circuitry coupled to the plurality of bit lines and the semiconductor body is adapted to program a selected memory cell by hot carrier injection using elevated channel potentials to create a heating electric field across the selected The channel of the memory cell is generated. The hot carrier using this process can apply a pass voltage to the word line on a first side of the selected word line by the control circuit during a programming interval, so as to connect a first semiconductor by capacitive coupling The body region is self-boosted to a self-boosted voltage, and it applies a programming voltage to the selected word line during the programming interval, and biases the selected word line during the programming interval A second semiconductor body region on a second side to a reference voltage level is achieved. A switching voltage is applied to a word line adjacent to the selected word line, the switching voltage has a first phase and a second phase during the programming interval, so that in the first phase by turning off the corresponding Memory cells isolate the first and second semiconductor body regions and establish the self-boosting voltage level and the reference voltage level respectively, and in the second stage the selected memory cell is connected to the reference voltage level by turning on the corresponding memory cell couple and cause hot carrier injection. the

The selected word line is biased during the programming interval by a programming voltage high enough to overcome the hot carrier injection barrier. However, this programming voltage can be much lower than required for typical Fuller-Nordham (FN) programming. Other word lines corresponding to the plurality of memory cells receive a pass voltage lower than the programming voltage to suppress interference from other memory cells. The switching voltage in the second stage of the programming interval is also similarly lower than the programming voltage to suppress interference from switching memory cells. the

For a NAND gate serial configuration embodiment, a first switch (ground selection switch or bottom bit line selection switch) is located on a first side between a bit line and the plurality of memory cells between a reference line and a second side of the plurality of memory cells, and a second switching switch (serial selection switching switch or top bit line selection switching switch). In this embodiment, the control circuit operates in the programming interval to turn on the first switch to self-boost the channel potential by isolating the semiconductor body from the first side of the selected word line. The control circuit operates in the programming interval to turn on the second switch to connect the semiconductor body with the bit line corresponding to the second side of the selected word line or the reference voltage line for applying a reference voltage. the

A second plurality of memory cells coupled to the same plurality of word lines, such as a parallel series of NAND gates on an unselected bit line, the control circuit turns off the second plurality of memory cells by and apply a pass voltage to memory cells on both sides of the selected memory cell to implement a "self-boosted source" arrangement. In this arrangement, the semiconductor body regions on either side of the selected word line are self-voltage boosted to similar voltage levels to prevent hot carrier injection in unselected strings. Alternatively, the control circuit may use a "drain to ground" arrangement to bias the semiconductor body regions on either side of the selected memory cell to a reference by opening the first and second switches of the second plurality of memory cells. voltage stages to prevent hot carrier injection in unselected strings. the

The control circuit is operable to maximize the capacitance of the first semiconductor body region, which can be boosted to a self-boosting voltage level by a number of techniques. According to one technique, the plurality of memory cells can be extended to include one or more additional memory cells along one or more additional word lines and placed between the plurality of memory cells and the first switch between. In this technique, a control circuit applies a pass voltage to the additional word line to expand the size of the first semiconductor body region, thereby providing the capacitance of the first semiconductor body region. According to another technique, the control circuit arranges the plurality of word lines to include a first set of word lines proximate one end of the plurality of memory cells, and a second set of word lines proximate another end of the plurality of memory cells. When programming a selected memory cell, the control circuit determines whether the selected word line is a member of one of the first group or the second group, and the first end assigned to the selected word line is self boosted So far the self-boosting voltage stage, which is the end of the other group comprising the first or second group. In this case, at least all wordlines in one of the first group or the second group may be used to establish the size of the first semiconductor body region. Thus, all the memory cells in the series have a first semiconductor body region used to create a self-boosting voltage level that is larger than a second semiconductor body region used to create a reference voltage level. the

The present invention also provides a hot carrier injection method for selected memory of the NAND gate flash memory, including blocking a first semiconductor body region and a first side of the selected memory cell of the NAND gate series. Carrier flow between a second semiconductor body region on a second side of the selected memory cell of the NAND series; the first semiconductor body region is self-voltage boosted to a self-voltage boost by capacitive coupling voltage; biasing the second semiconductor body region to a reference voltage level; applying a programming potential greater than a hot carrier injection barrier level to the selected memory cell; and enabling carriers to flow from the second semiconductor body region Flow to the selected memory cell results in generation of hot carriers. the

By means of the above-mentioned technical scheme, the method for selecting memory hot carrier injection of the memory element and the NAND flash memory of the present invention has at least the following advantages and beneficial effects:

The present invention can suppress process programming interference due to low operating voltage. Lower operating voltages can be used according to the new programming of hot carrier injection achieved using elevated node potentials. As a result of the lower operating voltage, the driver circuit in this integrated circuit can be implemented using only one MOSFET process without the need for an additional high voltage MOSFET process. the

The present invention is because the bit line voltage does not need to overcome the hot electron injection energy barrier height compared with the conventional channel hot electron injection operation. Therefore, the bit line voltage can be VCC or other lower voltage than conventional channel hot electron injection (CHE) programming voltage. In addition, the bit lines do not consume DC current during channel hot electron injection. Therefore, this new programming method should be able to achieve low power consumption. the

In addition, the word line voltage of this programming method is also lower than that required for the conventional NAND gate flash memory FN programming operation. Therefore no very high voltage drive means are required. In addition, the vertical electric field across the tunnel oxide in this NAND flash memory is also smaller than that required for FN injection. As a result of the low electric field requirement, the reliability of the device can be improved. the

Further, the present invention can result in reduced dielectric voltage between wordlines due to the lower programming and Vpass voltages required for the conventional FN programming operation, and thus reduce the distance generated between the wordlines due to the reduced distance between the wordlines. Dielectric breakdown problem between the word lines. the

To sum up, the present invention relates to a method of selecting memory hot carrier injection for a memory element and a NAND flash memory, which can lead to a reduction in the number of digits due to lower programming and Vpass voltages required for traditional FN programming operations. The dielectric voltage between the word lines is increased, and thus the problem of dielectric breakdown between the word lines due to the shrinking distance between the word lines is reduced. The present invention has significant progress in technology, and has obvious positive effects, and is a novel, progressive and practical new design. the

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings. the

Description of drawings

FIG. 1A and FIG. 1B are cross-sectional views showing a prior art flash memory with a NAND gate structure. the

2A and FIG. 2B are two-stage cross-sectional views showing a two-stage NAND series for drain self-boosting and hot carrier programming in a programming interval according to an embodiment of the present invention. the

FIG. 3 is a timing diagram showing voltage waveforms of a selected bit line during the two-stage programming intervals of FIGS. 2A and 2B . the

FIG. 4 is a timing diagram showing voltage waveforms of an unselected bit line of a NAND series, which shares a word line with the selected NAND series, during a programming interval. the

5A and FIG. 5B are schematic diagrams showing two phases of bias voltage cross-section of programming of an unselected NAND series, which is when a NAND series and selected NAND series share word lines. Figure 4 shows the bias to boost-node for the case of hot load subprogramming. the

6 is a schematic diagram showing a common source type NAND memory array operating using the programming bias described herein. the

7 is a schematic diagram showing a common source type NAND memory array operating according to an alternative embodiment using the programming bias described herein. the

8 is a schematic diagram showing a virtual grounded NAND array operating using the programming bias described herein. the

9 is a schematic diagram showing a virtual grounded NAND array operating according to an alternative implementation using the programming bias described herein. the

10 is a schematic diagram showing a virtual grounded NAND array including more than one switched memory cell operating according to an alternative implementation using the programming bias described herein. the

Fig. 11 is a schematic cross-sectional view showing the first-stage bias voltage of a selected bit line in the two-stage programming interval of lifting-node hot-carrier programming, wherein the target memory cell is near the end of the series of NAND gates end. the

Fig. 12 is a schematic cross-sectional view showing the first-stage bias voltage of a selected bit line in the two-stage programming interval of boost-node hot-carrier programming, wherein the series of NAND gates is extended by dummy word lines . the

13 is a simplified layout diagram showing a NAND array with dummy word lines adjacent to the common source terminal of the NAND series. the

14 is a schematic diagram showing a simplified layout of a NAND array with dummy word lines adjacent to string select line terminals of the NAND strings. the

15 is a simplified layout diagram showing a NAND gate array without dummy wordlines, wherein a simplified layout diagram showing a logical arrangement of a first group of wordlines and a second group of wordlines such that the virtual drain terminal of a selected memory cell is summed is greater than the virtual source extreme. the

16 is a schematic diagram showing a simplified layout of an array of NAND gates with dummy word lines adjacent to both ends of the series of NAND gates. the

Figure 17 is a schematic diagram showing an alternative timing arrangement for the use of programmed intervals to induce boost node hot carrier injection as described herein. the

Fig. 18 is a schematic diagram showing another alternative timing arrangement for the use of programmed intervals to induce the boost node hot carrier injection described herein. the

19 is a simplified schematic diagram showing an integrated circuit using the self-boosting virtual drain, hot carrier injection programmed NAND flash memory described herein. the

7, 8: Gate dielectric layer 9: Charge trapping structure

10: Semiconductor body 11, 19: Contacts

12-18: Node 21: Ground selection line GSL

22-27: Character line 28: Serial selection line SSL

30, 105: common source line CS31: bit line

32: No bit line selected

40, 100, 157, 180, 300, 320: Target memory cells

41, 113, 155, 156, 181, 304, 324: switch memory cells

42, 43: Toggle switch 50, 51: Isolation area

52: Depletion region 54: Hot carriers

62: Self-pressurization zone

101, 102, 103, 104, 201-207: series of NAND gates

111: Ground selection transistor 112: String selection transistor

301, 302, 321, 322: switching transistors 401, 402: dummy word lines

500-503: source/drain series 810: integrated circuit

812: NAND gate flash memory array 814: Word line (column) decoder and driver

816: word line 818: bit line decoder

820: bit line 822, 826: bus

824: Sense amplifier/data input structure 830: Other circuits

834: (hot carrier injection programming and FN erasing) controller

836: Bias voltage adjustment supply voltage 828: Data input line

832: data output line

Detailed ways

In order to further illustrate the technical means and effects that the present invention takes to achieve the intended invention purpose, below in conjunction with the accompanying drawings and preferred embodiments, the selection memory heat load of the memory element and the NAND flash memory proposed according to the present invention The specific implementation, structure, method, steps, features and effects of the sub-injection method are described in detail below. the

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation mode, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and description, and are not used to explain the present invention. be restricted. the

1A and FIG. 1B are cross-sectional views showing a prior art NAND structure flash memory, wherein a plurality of dielectric charge trapping flash memory cells are arranged in series to form a series of NAND gates and The bias voltage is used for FN tunneling programming. FIG. 1A shows the bias voltages of a NAND series including target cells on a selected bit line, and FIG. 1B shows the bias voltages of a NAND series on unselected bit lines. A technique for implementing NAND flash memory using bandgap engineered SONOS charge trapping technology is described in US Patent No. 7,315,474 to Lue, which is incorporated herein by reference. NAND cascades can be implemented using many different configurations, including FinFET technology, shallow trench isolation technology, vertical NAND technology, and more. For some examples of vertical NAND gate structures, see European Patent No. EP 2048709 entitled "Non-volatile memory device, method of operating the same and method of fabricating the same" by Kim et al. the

Please refer to FIG. 1A , the memory cell is shown formed on a semiconductor body 10 . For n-channel memory cells, semiconductor body 10 may be an isolated p-well located in a deep n-well region of a semiconductor wafer. Alternatively, the semiconductor body 10 may be isolated by a dielectric layer or other materials. P-channel memory cells may also be used in some embodiments, where the dopant material of the semiconductor body is n-type. the

A plurality of flash memory cells can be arranged in series along a bit line direction perpendicular to the word line direction. The word lines 22-27 extend through a series of parallel NAND gates. Nodes 12-18 are n-type regions in the semiconductor body (for n-channel devices) and serve as source/drain regions for memory cells. A first switch formed by metal-oxide-semiconductor transistors has a gate in the ground select line GSL 21, which is connected to the corresponding memory cell with the first word line 22 and formed by the n-type region in the semiconductor body 10. between one of the contacts 11 . This contact point 11 is connected to the common source line CS30. A second switch formed by metal-oxide-semiconductor transistors has a gate in the string select line SSL 28, which is connected to the corresponding memory cell with the last word line 27 and formed by the n-type region in the semiconductor body 10. between one of the contacts 19 . This contact 19 is connected to the bit line BL31. The first and second switches in this exemplary embodiment are metal-oxide-semiconductor transistors, in this example having a gate dielectric of silicon dioxide. the

In this illustration, there are six memory cells in the string for simplicity. In a typical configuration, a series of NAND gates can contain 16, 32 or more memory cells arranged in series. The word lines 22 - 27 corresponding to these memory cells have charge trapping structures 9 between the word lines and the channel region in the semiconductor body 10 . The charge trapping structure 9 in the memory cell may be a dielectric charge trapping structure, a floating gate charge trapping structure, or other suitable flash memory structures for programming using the techniques described herein. In addition, embodiments of the NAND flash structure have been developed without junctions in which nodes 13-17, and optionally nodes 12 and 18, can be omitted from this structure. the

FIG. 1A is a cross-sectional view of a prior art NAND-based flash memory, which is a schematic diagram of bias voltages for inducing FN tunneling to program memory cells corresponding to word lines 24 . According to the bias shown here, the ground select line GSL is biased to about 0V and the common source line is grounded, so that the first toggle switch corresponding to the ground select line GSL 21 is closed and the string select line SSL is biased to To about VCC and the selected bit line is also grounded, so that the second toggle switch corresponding to the string select line SSL 28 is on. Under these conditions, the semiconductor body in the region 33 associated with the NAND series is precharged to about 0V. The select word line 24 is biased to a high voltage programming level V-PGM, which may be on the order of 20 volts in some embodiments. Unselected word lines 22, 23, 2527 are biased to a pass voltage V-PASS, which is less than V-PGM by a voltage that inhibits programming of unselected cells in the string. As a result, electrons tunnel into the charge-trapping structures of the selected memory cells. the

FIG. 1B is a cross-sectional view showing a prior art NAND gate (NAND) architecture flash memory, which is an offset to the unselected bit lines of the NAND series sharing word lines 22-27 in FIG. 1A Pressure diagram. It can be seen from the figure that the ground select line GSL and the string select line SSL of all the word lines have the same bias voltage as shown in FIG. 1A . Similarly, the common source line 30 is also grounded. However, the unselected bit lines are biased to about the level of VCC. This closes the second toggle switch, which corresponds to the string select line SSL, and decouples the semiconductor body in region 35 from the unselected bit line BL 32. As a result, the semiconductor body in region 35 is self-boosted by capacitive coupling from voltages applied to wordlines 22-27, which prevents charge trapping structures sufficient to interfere with memory cells in unselected NAND series. An electric field is formed. So-called incrementally stepped pulse programming (ISSP) operation based on capacitive self-boosting is well known in the art. the

2A and FIG. 2B are two-stage cross-sectional diagrams showing a two-stage selection NAND series of drain self-voltage boosting and hot carrier programming in a programming interval according to an embodiment of the present invention. A schematic diagram showing memory cells arranged in series to form a series of NAND gates for drain self-boosting, hot carrier programming as described herein. For n-channel memory cells, hot carriers include electrons. For p-channel memory cells, a similar technique can be used to induce hot carrier injection, where the hot carriers include holes. The programming paradigm described here is illustrated with an n-channel memory cell, but the so-called "self-boosting node hot carrier injection" can alternatively be implemented with a p-channel memory cell. the

The first stage is shown in FIG. 2A where the common source line 30 is grounded and the selected bit line 31 is also coupled to approximately 0V. The ground select line GSL 21 is biased to approximately 0V such that the first toggle switch 42 is closed, decoupling the semiconductor body from the common source line CS 30. The string select line SSL is biased to approximately VCC to turn on the second switch 43 to couple the semiconductor body to the selected bit line 31 . The word line corresponding to the target memory cell 40 receives the programming pulse V-PGM. The word line adjacent to the target memory cell 40 at the end of the bit line 31 receives a two-stage switching voltage V-SW, which is at a low voltage during the programming interval of the first stage, so that the channel of the switching memory cell 41 is closed, and as isolation regions 50 and 51 in the semiconductor body. Under the bias conditions during this programming interval, the region 50 in the semiconductor body 10 is self-stressed by capacitive coupling to the virtual drain voltage Vd in response to the target word line receiving V-PGM and the first switching The pass voltage V-PASS (drain terminal) on the word line between switches 42 . Region 51 in semiconductor body 10 is precharged to virtual source voltage Vs by coupling bit line 31 and substrate biased to approximately 0V. The voltage V-PASS (source terminal) is coupled to the word line between the switching memory cell 41 and the second switching switch 43 . V-PASS (source terminal) can be the same voltage as V-PASS (drain terminal), or a different voltage, depending on a specific application or programming condition. The self-boosting voltage level in region 50 and the reference voltage level in region 51 are isolated in the first-stage programming interval by the depletion region 52 under the switching memory cell. the

In this example, all of the example NAND series shown here, the first and second switching switches (42, 43) are implemented using field effect transistors in series with the memory cells in the series. In the example shown in FIG. 2A, the gate dielectric layer of the field effect transistor is a single-layer structure and generally includes silicon oxide or nitrogen-doped silicon oxide. In other embodiments, the gate dielectric layer of the field effect transistor is a single-layer structure, and generally includes silicon oxide or nitrogen-doped silicon oxide. The field effect transistors that switch the switches (eg 42, 43) in the string may use multiple gate dielectric layers, including the same gate dielectric layer as all charge trapping structures used in the string. This solution can simplify the manufacturing process of the memory cell. In such an embodiment, the first and second switches may be characterized as "memory cells". If necessary, the channel length of the field effect transistor used as the switch can be longer than the channel length of the memory cell. the

The second stage of the programming interval is shown in FIG. 2B , where the switching voltage V-SW is changed to turn on the switching memory cell 41 adjacent to the target memory cell 40 . The difference between Vd and Vs at the time of switching is sufficient to induce thermal carriers 54 in the channel of the target memory cell. The voltage V-PGM on the word line corresponding to the target memory cell is sufficient to overcome the energy barrier height for hot carriers and cause induced hot carrier injection programming. A programming operation may include a series of programming intervals as described in FIGS. 2A and 2B , with interleaved programming verification steps to efficiently achieve target thresholds. This technique can also be used in embodiments for multi-level programming to store more than one bit per memory cell. the

FIG. 3 is a timing diagram showing voltage waveforms of a selected bit line during the two-stage programming intervals of FIGS. 2A and 2B . During the bit line setting interval, the bias voltage of the string select line SSL is increased to a level approximately VCC. In this setting interval, the voltage level Vd of the dummy drain region 50 and the voltage level Vs of the dummy source region 51 are both maintained at about 0V. During a programming interval, the voltage V-PGM is pulsed as previously described to a level high enough for hot carriers to overcome the injection barrier. Additionally, during the first phase of this programming interval, which may be referred to as the VDS setup phase, programming of unselected memory cells in the string can be inhibited by the voltage V-PASS being pulsed to one less than V-PGM Voltage. In some embodiments, the voltage V-PASS may be lower at the virtual source terminal than at the virtual drain terminal. In the first phase of the programming interval, the voltage V-SW is kept at a low voltage to turn off the memory cell 41 . In this example, the dummy drain region 50 is self-boosted by capacitive coupling so that the dummy drain voltage Vd is boosted beyond the Vcc level, while the dummy source voltage Vs remains at about 0V. After a sufficient time interval to allow the target memory cell to raise the source voltage VDS to a level that can induce hot carrier injection, the second phase of the programming interval begins, which may be referred to as the programming phase. During the second phase of the programming interval, voltage V-SW is pulsed to a switching voltage, in this embodiment not higher than V-PASS. During at least a first phase of the interval represented by the shaded area 90, the drain/source voltage VDS is maintained sufficiently to induce hot carriers, and hot carrier injection occurs to program the target memory cell. After V-PASS and V-PGM fall at the end of the programming phase of the programming interval, the string select line SSL bias can be maintained at the level of VCC for a period of time, at which time the semiconductor body can be discharged through the bit line. the

FIG. 4 is a timing diagram showing voltage waveforms of an unselected bit line of a NAND series, which shares a word line with the selected NAND series, during a programming interval. For unselected bit lines in this series of NAND gates, the voltage level of the semiconductor body is self-voltage boosted to the first level in the bit line setting interval, and the voltage level of the word line is increased by the word line voltage in the first and second programming intervals. The two-stage self-boosting makes the virtual drain and virtual source voltages equal or nearly equal when the second stage of the programming interval begins. As a result, hot carriers will not be generated on unselected bit lines of the NAND series, and the memory cell will not be disturbed. the

5A and FIG. 5B are schematic diagrams showing two phases of bias voltage cross-section of programming of an unselected NAND series, which is when a NAND series and selected NAND series share word lines. Figure 4 shows the bias to boost-node for the case of hot load subprogramming. In FIG. 5A, the first stage is shown, wherein the common source line 30 is grounded, and the unselected bit lines 32 are biased to a level of about VCC, rather than as the selected bit lines are biased to about 0V. The ground select line GSL 21 is coupled to approximately 0V to close the first toggle switch 42u, decoupling the semiconductor body from the common source line CS 30. The string select line SSL 28 is coupled to approximately VCC, which does not turn on the second toggle switch 43u, thus decoupling the semiconductor body from the unselected bit lines 32. The word lines corresponding to the unselected target memory cells 40u receive the programming pulse V-PGM. The word line adjacent to the bit line end of the unselected target cell 40u receives a switching voltage V-SW, which is kept at a low voltage during the first phase of the programming interval, so that the switching cell 41u acts as an isolated semiconductor body in areas 50 and 60. Under the bias conditions during the first phase of this programming interval, region 50 in semiconductor body 10 is self-voltage boosted to virtual drain voltage Vd by capacitive coupling in response to the target word line between receiving V-PGM The pass voltage V-PASS (drain terminal) on the word line between the first switching switch 42u. Regions 60 in semiconductor body 10 of unselected bit lines are also self-boosted by capacitive coupling and reach a virtual source voltage Vs close to virtual drain voltage Vd in response to pass voltage V-PASS (source terminal). The self-boosting voltage level in region 50 is similar to the reference voltage level in region 60, but is still isolated by depleted region 61 below switching memory cell 41u. the

In FIG. 5B , the second stage of this programming interval is shown, in which switching voltage V-SW is changed to turn on switching memory cell 41u, coupling regions 50 and 60 together to form self-boosting region 62 . During switching the difference between Vd and Vs is zero, or a level too low to induce heat carriers in the channel of the memory cell corresponding to the target word line. The voltage V-PGM on the word line corresponding to the unselected target cell 40u is also not sufficient to induce FN tunneling in the region 63, and so that the unselected line cell 40 of the unselected bit line is not disturbed. the

The bias levels for representative program and erase operations are shown in the table below. the

the programmatic erase No character line selected 6-12V -8V select character line 10-16V -8V Toggle character lines (second stage) 4-12V -8V No bit line selected VCC Floating select bit line 0V Floating PW 0V 12V SSL VCC Floating/VCC GSL 0V Floating/VCC CS 0V Floating

FIG. 6 is a schematic diagram showing a common source type NAND gate memory array operating using the programming bias described herein, showing the layout of four series of NAND gates 101, 102, 103, 104. , which are respectively coupled to respective bit lines BL-1 to BL-4 and a common source line CS 105 via a string selection transistor (eg, 112) and a ground selection transistor (eg, 111). For the purpose of illustration, the bias voltage shown here is to program a target memory cell 100 of the word line WL(i) corresponding to the NAND gate series 101 . The first toggle switch transistor 111 is biased by ground on the ground select line GSL to decouple the series of NAND gates from the common source line CS 105. The second switch transistor 112 is biased by the string select line SSL to couple the NAND string to the selected bit line BL-1. The switching memory cell 113 corresponding to the word line WL(i−1) is adjacent to the target memory cell 100 . Therefore, word line WL(i−1) receives V-SW to support this two-stage programming interval. In the first phase of this programming interval, region 120 in the semiconductor body is biased to approximately 0 V of the virtual source voltage Vs, and region 121 in the semiconductor body is biased to the virtual drain by capacitive coupling. Voltage Vd. On unselected bit lines, regions 122, 123 are also brought to a relatively high voltage by capacitive coupling. Therefore, when the second phase of the programming interval begins, hot carrier injection will occur in the target memory cell 100, while other memory cells in the array will not be disturbed. It should be noted that when the memory cell is on the first word line WL(0), the string select line SSL can be used to apply the switching voltage V-SW to the switching transistor 112, allowing the bit line operation of the NAND gate string is a virtual source. the

7 is a schematic diagram showing a common source type NAND memory array operating according to an alternate embodiment using the programming bias described herein. It shows the bias condition of the switching transistor 113 adjacent to the common source side of the target memory cell 100 in the series. Therefore, FIG. 7 is a circuit diagram showing the layout of four NAND gate series 101, 102, 103, 104, which are respectively connected to respective bit lines BL-1 to BL-4 via a series selection transistor and a ground selection transistor. It is coupled to a common source line CS105. The bias voltage shown here is to program a target memory cell 100 of the word line WL(i) corresponding to the NAND gate series 101 . The first toggle switch transistor 111 is biased by VCC on the ground select line GSL to couple the series of NAND gates to the common source line CS 105. The second toggle switch transistor 112 is biased by the string select line SSL and VCC of the selected bit line BL-1 to decouple the NAND series from the selected bit line BL-1. The switching memory cell 113 corresponding to the word line WL(i+1) is adjacent to the target memory cell 100 . Therefore, word line WL(i+1) receives V-SW to support this two-stage programming interval. In the first stage of this programming interval, the region 150 in the semiconductor body is biased to the virtual drain voltage Vd by capacitive coupling. A region 151 in the semiconductor body is biased to a virtual source voltage Vs via a common source line CS. On unselected bit lines, which are coupled to 0V, region 152 is biased to ground via unselected bit lines BL-2 to BL-4 and region 153 is also biased to land. Therefore, when the second phase of the programming interval begins, hot carrier injection will occur in the target memory cell 100, while other memory cells in the array will not be disturbed. the

Figures 6 and 7 show two possible bias directions, from the top and bottom of the string in a single array configuration. This has the advantage of ensuring that the semiconductor body portion acting as a dummy drain has sufficient capacitance to maintain the hot carrier injection current necessary for a reasonable programming speed. For example, the programmed controller can be used to bias the array such that the virtual drain side of the target cell has at least half of the digit lines in the string. the

FIG. 8 shows a layout diagram of seven series of NAND gates 201-207 arranged in a virtual grounded NAND gate architecture. In the virtual grounded NAND architecture described here, the bit line acts as both the bit line coupled to the sense amplifier and the reference line coupled to the reference voltage source, depending on the row position being accessed. The series of NAND gates is coupled to a corresponding set of bit lines BL- 1 to BL- 8 by the top bit line select transistor BLT and the bottom bit line select transistor BLB. For illustration, the bias voltage shown in the figure is the bias voltage for programming a target memory cell 300 corresponding to the word line WL(i) in the NAND gate series 204 . The first toggle switch transistor 301 is connected to VCC on the bottom bit line select transistor BLB to couple the NAND series 204 to BL-5, which is grounded. The second switch transistor 302 is connected to VCC on the top bit line select transistor BLT to decouple the NAND series 204 from BL-4, which is biased to VCC. All bit lines BL-1 to BL-3 to the left of NAND series 204 are biased to VCC. All bit lines BL-6 through BL-8 to the right of NAND series 204 are biased to ground. The switching cell 304 corresponding to the word line WL(i+1) is adjacent to the target cell 300 . Therefore, word line WL(i+1) receives V-SW to support this two-stage programming interval. In the first phase of this programming interval, region 311 in the semiconductor body is biased to approximately 0 V of the virtual source voltage Vs, and region 310 in the semiconductor body is biased to the virtual drain by capacitive coupling. The voltage Vd is thus set for the second phase of the programming interval, where hot carrier injection causes the target memory cell 300 to be programmed. On the unselected bitlines on the right, regions 312 and 313 are biased to ground via bitlines BL-5 to BL-8 to avoid disturbing the memory cells on the string. On the unselected bit lines on the left, regions 314 and 315 are self-boosted to a relatively high voltage by capacitive coupling to avoid disturbing the memory cells on the string. Therefore, when the second phase of the programming interval begins, hot carrier injection will occur in the target memory cell 300 without disturbing other memory cells in the array. the

FIG. 9 shows a schematic diagram of adjusting bias similar to FIG. 8 arranged in a virtual grounded NAND architecture, with the switching transistors on the other side. The series of NAND gates is coupled to a corresponding set of bit lines BL- 1 to BL- 8 by the top bit line select transistor BLT and the bottom bit line select transistor BLB. For illustration, the bias voltage shown in the figure is the bias voltage for programming a target memory cell 320 corresponding to the word line WL(i+1) in the NAND gate series 204 . The first toggle switch transistor 321 decouples the NAND series 204 from BL-5, which is biased to VCC, from the bottom bit line select transistor BLB to VCC. The second toggle switch transistor 322 is connected to VCC on the top bit line select transistor BLT to couple the NAND series 204 to BL-4, which is ground. All bit lines BL-1 to BL-3 to the left of NAND gate train 204 are biased to ground. All bit lines BL-6 through BL-8 to the right of NAND series 204 are biased to VCC. The switching cell 324 corresponding to the word line WL(i) is adjacent to the target cell 320 . Therefore, word line WL(i) receives V-SW to support this two-stage programming interval. In the first phase of this programming interval, region 330 in the semiconductor body is biased to approximately 0 V of the virtual source voltage Vs, and region 331 in the semiconductor body is biased to the virtual drain by capacitive coupling. The pole voltage Vd is therefore set for the second phase of the programming interval, where hot carrier injection causes the target memory cell 320 to be programmed. On the unselected bit lines on the right, regions 332 and 333 are self-boosted to a relatively high voltage by capacitive coupling to prevent memory cells on the string from being disturbed. On the unselected bitlines on the left, regions 334 and 335 are biased to ground via bitlines BL-1 to BL-4 to prevent memory cells on the string from being disturbed. Therefore, when the second phase of the programming interval begins, hot carrier injection occurs in the target memory cell 320 without disturbing other memory cells in the array. the

FIG. 10 shows the bias conditions of the NAND gate array similar to FIG. 6 and FIG. 7 , where two switching memory cells 155 , 156 are adjacent to the target memory cell 157 on the common source CS side of the series. FIG. 10 shows a layout diagram of four NAND gate series 101, 102, 103, 104, which are respectively connected to respective bit lines BL-1 to BL-4 and a common source via a series selection transistor and a ground selection transistor. The pole line CS 105 is coupled. The bias voltage shown here is for programming a target memory cell 157 of the word line WL(i+1) corresponding to the NAND gate series 101 . The first toggle switch transistor 111 is biased by ground on the ground select line GSL to decouple the series of NAND gates from the common source line CS 105. The second toggle switch transistor 112 is biased by the string select line SSL to VCC to couple the NAND string to the selected bit line BL-1, which is biased to ground. The switching memory cell 155 corresponding to the word line WL(i−1) and the switching memory cell 156 corresponding to the word line WL(i) are adjacent to the target memory cell 157 . Thus, word lines WL(i−1) and WL(i) receive V-SW to support this two-stage programming interval, which may be the same or different depending on the application of a particular embodiment. In the first phase of this programming interval, region 160 in the semiconductor body is biased to approximately 0 V of the virtual source voltage Vs, and region 161 in the semiconductor body is biased to the virtual drain by capacitive coupling. Voltage Vd. By biasing the unselected bit lines to VCC, thus decoupling the corresponding series of NAND gates from these bit lines, regions 162, 163 are also brought to a relatively high voltage by capacitive coupling. Therefore, when the second phase of the programming interval begins, hot carrier injection will occur in the target memory cell 157 without disturbing other memory cells in the array. Using two switching cells 155, 156 to isolate the dummy drain region 161 and dummy source region 160 during the first phase of this programming interval can suppress leakage currents including subthreshold leakage during the setup phase of the programming interval. the

FIG. 11 shows a cross-sectional view of a series of NAND gates similar to FIGS. 2A and 2B . In FIG. 11 , the bias voltage of the first stage is shown, wherein the target memory cell 180 is near one end of the string, for example, near the ground select line GSL. Under this condition, the common source line 30 is grounded and the selected bit line 31 is also coupled to approximately 0V during the first phase of the programming interval. The ground select line GSL 21 is biased to approximately 0V such that the first toggle switch 42 is closed, decoupling the semiconductor body from the common source line CS 30. The string select line SSL 28 is biased to approximately VCC to turn on the second toggle switch 43, coupling the semiconductor body to the selected bit line 31. The word line corresponding to the target memory cell 180 receives the programming pulse V-PGM. Word lines adjacent to the target cell 180 at the end of the bit line 31 receive a switching voltage V-SW to establish the switching cell 181. During the programming interval of the first stage, the switching voltage V-SW is at a low voltage, so that the switching memory cell 181 is used to isolate the regions 183 and 184 in the semiconductor body. During a programming interval, which is the bias condition, region 184 in semiconductor body 10 is self-voltage boosted to virtual drain voltage Vd by capacitive coupling in response to the target word line between receiving V-PGM and GSL The pass voltage V-PASS (drain terminal) on the word line between the lines. Region 183 in semiconductor body 10 is precharged to virtual source voltage Vs by coupling bit line 31 to the substrate. The voltage V-PASS (source terminal) is coupled to the word line between the switched word line of the memory cell 181 and the second switch 43 . The self-boost voltage level in region 184 and the reference voltage level in region 183 are isolated by the depleted region beneath the switching memory cell 181 . In this case, however, the dummy drain region 184 is small, and thus would have a relatively small capacitance. A small capacitance results in a lower amount of hot carrier generation in the region 90 of FIG. 3 and reduces the amount of hot carrier injection that can be achieved in a single redistribution interval. the

Therefore, as shown in FIG. 12, it is an alternative to use one or more dummy word lines (401, 402) between the GSL and the memory cells of the NAND series to improve minimum programming efficiency. Example. FIG. 12 shows a cross-sectional view of a series of NAND gates similar to FIG. 11 . In FIG. 12 , the bias voltage of the first stage is shown, wherein the target memory cell 480 is near one end of the string, for example, near the ground select line GSL. Under this condition, the common source line 30 is grounded and the selected bit line 31 is also coupled to approximately 0V during the first phase of the programming interval. The ground select line GSL 21 is biased to approximately 0V such that the first toggle switch 42 is closed, decoupling the semiconductor body from the common source line CS 30. The string select line SSL is biased to approximately VCC to turn on the second switch 43 to couple the semiconductor body to the selected bit line 31 . The word line corresponding to the target memory cell 480 receives the programming pulse V-PGM. The word line adjacent to the target cell 480 at the end of the bit line receives a switching voltage V-SW to establish the cell 481 as a switching cell. The switching voltage V-SW is at a low voltage during the programming interval of the first stage, so that the switching memory cell 481 acts as an isolated region 483 and 484 in the semiconductor body. During the first-stage programming interval, which is the bias condition, region 484 in semiconductor body 10 is self-charged to virtual drain voltage Vd by capacitive coupling in response to a target word line between receiving V-PGM and Pass voltage V-PASS (drain terminal) on word line 482 between GSL lines and dummy word lines 401, 402. Region 483 in semiconductor body 10 is precharged to virtual source voltage Vs by coupling bit line 31 to the substrate. The voltage V-PASS (source terminal) is coupled to the word line between the switched word line of the memory cell 481 and the second switch 43 . The voltage V-PASS (source terminal) can be the voltage V-PASS (drain terminal), or a different voltage, depending on the requirements of a particular application or programming condition. The self-boost voltage level in region 484 and the reference voltage level in region 483 are isolated by the depleted region beneath the switching memory cell 181 . As shown, in this case, the dummy drain region 484 is guaranteed to include at least two memory cells below the dummy word lines 401, 402, and thus will have sufficient reprogramming interval to induce a large number of hot carriers. Injected capacitor. It should be noted that the dummy cells can be used as switching cells for programming the memory cells corresponding to the word line 482 when applying the common source terminal as dummy source mode. the

FIG. 13 shows a simplified layout diagram of a NAND gate array similar to that shown in FIG. 12 with dummy word lines DWL1 , DWL2 adjacent to GSL lines, showing word lines and source/drain strings. Thus, the source/drain strings 500-503 extend vertically along the page. Horizontal wires are above the source/drain series 500-503. The horizontal wires include SSL lines, word lines WL0 to WL(n-1), and dummy word lines DWL1, DWL2. In addition, the horizontal wires also include a ground selection line GSL and a common source line CS. the

Figure 14 shows a simplified schematic layout of a NAND array similar to that shown in Figure 12 with dummy word lines on the other side of the array adjacent to the SSL lines, showing word lines and source/drain strings . Thus, the source/drain strings 500-503 extend vertically along the page. Horizontal wires are above the source/drain series 500-503. The horizontal wires include SSL lines, dummy word lines DWL1, DWL2 and word lines WL0 to WL(n-1). In addition, the horizontal wires also include a ground selection line GSL and a common source line CS. the

FIG. 15 shows a simplified layout diagram of a NAND array similar to that shown in FIG. 12 without dummy word lines, showing word lines and source/drain strings. However, the word lines are logically arranged in a set of top word lines TWL0 to TWL(n-1) (only TWL(0) to TWL(4) are shown in the figure) and a set of bottom word lines BWL0 to BTWL (m -1) (only BWL(M-5) to TWL(M-1) are shown in the figure). Thus, when a target cell falls within the top wordline, the programming operation is arranged such that the dummy drain region includes all semiconductor body regions below the bottom wordline. In this case, the programmed performance of hot carrier injection can be improved. the

Figure 16 shows a simplified layout diagram of a NAND gate array similar to that shown in Figure 12 with word lines adjoining GSL lines and dummy word lines adjoining SSL lines, showing word lines and source/drain strings List. Thus, the source/drain strings 500-503 extend vertically along the page. Horizontal wires are above the source/drain series 500-503. The horizontal wires include SSL lines, top wordlines TWL1 and TWL2, wordlines WL0 to WL(n-1), and bottom wordlines BWL1 and BWL2. In addition, the horizontal wires also include a ground selection line GSL and a common source line CS. the

Figures 17 and 18 show schematic diagrams of alternative timing arrangements for the use of programmed intervals to induce the boost node hot carrier injection described herein. These sequences include biasing the string select line SSL to a high level to turn on the second switch when the switching voltage V-SW is low for at least a portion of the first phase of the programming interval, and when When the switching voltage V-SW is at a high level, at least part of the time in the second phase of the programming interval is by switching the string selection line SSL to a low level to close the second switching switch. As shown in FIG. 17, during a programming interval, selected bit lines 31, ground select line GSL, and common source line CS are maintained at ground potential, while unselected bit lines are biased to about VCC . At time 600 at the beginning of this programming interval, the string select line SSL is biased to approximately VCC to couple the semiconductor body to ground. At a short time point 610 after the string select line SSL is switched to VCC, the target word line receives the programming pulse V-PGM potential, and the word line adjacent to the switched memory cell receives a switching voltage V-SW, which is at Low voltage can turn off the switching memory cell, while other word lines along the series of NAND gates receive voltage V-PASS. In this way, dummy source and dummy drain regions are set as shown in FIG. 2A. According to the procedure in FIG. 17 , the string select line SSL switches back to ground at time 602 instead of remaining at VCC throughout the programming interval as in FIG. 3 . The switching voltage V-SW is switched to a high level at time 603 , which may be at the same time as time 602 . The programming interval ends at time 604 when the programming potential along with other signals returns to ground. the

As shown in FIG. 18 , a delay time 606 can be added between the time 602 when the string select line SSL switches back to the ground potential and the time 605 when the switching voltage V-SW switches to the high level. As before, during a programming interval, selected bit lines, ground select line GSL, and common source line CS are maintained at ground potential, while unselected bit lines are biased to approximately VCC. At time 600 at the beginning of this programming interval, the string select line SSL is biased to approximately VCC to couple the semiconductor body to ground. At a short time point 610 after the string select line SSL is switched to VCC, the target word line receives the programming pulse V-PGM potential, while other word lines along the NAND series receive the voltage V-PASS . In this sequence, the switching voltage V-SW is switched to a high level at time 605 after the string select line SSL switches back to ground for a delay time 606 . The programming interval ends at time 604 when the programming potential along with other signals returns to ground. These switching procedures, which turn off both the ground select line GSL and the string select line SSL, can operate at low power. the

Figure 19 shows a simplified schematic diagram of an integrated circuit using the self-boosting virtual drain, hot carrier injection programmed NAND flash memory described herein. The integrated circuit 810 includes a memory array 812 using charge trapping or floating gate memory cells formed, for example, on a semiconductor substrate. A word line (column) and string select decoder (including appropriate drivers) 814 is coupled and in electrical communication with a plurality of word lines 816, string select lines, and ground select lines, and along the memory array 812 Arranged in column direction. The bit line (row) decoder and driver 818 are in electrical communication with a plurality of bit lines 820 and arranged along the row direction of the memory array 812 to read or write data from memory cells (not shown) of the array 812 to it. Addresses are provided by bus 822 to word line and string select decoder 814 and bit line decoder 818 . The sense amplifiers and data input structure in block 824 are coupled to bit line decoder 818 via data bus 826 . Data is provided to the data input line 828 by the input/output port on the integrated circuit 810 , or input to the data input structure in block 824 by other internal/external data sources of the integrated circuit 810 . Other circuits 830 are included in the integrated circuit 810, such as general purpose processors or special purpose application circuits, or modules combined to provide system-on-chip functions supported by the array. Data is provided to the integrated circuit 810 by the sense amplifier in block 824 via the data output line 832 , or to other data terminals inside/outside the integrated circuit 810 . the

The controller 834 used in this embodiment, using the bias adjustment state mechanism 836, controls the application of the bias adjustment supply voltage and current source, such as reading, programming, erasing, erasing confirmation, and programming Verify that a voltage or current is applied to the word line or bit line and use the access control procedure to control the word line/source line operation. The controller also applies switching sequences to induce the boost-node hot-load subprogramming described here. In an alternative embodiment, the controller 834 includes a general purpose processor that can be used on the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 834 is a combination of special purpose logic and a general purpose processor. the

The invention provides a new programming method of NAND flash memory, which can suppress process programming interference due to low operating voltage. Lower operating voltages can be used according to the new programming of hot carrier injection achieved using elevated node potentials. As a result of the lower operating voltage, the driver circuit in this integrated circuit can be implemented using only one MOSFET process without the need for an additional high voltage MOSFET process. the

Compared with conventional channel hot electron injection operation, the bit line voltage does not need to overcome the hot electron injection energy barrier height. Therefore, the bit line voltage can be VCC or other lower voltage than conventional channel hot electron injection (CHE) programming voltage. In addition, the bit lines do not consume DC current during channel hot electron injection. Therefore, this new programming method should be able to achieve low power consumption. the

In addition, the word line voltage of this programming method is also lower than that required for the conventional NAND gate flash memory FN programming operation. Therefore no very high voltage drive means are required. In addition, the vertical electric field across the tunnel oxide in this NAND flash memory is also smaller than that required for FN injection. As a result of the low electric field requirement, the reliability of the device can be improved. the

Further, the lower programming and Vpass voltages required for conventional FN programming operations result in reduced dielectric voltage between wordlines, and thus reduce wordline generation due to the reduced distance between wordlines dielectric breakdown problem. the

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the method and technical content disclosed above to make some changes or modifications to equivalent embodiments with equivalent changes, but if they do not depart from the technical solution of the present invention, Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solutions of the present invention. the

Claims (21)

1. A memory element, characterized in that it comprises: A plurality of memory cells are connected in series in a semiconductor body, a plurality of word lines, the word lines of the plurality of word lines are coupled to the corresponding memory cells of the plurality of memory cells; and The control circuit is coupled to the plurality of bit lines, and the following steps are used to program a selected memory cell among the plurality of memory cells corresponding to a selected word line: applying a pass voltage to word lines on a first side of the selected word line during a programming interval; self-boosting a first semiconductor body region to a self-boosting voltage by capacitive coupling; applying a programming voltage to the selected word line during the programming interval; biasing a second semiconductor body region on a second side of the selected word line to a reference voltage during the programming interval; and Applying a switching voltage to a word line adjacent to the selected word line, the switching voltage has a first phase and a second phase during the programming interval, so that the first phase will be connected to the selected word line The selected memory cell corresponding to the selected word line is isolated from the reference voltage, and the selected memory cell is coupled to the reference voltage in the second stage. 2. The memory device according to claim 1, wherein the selected memory cell corresponding to the selected word line is biased to the switching voltage in the second stage to perform channel hot carrier subprogramming . 3. The memory device according to claim 1, wherein the switching voltage is less than the programming voltage in the second stage. 4. The memory device according to claim 1, wherein said plurality of memory cells are arranged in a series of NAND gates. 5. The memory device according to claim 1, further comprising a first switch located between a bit line and a first side of the plurality of memory cells, and a second switch located between a reference between the line and a second side of the plurality of memory cells, and wherein the control circuit turns on the first switching switch and turns off the second switching switch during the programming period. 6. The memory device according to claim 5, further comprising a second plurality of memory cells coupled to the plurality of word lines, and wherein the control circuit applies a voltage to one and the second plurality of memory cells a second bit line corresponding to the selected word line to isolate a semiconductor body region in the second plurality of memory cells corresponding to the second side of the selected word line, and apply a pass voltage to the selected word The word line corresponding to the second side of the word line self-boosts a semiconductor body region where the second plurality of memory cells are located to a voltage to suppress the second plurality of memories coupled to the selected word line A memory cell in the cell generates hot carriers. 7. The memory device according to claim 5, further comprising an additional memory cell connected in series with the plurality of memory cells in the semiconductor body region and an additional word line, and the additional memory cell is placed on between the plurality of memory cells and the second switch, and when the control circuit applies a pass voltage to the additional word line during the programming interval, the first side of the selected word line The capacitance value of the semiconductor body region is increased. 8. The memory device according to claim 5, wherein said control circuit turns on the second switching switch during the first stage of a part of the switching voltage, and turns on the second switching switch during the second part of the switching voltage. Phase closes the second toggle switch. 9. The memory device according to claim 1, further comprising a first switch positioned between a bit line and a first side of the plurality of memory cells, and a second switch on a reference between the line and a second side of the plurality of memory cells, and wherein the control circuit closes the first switching switch and turns on the second switching switch during the programming period. 10. The memory device according to claim 9, further comprising a second plurality of memory cells coupled to the plurality of word lines and a second bit line, and wherein the control circuit is in the programming interval biasing the second bit line such that a first semiconductor body region in the second plurality of memory cells on the first side of the selected word line and the second bit line on the selected word line A second semiconductor body region in the second plurality of memory cells is biased to a reference voltage to suppress hot carrier generation. 11. The memory device according to claim 9, further comprising an additional memory cell connected in series with the plurality of memory cells in the semiconductor body region and an additional word line, and the additional memory cell is placed on between the plurality of memory cells and the first switch, and when the control circuit applies a pass voltage to the additional word line during the programming interval, the first side of the selected word line The capacitance value of the semiconductor body region is increased. 12. The memory device according to claim 1, wherein said control circuit applies a switching voltage to a plurality of word lines during the programming period. 13. The memory device according to claim 1, wherein the plurality of word lines comprises a first group of word lines near one end of the plurality of memory cells, and a second group of word lines near the ends of the plurality of memory cells. The other end of a memory cell, and the control circuit determines whether the selected word line is in the first group or the second group, and assigns the end of the selected word line to include the first group or the second group. 14. The memory device according to claim 1, wherein the plurality of memory cells connected in series in a semiconductor body are interposed between the first and second switching transistors, and the plurality of word lines comprise a A first string selection line and a second string selection line are respectively coupled to the first and second switching transistors. 15. A memory element, characterized in that it comprises: A series of NAND gates includes a plurality of memory cells connected in series in a semiconductor body; a plurality of word lines, the word lines of the plurality of word lines are coupled to the corresponding memory cells of the plurality of memory cells; and The control circuit is coupled to the plurality of bit lines, and the following steps are used to program a selected memory cell among the plurality of memory cells corresponding to a selected word line: blocking a first semiconductor body region between a first side of the selected memory cell of the NAND series and a second semiconductor body region of a second side of the selected memory cell of the NAND series carrier flow between self-boosting the first semiconductor body region to a self-boosting voltage by capacitive coupling; biasing the second semiconductor body region to a reference voltage; applying a programming potential greater than a hot carrier injection barrier to the selected memory cell; and Enabling carriers flow from the second semiconductor body region to the selected memory cell to generate hot carriers. 16. A NAND gate flash memory selection memory hot carrier injection method, characterized in that it comprises the following steps: blocking a first semiconductor body region between a first side of a selected memory cell of the NAND series and a second semiconductor body region of a second side of the selected memory cell of the NAND series carrier flow between self-boosting the first semiconductor body region to a self-boosting voltage by capacitive coupling; biasing the second semiconductor body region to a reference voltage; applying a programming potential greater than a hot carrier injection barrier to the selected memory cell; and Enabling carriers flow from the second semiconductor body region to the selected memory cell to generate hot carriers. 17. The hot carrier injection method for selected memory of NAND flash memory according to claim 16, characterized in that it includes applying a two-stage switching voltage to the adjacent selected memory cell in the NAND gate series A memory cell including a first stage of turning off the memory cell to implement the blocking, and a second stage of turning on the memory cell to implement the enabling. 18. The hot carrier injection method for selected memory of NAND gate flash memory according to claim 16, wherein said NAND gate series in said NAND gate array includes a first switching switch Between a first side of the NAND gate series and a bit line or a reference line, and a second switching switch between a second side of a plurality of memory cells and the reference line or bit line between, and wherein the self-pressurization includes: closing the first switch in the series of NAND gates including the selected memory cell to isolate the first semiconductor body region and applying a pass voltage to the first switch in the series of NAND gates of the selected memory cell One side is coupled to the word line, the second switching switch is turned on and a reference voltage is applied to the second semiconductor body region through the second switching switch. 19. The hot carrier injection method for the selected memory of the NAND gate flash memory according to claim 18, comprising closing the first and second switches in the non-selected NAND gate series. 20 . The hot carrier injection method for selected memory of a NAND gate flash memory according to claim 18 , comprising turning on the first and second switches in the series of unselected NAND gates. 21 . 21. The hot carrier injection method for selected memory of a NAND flash memory according to claim 16, wherein the NAND series of the array includes a first group of M memory cells and a first two sets of N memory cells and if the selected memory cell is in the first set of M memory cells, biasing the series of NAND gates such that the first semiconductor body region includes at least the second set of N memory cells memory cells, and if the selected memory cell is in the second set of N memory cells, biasing the series of NAND gates such that the first semiconductor body region includes at least the first set of M memory cells .