CN103093811A - Flash memory current limiting device and flash memory using the device - Google Patents

Abstract

The invention discloses a flash memory current limiting device. The flash memory current limiting device is arranged outside a memory cell array of a flash memory and comprises: the device comprises a transmission tube, a reference current generation module and a current limiting unit, wherein the transmission tube is a PMOS tube, the grid end of the transmission tube is connected to a voltage control signal, the drain end of the transmission tube is connected to a voltage PHV required by the erasing operation of the source end of a storage unit in a storage unit array, and the source end of the transmission tube is connected to a source line in the storage unit; the source end of the PMOS tube and the source line of the storage unit are jointly used as one input end of the current limiting unit, and the reference current generated by the reference current generating module is used as the other input end of the current limiting unit. The flash memory current limiting device can save a large amount of chip area because the current limiting device is not integrated in the array.

Description

Flash memory current limiting device and flash memory using the device

technical field

The invention relates to the technical field of memory in the microelectronics industry, in particular to a flash memory current limiting device and a flash memory using the device.

Background technique

Generally speaking, by applying appropriate voltages to the source, drain and control gate of the flash memory cell, the charge will be stored or removed, so data can be stored or stored in the memory cell in the form of this charge. Erased from the memory cell. The presence or absence of charge on the floating gate determines whether current flows between the source and drain regions when the memory cell is selected. By judging the magnitude of the current between the source and drain regions in the memory cell, it is possible to distinguish whether the stored content is "0" or "1". Typically, the bit lines of the flash memory cells in the array are connected to the drains of the memory cells in any specific row, and the word lines are connected to the gates of the memory cells in any specific column. The source of each memory cell is usually connected to ground.

Flash memory not only has the function of reading, but also the function of programming and erasing. To complete these operations, it is necessary to apply a relatively high voltage to the bit line corresponding to the row of the selected memory cell in the memory array. In addition, the word line connected to the row where the selected memory cell is located will also be applied with a high voltage. Its drain and gate are applied with high voltage to generate current to generate charge. However, when performing these operation modes, the drains of the unselected memory cells located in the same row as the selected memory cells will also receive the potential of the high voltage bit line, and the current or leakage current at the time of shutdown may be reduced. flows between the source and drain of these unselected memory cells. Although the leakage current of a single memory cell may be extremely small, the sum of the leakage currents of each unselected memory cell may approach or even exceed the current in the selected memory cell, resulting in device damage. Adding a current limiting device to the storage system can make the sum of the leakage current not exceed the set value, so that the device will not be damaged. But now many storage systems do not have a current limiting solution, or only add a current limiting solution when making devices, or integrate the current limiting solution in the device array.

FIG. 1 is a schematic structural diagram of a current limiting scheme for a flash memory in the prior art. As shown in FIG. 1 , 100 is a memory cell array, and 101 is a PMOS transmission transistor (MP) that acts as a current limiter, wherein, the source terminal of the PMOS transmission transistor (MP) 101 is connected to the adjustable voltage VHB, and its gate terminal is connected to a On a fixed voltage V0 , the substrate voltage is connected to VPP, and the drain end of the PMOS transfer transistor (MP) 101 is connected to the array source line 104 of the memory cell array 100 . The traditional current limiting scheme is to limit the magnitude of the current by changing the voltage VHB on the bit line, and then giving an appropriate voltage V0. However, the change of V0 will cause the threshold voltage of the PMOS transmission transistor (MP) to fluctuate, so that the current limit cannot accurately reach the set value.

FIG. 2 is a structural diagram of using a current limiting device to operate a single memory cell in a flash memory array in the prior art. As shown in FIG. 2 , the flash memory device includes a memory cell array 100 . Each memory cell typically contains a source, drain and gate. The array 100 further includes a plurality of bit lines 102 , such as BL0 , BL1 , . . . BLm, and a plurality of word lines 103 , such as word lines WL0 , WL1 , . . . WLn. Bit lines BL0-BLm are connected to bit line driver circuit 105, word lines WL0-WLn are connected to word line driver circuit 106, high voltage system 107 provides memory cell operation for bit line driver circuit 105, word line driver circuit 106 and current limiting device 108 the required voltage. The voltage generated by the high voltage system 107 is connected to the power signal terminals of the word line driving circuit and the bit line driving circuit, and the voltage generated by the high voltage system 107 is applied to one or more bit lines BL0-BLm through word line and bit line selection. The source lines 104 of the memory array 100 are connected together, and the current limiting device 108 is connected between the array source lines 104 and ground.

FIG. 3 is a schematic diagram of the memory cell array 100 in FIG. 2 . As shown in FIG. 3, array 100 includes a plurality of memory cells 115 arranged in columns and rows. The word lines WL0 , WL1 , . . . WLn have a total of n+1 rows, and the bit lines BL0 , BL1 , . . . BLm have a total of m+1 columns. The respective drains of memory cells 115 and 116 are coupled together and connected to bit line BL0. The memory cells of other columns are connected in the same way to form word lines BL1-BLm, wherein the sources of all memory cells are connected together.

In FIG. 3, cell 115 is the memory cell selected for programming. The selected cell 115 is operated by applying a higher bias voltage to bit line BL0 and word line WL0 and a lower voltage to unselected word lines WL1-WLn and bit lines BL1-BLm. These bias voltages can be, for example, 10V, 5V, 0V, 0V applied to word line WL0, bit line BL0, WL1-WLn, BL1-BLm, respectively. As shown in Figure 3, the high-voltage system 107 transmits the corresponding voltage to the word line driver circuit 106 and the bit line driver circuit 105, and then the word line driver circuit 106 and the bit line driver circuit 105 are respectively applied to the word lines WL0-WLn, the bit line BL0-BLm. In the operational mode, word line WL0 provides a voltage to the control gate of the selected cell 115 and the gate of the unselected memory cell connected to WL0 to facilitate electron injection into the selected memory cell 115 .

For example, 5V is biased to the bit line BL0 , and 10V is biased to the word line WL0 as the voltage required to operate the unit 115 . Since the drains of the unselected cells are connected to the drain of the selected cell 115, those unselected cells 116 also receive the voltage of the bit line BL0 at their respective drains. The bit voltage applied to the respective drains of the unselected memory cells 116 increases the drain-to-source voltage of each of the unselected memory cells 116, and the value of this drain-to-source voltage increases the value of the unselected memory cells 116. Selected cell 116 leakage current. However, according to the specific embodiment, the current limiting device 108 can limit the magnitude of the leakage current. As shown in FIG. 3, with the application of the drain-to-source voltage, each unit in the unselected memory cells 116 generates a leakage current Ioff, which flows in from the drain, and from each unselected memory cell 116 source outflow. The sum of these Ioff currents, together with the leakage current flowing through the selected cell 115, passes through the array source line 104 together. The array source line 104 then passes through the current limiting device 108, thereby limiting the sum of the leakage current so that it does not exceed a desired preset value.

In the process of realizing the present invention, the applicant realized that the prior art has the following defects: 1. The current limiting device of the prior art is integrated in the array, occupying a large area; 2. The existing current limiting device is affected by temperature, etc. Influenced by external conditions, resulting in inaccurate current limiting.

Contents of the invention

(1) Technical problems to be solved

In order to solve one or more of the above problems, the present invention provides a flash memory current limiting device and a flash memory using the device, so as to save the area of the storage array and enable the current limiting to accurately reach the set value.

(2) Technical solutions

According to one aspect of the present invention, a flash memory current limiting device is provided. The flash memory current limiting device is located outside the memory cell array of the flash memory, and includes: a current limiting unit, a transfer transistor and a reference current generation module, wherein the transfer transistor is a PMOS transistor (MP0), and its gate terminal is connected to a voltage control signal, the drain end is connected to the voltage PHV required for the erase operation of the source end of the memory cell in the memory cell array, and the source end is connected to the source line in the memory cell; the source end of the PMOS transistor (MP0) and the source line of the memory cell work together as One input terminal of the current limiting unit, the reference current generated by the reference current generating module is used as the other input terminal of the current limiting unit; if the current of the source line of the storage unit does not exceed the reference current generated by the reference current generating module, the current limiting unit is cut off ; If the current of the source line of the storage unit is greater than the reference current generated by the reference current generating module, the current is discharged to the ground through the current limiting unit.

According to another aspect of the present invention, a flash memory is also provided. The flash memory includes a storage unit and the above-mentioned current limiting device, wherein the storage unit contains a source, a drain and a control gate; each word line corresponds to a column in the storage unit, and the gates of the storage unit correspond to A column in the storage unit; each bit line corresponds to a row in the storage unit, and the drain of the storage unit corresponds to a row in the storage unit; the source of each storage unit shares a source line, the source line Connect with the flow limiting unit and transfer tube.

(3) Beneficial effects

The flash memory current limiting device of the present invention and the flash memory using the device have the following beneficial effects:

(1) In the present invention, since the current limiting device does not need to be integrated in the array, a large amount of chip area can be saved;

(2) In the present invention, since the current mirror circuit is less affected by the process conditions, there is not much difference between the current provided by the outside and the current mirrored by the current mirror, so that the current in the storage unit and the current phase provided by the outside can be accurately Comparison, so that the leakage current can be precisely limited not to exceed a certain value.

Description of drawings

FIG. 1 is a schematic structural diagram of a flash memory current limiting scheme in the prior art;

FIG. 2 is a schematic structural diagram of using a current limiting device in the prior art to operate a single storage unit in a flash memory array;

FIG. 3 is a schematic diagram of the memory cell array 100 in FIG. 2;

FIG. 4 is a schematic diagram of a flash memory current limiting device according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the operating sequence of the flash memory current limiting device in the embodiment of the present invention when the current is not limited;

FIG. 6 is a schematic diagram of an operation sequence during current limiting of the flash memory current limiting device according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The invention provides a flash memory current limiting device. The flash memory current limiting device includes: a transmission tube, a reference current generating module and a current limiting unit. Wherein, the transfer transistor is a PMOS transistor (MP0), its gate end is connected to a voltage control signal, its drain end is connected to the voltage PHV required for the source end erase operation of the memory cell in the memory cell array, and its source end is connected to the memory cell stored in the memory cell array. The source line in the unit; the source end of the PMOS transistor (MP0) and the source line of the storage unit are jointly used as an input end of the current limiting unit, and the reference current generated by the reference current generation module is used as the other input end of the current limiting unit; The output terminal of the current unit is grounded. When the current of the source line of the storage unit is greater than the reference current generated by the reference current generation module, the current is discharged to the ground through the current limiting unit; if the current of the source line of the storage unit does not exceed the reference current When the reference current generated by the module is generated, the current limiting unit is cut off.

FIG. 4 is a schematic diagram of a flash memory current limiting device according to an embodiment of the present invention. As shown in FIG. 4 , the current limiting device 108 includes current limiting transistors MN0 - MN3 and a PMOS transmission transistor MP0 , wherein the drain of the transistor MN2 is connected to the array source line 104 , and the drain of the transistor MN0 is connected to the reference current generating circuit 110 . The control gates of transistors MN0 and MN3 are respectively connected to control signals I_EN and Vbias. The drain of transistor MN0 and the source of transistor MN3 are connected to the gates of transistors MN1, MN2. The source of the transistor MP0 is connected to the source line 104 of the array and the drain of the transistor MN2 , the gate is connected to the control signal Vbias1 , and the drain is connected to the voltage PHV. The current limiting device 108 is used to limit the sum of array source currents within a preset value. Since the sum of the source currents is limited to a preset value, the design difficulty of the external high voltage system is reduced.

During the non-current-limiting operation, the signal control logic of the current-limiting device 108 is shown in FIG. 5 . At time t0, the control signal I_EN is connected to the line 112, the control signal Vbias is connected to the line 113, the control signal Vbias1 is connected to the line 114 at a low level, and at time t4, the control ends. VSL corresponds to the schematic diagram of the voltage of the storage array source 104, MP0 is turned on at t1, and the PHV voltage is transmitted to the storage array source 104; at t4, MP0 is turned off, and the voltage VSL becomes V1 at the storage array source 104.

During the current limiting operation, the signal control logic of the current limiting device 108 is shown in FIG. 6 . At time t0, the voltage of the control signal I_EN is the power supply voltage VCC and connected to the line 112; the voltage of the control signal Vbias is the power supply voltage VCC and connected to the line 113; the voltage of the control signal Vbias1 is high level PHV to cut off MP0, and at the same time connect to line 114. At time t6, the control signals I_EN and Vbias become low level to end the control. Wherein ISL corresponds to the current schematic diagram of the source 107 of the storage array, assuming that due to a certain operation mode, the current ISL increases at time t3, when the total leakage current exceeds Imax, due to the current limiting device 108, the current ISL is discharged to the ground through the MN2 tube , so that the current ISL drops below the current preset value Imax at time t4. Assuming that the total leakage current ISL is not greater than the pre-market value Imax in a certain operation mode, the MN2 in the current limiting device 108 will not discharge the current ISL to the ground through the MN2 tube.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (7)

1. A flash memory current limiting device, characterized in that, the flash memory current limiting device is located outside the storage cell array of the flash memory, including: transmission tube, reference current generation module and current limiting unit, wherein, The transfer transistor is a PMOS transistor (MP0), its gate end is connected to the voltage control signal, its drain end is connected to the voltage PHV required for the source end erase operation of the memory cell in the memory cell array, and its source end is connected to the memory cell the source line; The source terminal of the PMOS transistor (MP0) and the source line of the storage unit are jointly used as an input terminal of the current limiting unit, and the reference current generated by the reference current generating module is used as the other input terminal of the current limiting unit ; The output terminal of the current limiting unit is grounded, and if the current of the source line of the storage unit does not exceed the reference current generated by the reference current generating module, the current limiting unit is cut off; if the current of the source line of the storage unit is greater than the If the reference current generated by the reference current generation module is used, the current is discharged to the ground through the current limiting unit. 2 . The flash memory current limiting device according to claim 1 , wherein the reference current generating module mirrors an external current through a current mirror to generate a reference current. 3 . 3. The flash memory current limiting device according to claim 1, wherein the current limiting unit comprises a first NMOS transistor (MN0), a second NMOS transistor (MN1), a third NMOS transistor (MN2) and The fourth NMOS tube (MN3), wherein: The drain of the first NMOS transistor (MN0) is connected to the reference current generated by the reference current generating module, the control gate is connected to the first control signal I_EN, and the source is connected to the drain of the second NMOS transistor (MN1); The second NMOS transistor (MN1) and the third NMOS transistor (MN2) form a current mirror circuit, the gate of the second NMOS transistor (MN1) is interconnected with the gate of the third NMOS transistor (MN2), and is connected to the first NMOS transistor (MN2). The source connection of the tube (MN0); The drain of the third NMOS transistor (MN2) is connected to the source of the memory cell and the source of the PMOS transmission transistor (MP0), and the gate of the third NMOS transistor (MN2) is connected to the gate of the second NMOS transistor (MN1). Interconnect, source to ground; The drain end of the fourth NMOS transistor (MN3) is connected to the gates of the third NMOS transistor (MN2) and the second NMOS transistor (MN1); its source is grounded, and its control gate is connected to the second control signal Vbias; The control gate of the PMOS transistor (MP0) is connected to the third control signal Vbias1, the source is connected to the high voltage PHV, and the drain is connected to the source line of the memory cell array; If the current of the source line of the storage unit does not exceed the reference current generated by the reference current generation module, the third NMOS transistor (MN2) is turned off; if the current of the source line of the storage unit is greater than the reference current generated by the reference current generation module Referring to the current, the current is discharged to the ground through the third NMOS transistor (MN2). 4. The flash memory current limiting device according to claim 3, characterized in that, when the source line of the storage unit is subjected to a current limiting operation, The first control signal I_EN is connected to the power supply voltage; the second control signal Vbias is connected to the ground level; the third control signal Vbias1 is connected to the high voltage PHV to turn off the PMOS transmission transistor (MP0). 5. The flash memory current limiting device according to claim 3, wherein when the source line of the storage unit is not subjected to a current limiting operation, The first control signal I_EN is connected to the ground voltage; the second control signal Vbias is connected to the power supply voltage; the third control signal Vbias1 is connected to the ground level to turn on the PMOS transmission transistor (MP0). 6. The flash memory current limiting device according to claim 3, wherein: When performing an erase operation, the fourth NMOS transistor (MN3) is turned on, the third NMOS transistor (MN2) is turned off, and the PHV voltage is transmitted to the source terminal of the memory cell through the first NMOS transistor (MN0); When performing programming and reading operations, the fourth NMOS transistor (MN3) is turned off, and the third NMOS transistor (MN2) is turned on. When the total leakage current exceeds a preset value, the current flows to the ground through the third NMOS transistor (MN2). 7. A flash memory, characterized in that it comprises a storage unit and the current limiting device according to any one of claims 1 to 6, A memory cell has a source, a drain, and a control gate; Each word line corresponds to a column in the storage unit, and the gate of the storage unit corresponds to a column in the storage unit; Each bit line corresponds to a row in the storage unit, and the drain of the storage unit corresponds to a row in the storage unit; The source of each storage unit shares a source line, which is connected to the current limiting unit and the transmission tube.

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