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CN103021883A - Flat package part manufacturing process based on corrosion plastic package body - Google Patents

Flat package part manufacturing process based on corrosion plastic package body Download PDF

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Publication number
CN103021883A
CN103021883A CN2012105232947A CN201210523294A CN103021883A CN 103021883 A CN103021883 A CN 103021883A CN 2012105232947 A CN2012105232947 A CN 2012105232947A CN 201210523294 A CN201210523294 A CN 201210523294A CN 103021883 A CN103021883 A CN 103021883A
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plastic
plastic sealing
package
frame
manufacturing process
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王虎
郭小伟
谌世广
朱文辉
马晓波
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Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本发明涉及一种基于腐蚀塑封体的扁平封装件制作工艺,属于集成电路封装技术领域。本发明采用的不同于以往的塑封工艺,在框架上用腐蚀的方法形成凹槽后,采用二次塑封的方法在框架与一次塑封料、二次塑封料之间形成有效的防拖拉结构,大大降低封装件分层情况的发生几率,极大提高产品可靠性,优于传统AQQFN产品的塑封效果。

Figure 201210523294

The invention relates to a manufacturing process of a flat package based on a corroded plastic package, and belongs to the technical field of integrated circuit packaging. The present invention adopts different from the previous plastic sealing process. After the grooves are formed on the frame by corrosion method, an effective anti-drag structure is formed between the frame and the primary plastic sealing compound and the secondary plastic sealing compound by the method of secondary plastic sealing, which greatly Reduce the probability of package delamination, greatly improve product reliability, better than the plastic sealing effect of traditional AQQFN products.

Figure 201210523294

Description

一种基于腐蚀塑封体的扁平封装件制作工艺A manufacturing process of flat package based on corroded plastic package

技术领域 technical field

本发明涉及一种基于腐蚀塑封体的扁平封装件制作工艺,属于集成电路封装技术领域。 The invention relates to a manufacturing process of a flat package based on a corroded plastic package, and belongs to the technical field of integrated circuit packaging.

背景技术     Background technique

集成电路是信息产业和高新技术的核心,是经济发展的基础。集成电路封装是集成电路产业的主要组成部分,它的发展一直伴随着其功能和器件数的增加而迈进。自20世纪90年代起,它进入了多引脚数、窄间距、小型薄型化的发展轨道。无载体栅格阵列封装(即AAQFN)是为适应电子产品快速发展而诞生的一种新的封装形式,是电子整机实现微小型化、轻量化、网络化必不可少的产品。 Integrated circuits are the core of the information industry and high-tech, and the foundation of economic development. Integrated circuit packaging is the main component of the integrated circuit industry, and its development has been accompanied by the increase in its functions and device count. Since the 1990s, it has entered the development track of multi-pin count, narrow pitch, and miniaturization. Carrierless grid array package (AAQFN) is a new packaging form born to adapt to the rapid development of electronic products, and it is an indispensable product for the realization of miniaturization, light weight and networking of electronic machines.

    无载体栅格阵列封装元件,底部没有焊球,焊接时引脚直接与PCB板连接,与PCB的电气和机械连接是通过在PCB焊盘上印刷焊膏,配合SMT回流焊工艺形成的焊点来实现的。该技术封装可以在同样尺寸条件下实现多引脚、高密度、小型薄型化封装,具有散热性、电性能以及共面性好等特点。 There are no carrier grid array package components, no solder balls at the bottom, and the pins are directly connected to the PCB board when soldering. The electrical and mechanical connection to the PCB is through printing solder paste on the PCB pads, and the solder joints formed by the SMT reflow process. to achieve. This technology package can realize multi-pin, high-density, small and thin package under the same size condition, and has the characteristics of heat dissipation, electrical performance and good coplanarity.

AAQFN封装产品适用于大规模、超大规模集成电路的封装。AAQFN封装的器件大多数用于手机、网络及通信设备、数码相机、微机、笔记本电脑和各类平板显示器等高档消费品市场。掌握其核心技术,具备批量生产能力,将大大缩小国内集成电路产业与国际先进水平的差距,该产品有着广阔市场应用前景。 AAQFN packaging products are suitable for packaging of large-scale and ultra-large-scale integrated circuits. Most of the AAQFN packaged devices are used in high-end consumer markets such as mobile phones, network and communication equipment, digital cameras, microcomputers, notebook computers and various flat panel displays. Mastering its core technology and having mass production capacity will greatly narrow the gap between the domestic integrated circuit industry and the international advanced level. This product has a broad market application prospect.

但是由于技术难度等限制,目前AAQFN产品在市场上的推广有一定难度,尤其是在可靠性方面,直接影响产品的使用及寿命,已成为AAQFN封装件的技术攻关难点。 However, due to limitations such as technical difficulties, it is currently difficult to promote AAQFN products in the market, especially in terms of reliability, which directly affects the use and life of products, and has become a technical difficulty for AAQFN packages.

发明内容 Contents of the invention

为了克服上述现有技术存在的问题,本发明提供一种基于腐蚀塑封体的扁平封装件制作工艺,使集成电路框架与塑封体结合更加牢固,不受外界环境影响,直接提高产品的封装可靠性,并在一定程度上降低成本。 In order to overcome the above-mentioned problems in the prior art, the present invention provides a flat package manufacturing process based on corroded plastic packages, which makes the combination of the integrated circuit frame and the plastic package more firm, free from the influence of the external environment, and directly improves the packaging reliability of the product , and reduce costs to a certain extent.

本发明采用的技术方案:一种基于腐蚀塑封体的扁平封装件制作工艺,具体按照以下步骤进行: The technical scheme adopted in the present invention: a flat package manufacturing process based on corroded plastic packaging, specifically carried out according to the following steps:

第一步、减薄:减薄厚度为50μm~200μm; The first step, thinning: the thinning thickness is 50 μm to 200 μm;

第二步、划片:150μm以上晶圆采用普通QFN划片工艺,厚度在150μm以下晶圆,使用双刀划片机及其工艺; The second step, dicing: the wafer above 150μm adopts the ordinary QFN dicing process, and the wafer with the thickness below 150μm uses a double-knife dicing machine and its process;

第三步、上芯:采用粘片胶上芯; The third step, core: use adhesive film to glue the core;

第四步、压焊; The fourth step, pressure welding;

第五步、一次塑封:用传统塑封料进行塑封; The fifth step, one-time plastic sealing: use traditional plastic sealing compound for plastic sealing;

第六步、框架蚀刻凹槽:用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内; The sixth step, frame etching groove: use ferric chloride solution to do partial window half-etching on the back of the frame to form a groove, and the depth is controlled within half of the thickness of the frame;

第七步、回流焊; The seventh step, reflow soldering;

第八步、二次塑封:二次塑封使用30~32um颗粒度的塑封料填充; The eighth step, secondary plastic sealing: the secondary plastic sealing is filled with plastic sealing compound with a particle size of 30~32um;

第九步、腐蚀塑封体:用硫酸和发烟硝酸混合液腐蚀塑封体; The ninth step, corrode the plastic package: corrode the plastic package with a mixture of sulfuric acid and fuming nitric acid;

第十步、后固化、磨胶、锡化、打印、产品分离、检验、包装。 The tenth step is post-curing, grinding, tinning, printing, product separation, inspection, and packaging.

所述的步骤中第三步可采用胶膜片(DAF)代替粘片胶;所述的步骤中第四步、第五步、第七步、第十步均与常规AAQFN工艺相同。 In the third step of the above-mentioned steps, the adhesive film (DAF) can be used instead of the adhesive film; the fourth, fifth, seventh, and tenth steps of the above-mentioned steps are all the same as the conventional AAQFN process.

本发明的有益效果:本发明先在框架上用腐蚀的方法形成凹槽,第一次塑封是塑封料填充进凹槽,背面蚀刻后,再进行植球,最后进行二次塑封,可以有效降低产品整体厚度,适应发展需求;尤其是第二次塑封的塑封料可以与第一次塑封的塑封料和框架间形成更加有效的防拖拉结构,显著提高封装件的可靠性,且此法易行,生产效率高。 Beneficial effects of the present invention: In the present invention, grooves are first formed on the frame by means of corrosion, the first plastic sealing is to fill the grooves with plastic sealing compound, after the back is etched, then the balls are planted, and finally the secondary plastic sealing is performed, which can effectively reduce the The overall thickness of the product meets the needs of development; especially, the plastic sealing compound of the second plastic sealing can form a more effective anti-drag structure with the plastic sealing compound of the first plastic sealing and the frame, which significantly improves the reliability of the package, and this method is easy to implement ,high productivity.

附图说明 Description of drawings

图1  引线框架剖面图; Figure 1 Sectional view of the lead frame;

图2  上芯后产品剖面图; Figure 2 Sectional view of the product after core loading;

图3  压焊后产品剖面图; Figure 3 Cross-sectional view of the product after pressure welding;

图4  一次塑封后产品剖面图; Figure 4 Product profile after one-time plastic sealing;

图5  框架背面蚀刻后产品剖面图; Figure 5 Product profile after etching on the back of the frame;

图6  刷锡膏回流焊后产品剖面图; Figure 6 Product profile after reflow soldering with solder paste;

图7  二次塑封后产品剖面图; Figure 7 Product profile after secondary plastic sealing;

图8  腐蚀后产品剖面图; Figure 8 Sectional view of the product after corrosion;

图9  产品成品剖面。 Figure 9 Profile of the finished product.

图中:1-引线框架、2-粘片胶、3-芯片、4-键合线、5-第一次塑封体、6-蚀刻凹槽、7-锡球、8-第二次塑封体。 In the figure: 1-lead frame, 2-adhesive, 3-chip, 4-bonding wire, 5-first plastic package, 6-etching groove, 7-solder ball, 8-second plastic package .

具体实施方式 Detailed ways

下面结合附图和实施例对本发明做进一步说明,以方便技术人员理解。 The present invention will be further described below in conjunction with the accompanying drawings and embodiments, so as to facilitate the understanding of technical personnel.

如图1-9所示:采用本发明所述的方法用于单芯片封装,产品包括引线框架1、粘片胶2、芯片3、键合线4、第一次塑封体5、蚀刻凹槽6、锡球7、第二次塑封体8;其中芯片3与引线框架1通过粘片胶2相连,键合线4直接从芯片3打到引线框架1上,引线框架1上是粘片胶2,粘片胶2上是芯片3,芯片3上的焊点与内引脚间的焊线是键合线4,第一次塑封体5包围了引线框架1、粘片胶2、芯片3、键合线4、蚀刻凹槽6、锡球7构成了电路的整体,第一次塑封体5对芯片3的键合线4和锡球7起到了支撑和保护作用,芯片3、键合线4、引线框架1和锡球7构成了电路的电源和信号通道。 As shown in Figures 1-9: the method of the present invention is used for single-chip packaging, and the product includes a lead frame 1, a die-bonding glue 2, a chip 3, a bonding wire 4, the first plastic package 5, and an etching groove 6. Solder balls 7, the second plastic package 8; wherein the chip 3 is connected to the lead frame 1 through the adhesive 2, and the bonding wire 4 is directly hit from the chip 3 to the lead frame 1, and the lead frame 1 is the adhesive 2. Chip 3 is on the adhesive 2, and the bonding wire between the solder joint on the chip 3 and the inner pin is the bonding wire 4. The plastic package 5 surrounds the lead frame 1, the adhesive 2, and the chip 3 for the first time. , the bonding wire 4, the etching groove 6, and the solder ball 7 constitute the whole circuit, and the first plastic package 5 plays a role of supporting and protecting the bonding wire 4 and the solder ball 7 of the chip 3, and the chip 3, bonding The wire 4, the lead frame 1 and the solder ball 7 constitute the power supply and signal channel of the circuit.

一种基于腐蚀塑封体的扁平封装件制作工艺,先在框架上用腐蚀的方法形成凹槽,第一次塑封是塑封料填充进凹槽,背面蚀刻后,再进行植球,最后进行二次塑封,具体按照以下步骤进行; A flat package manufacturing process based on corroded plastic packaging. First, grooves are formed on the frame by corrosion. The first plastic packaging is to fill the grooves with plastic compound. After the back is etched, ball planting is performed, and finally the second Plastic sealing, specifically follow the steps below;

实施例1 Example 1

第一步、减薄:减薄厚度为50μm~200μm; The first step, thinning: the thinning thickness is 50 μm to 200 μm;

第二步、划片:采用厚度为100μm的晶圆,使用双刀划片机及其工艺; The second step, dicing: use a wafer with a thickness of 100 μm, use a double-knife dicing machine and its process;

第三步、上芯:采用粘片胶2上芯; The third step, core: use adhesive 2 to core;

第四步、压焊:与常规AAQFN工艺相同; The fourth step, pressure welding: the same as the conventional AAQFN process;

第五步、一次塑封:用传统塑封料9920进行塑封,与常规AAQFN工艺相同; The fifth step, one-time plastic sealing: use traditional plastic sealing compound 9920 for plastic sealing, which is the same as the conventional AAQFN process;

第六步、框架蚀刻凹槽:用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内; The sixth step, frame etching groove: use ferric chloride solution to do partial window half-etching on the back of the frame to form a groove, and the depth is controlled within half of the thickness of the frame;

第七步、回流焊:与常规AAQFN工艺相同; The seventh step, reflow soldering: the same as the conventional AAQFN process;

第八步、二次塑封:二次塑封使用30um颗粒度的塑封料填充; The eighth step, secondary plastic sealing: the secondary plastic sealing is filled with 30um particle size plastic sealing compound;

第九步、腐蚀塑封体:用硫酸和发烟硝酸混合液腐蚀塑封体,溶液不会和锡球反应。此法能更好的保护锡球,提高封装良率; The ninth step, corroding the plastic package: corrode the plastic package with a mixture of sulfuric acid and fuming nitric acid, the solution will not react with the solder ball. This method can better protect the solder balls and improve the packaging yield;

第十步、后固化、磨胶、锡化、打印、产品分离、检验、包装与常规AAQFN工艺相同。 The tenth step, post-curing, grinding, tinning, printing, product separation, inspection, and packaging are the same as the conventional AAQFN process.

实施例2 Example 2

第一步、减薄:减薄厚度为50μm~200μm; The first step, thinning: the thinning thickness is 50 μm to 200 μm;

第二步、划片:采用厚度为130μm的晶圆,使用双刀划片机及其工艺; The second step, dicing: use a wafer with a thickness of 130 μm, use a double-knife dicing machine and its process;

第三步、上芯:采用粘片胶2上芯; The third step, core: use adhesive 2 to core;

第四步、压焊:与常规AAQFN工艺相同; The fourth step, pressure welding: the same as the conventional AAQFN process;

第五步、一次塑封:用传统塑封料9920进行塑封,与常规AAQFN工艺相同; The fifth step, one-time plastic sealing: use traditional plastic sealing compound 9920 for plastic sealing, which is the same as the conventional AAQFN process;

第六步、框架蚀刻凹槽:用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内; The sixth step, frame etching groove: use ferric chloride solution to do partial window half-etching on the back of the frame to form a groove, and the depth is controlled within half of the thickness of the frame;

第七步、回流焊:与常规AAQFN工艺相同; The seventh step, reflow soldering: the same as the conventional AAQFN process;

第八步、二次塑封:二次塑封使用31um颗粒度的塑封料填充; The eighth step, secondary plastic sealing: the secondary plastic sealing is filled with 31um particle size plastic sealing compound;

第九步、腐蚀塑封体:用硫酸和发烟硝酸混合液腐蚀塑封体,溶液不会和锡球反应。此法能更好的保护锡球,提高封装良率; The ninth step, corroding the plastic package: corrode the plastic package with a mixture of sulfuric acid and fuming nitric acid, the solution will not react with the solder ball. This method can better protect the solder balls and improve the packaging yield;

第十步、后固化、磨胶、锡化、打印、产品分离、检验、包装与常规AAQFN工艺相同。 The tenth step, post-curing, grinding, tinning, printing, product separation, inspection, and packaging are the same as the conventional AAQFN process.

实施例3 Example 3

第一步、减薄:减薄厚度为50μm~200μm; The first step, thinning: the thinning thickness is 50 μm to 200 μm;

第二步、划片:采用厚度为170μm的晶圆,同普通QFN划片工艺相同; The second step, dicing: use a wafer with a thickness of 170 μm, which is the same as the ordinary QFN scribing process;

第三步、上芯:采用粘片胶2上芯; The third step, core: use adhesive 2 to core;

第四步、压焊:与常规AAQFN工艺相同; The fourth step, pressure welding: the same as the conventional AAQFN process;

第五步、一次塑封:用传统塑封料9920进行塑封,与常规AAQFN工艺相同; The fifth step, one-time plastic sealing: use traditional plastic sealing compound 9920 for plastic sealing, which is the same as the conventional AAQFN process;

第六步、框架蚀刻凹槽:用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内; The sixth step, frame etching groove: use ferric chloride solution to do partial window half-etching on the back of the frame to form a groove, and the depth is controlled within half of the thickness of the frame;

第七步、回流焊:与常规AAQFN工艺相同; The seventh step, reflow soldering: the same as the conventional AAQFN process;

第八步、二次塑封:二次塑封使用32um颗粒度的塑封料填充; The eighth step, secondary plastic sealing: the secondary plastic sealing is filled with 32um particle size plastic sealing compound;

第九步、腐蚀塑封体:用硫酸和发烟硝酸混合液腐蚀塑封体,溶液不会和锡球反应。此法能更好的保护锡球,提高封装良率; The ninth step, corroding the plastic package: corrode the plastic package with a mixture of sulfuric acid and fuming nitric acid, the solution will not react with the solder ball. This method can better protect the solder balls and improve the packaging yield;

第十步、后固化、磨胶、锡化、打印、产品分离、检验、包装与常规AAQFN工艺相同。 The tenth step, post-curing, grinding, tinning, printing, product separation, inspection, and packaging are the same as the conventional AAQFN process.

本发明通过具体实施过程进行说明的,在不脱离本发明范围的情况下,还可以对本发明专利进行各种变换及等同代替,因此,本发明专利不局限于所公开的具体实施过程,而应当包括落入本发明专利权利要求范围内的全部实施方案。 The present invention is described through a specific implementation process. Without departing from the scope of the present invention, various transformations and equivalent substitutions can also be made to the patent of the present invention. Therefore, the patent of the present invention is not limited to the disclosed specific implementation process, but should be All embodiments falling within the scope of the patent claims of the present invention are included.

Claims (3)

1.一种基于腐蚀塑封体的扁平封装件制作工艺,其特征在于:具体按照以下步骤进行: 1. A flat package manufacturing process based on corroded plastic seals, characterized in that: specifically follow the steps below: 第一步、减薄:减薄厚度为50μm~200μm; The first step, thinning: the thinning thickness is 50 μm to 200 μm; 第二步、划片:150μm以上晶圆采用普通QFN划片工艺,厚度在150μm以下晶圆,使用双刀划片机及其工艺; The second step, dicing: the wafer above 150μm adopts the ordinary QFN dicing process, and the wafer with the thickness below 150μm uses a double-knife dicing machine and its process; 第三步、上芯:采用粘片胶上芯; The third step, core: use adhesive film to glue the core; 第四步、压焊; The fourth step, pressure welding; 第五步、一次塑封:用传统塑封料进行塑封; The fifth step, one-time plastic sealing: use traditional plastic sealing compound for plastic sealing; 第六步、框架蚀刻凹槽:用三氯化铁溶液在框架背面做局部开窗半蚀刻,形成凹槽,深度控制在框架厚度的一半以内; The sixth step, frame etching groove: use ferric chloride solution to do partial window half-etching on the back of the frame to form a groove, and the depth is controlled within half of the thickness of the frame; 第七步、回流焊; The seventh step, reflow soldering; 第八步、二次塑封:二次塑封使用30~32um颗粒度的塑封料填充; The eighth step, secondary plastic sealing: the secondary plastic sealing is filled with plastic sealing compound with a particle size of 30~32um; 第九步、腐蚀塑封体:用硫酸和发烟硝酸混合液腐蚀塑封体; The ninth step, corrode the plastic package: corrode the plastic package with a mixture of sulfuric acid and fuming nitric acid; 第十步、后固化、磨胶、锡化、打印、产品分离、检验、包装。 The tenth step is post-curing, grinding, tinning, printing, product separation, inspection, and packaging. 2.根据权利要求1所述的一种基于腐蚀塑封体的扁平封装件制作工艺,其特征在于:所述的步骤中第三步可采用胶膜片(DAF)代替粘片胶。 2 . The manufacturing process of a flat package based on corroded plastic package according to claim 1 , characterized in that: in the third step of the steps, an adhesive film (DAF) can be used instead of the adhesive. 3.根据权利要求1所述的一种基于腐蚀塑封体的扁平封装件制作工艺,其特征在于:所述的步骤中第四步、第五步、第七步、第十步均与常规AAQFN工艺相同。 3. A kind of flat package manufacturing process based on corroded plastic package according to claim 1, it is characterized in that: the fourth step, the fifth step, the seventh step and the tenth step in the described steps are all the same as the conventional AAQFN The process is the same.
CN2012105232947A 2012-12-09 2012-12-09 Flat package part manufacturing process based on corrosion plastic package body Pending CN103021883A (en)

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CN104037093A (en) * 2014-05-14 2014-09-10 华天科技(西安)有限公司 Package part based on secondary exposure and secondary plastic package of AAQFN and manufacturing process thereof
CN106784268A (en) * 2016-11-25 2017-05-31 安徽巨合电子科技有限公司 A kind of miniature three-primary color LED and its method for packing without substrate package
CN111162016A (en) * 2019-12-27 2020-05-15 长电科技(宿迁)有限公司 A packaging method for temporary bonding and reinforcement of lead frame

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CN102365737A (en) * 2009-03-30 2012-02-29 凸版印刷株式会社 Method of producing substrate for semiconductor element, and semiconductor device
CN101958300B (en) * 2010-09-04 2012-05-23 江苏长电科技股份有限公司 Double-sided graphic chip inversion module packaging structure and packaging method thereof
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CN104037093A (en) * 2014-05-14 2014-09-10 华天科技(西安)有限公司 Package part based on secondary exposure and secondary plastic package of AAQFN and manufacturing process thereof
CN106784268A (en) * 2016-11-25 2017-05-31 安徽巨合电子科技有限公司 A kind of miniature three-primary color LED and its method for packing without substrate package
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