CN202384324U - Semiconductor package-in-package (PiP) system structure - Google Patents

Abstract

The utility model discloses a packaging system structure in semiconductor packaging. The package system structure in the semiconductor package includes a lead frame, a first metal material layer, a second metal material layer, an IC chip with bumps, a wire-bonded IC chip, an insulating filling material, an adhesive material and a plastic packaging material. The lead frame includes a chip carrier and a plurality of pins arranged in multiple turns around the chip carrier. The first metal material layer and the second metal material layer are respectively arranged on the upper surface and the lower surface of the lead frame. The insulating filling material is disposed under the stepped structure of the lead frame. A wire-bonded IC chip is disposed on a chip carrier. The IC chips with bumps are flip-chip welded on the inner pins of the multi-turn pins, and the IC chips with bumps and wire-bonded IC chips are covered with plastic packaging materials to form a package system structure in semiconductor packaging. The utility model is a three-dimensional packaging structure with high reliability, low cost and high I/O density based on QFN packaging.

Description

Package system structure in a semiconductor package

technical field

The utility model relates to the technical field of manufacturing semiconductor components, in particular to a semiconductor package-in-package (Package in Package, PiP) system structure based on QFN packaging.

Background technique

With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portability, ultra-thinness, multimedia and low-cost requirements for popularization, high-density, high-performance, high-reliability and low-cost packaging forms and Its assembly technology has been developed rapidly. Compared with the expensive BGA and other packaging forms, the new packaging technology developed rapidly in recent years, that is, the quad flat non-lead QFN (Quad Flat Non-lead Package) package, due to its good thermal and electrical properties, small size, Many advantages such as low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology.

剖面的剖面示意图，该QFN封装结构包括引线框架11，塑封材料12，粘片材料13，IC芯片14，金属导线15，其中引线框架11包括芯片载体111和围绕芯片载体111四周排列的引脚112，IC芯片14通过粘片材料13固定在芯片载体111上，IC芯片13与四周排列的引脚112通过金属导线15实现电气连接，塑封材料12对IC芯片14、金属导线15和引线框架11进行包封以达到保护和支撑的作用，引脚112裸露在塑封材料12的底面，通过焊料焊接在PCB等电路板上以实现与外界的电气连接。底面裸露的芯片载体111通过焊料焊接在PCB等电路板上，具有直接散热通道，可以有效释放IC芯片14产生的热量。与传统的TSOP和SOIC封装相比，QFN封装不具有鸥翼状引线，导电路径短，自感系数及阻抗低，从而可提供良好的电性能，可满足高速或者微波的应用。裸露的芯片载体提供了卓越的散热性能。Fig. 1A and Fig. 1B are the rear schematic view and the edge view of the traditional QFN package structure respectively.

A cross-sectional schematic diagram of a section, the QFN package structure includes a lead frame 11, a plastic packaging material 12, a bonding material 13, an IC chip 14, and a metal wire 15, wherein the lead frame 11 includes a chip carrier 111 and pins 112 arranged around the chip carrier 111 The IC chip 14 is fixed on the chip carrier 111 through the adhesive sheet material 13, the IC chip 13 and the pins 112 arranged around are electrically connected through the metal wire 15, and the plastic packaging material 12 is used for the IC chip 14, the metal wire 15 and the lead frame 11. Encapsulated to achieve the function of protection and support, the pins 112 are exposed on the bottom surface of the plastic encapsulation material 12, and are soldered to a circuit board such as a PCB by solder to realize electrical connection with the outside world. The chip carrier 111 exposed on the bottom surface is welded on a circuit board such as a PCB by solder, and has a direct heat dissipation channel, which can effectively release the heat generated by the IC chip 14 . Compared with traditional TSOP and SOIC packages, QFN packages do not have gull-wing leads, have short conductive paths, low self-inductance and low impedance, thereby providing good electrical performance and meeting high-speed or microwave applications. Exposed chip carrier provides excellent thermal performance.

With the improvement of IC integration and the continuous enhancement of functions, the number of I/Os of ICs increases, and the number of I/O pins of corresponding electronic packages also increases accordingly, and gradually changes from traditional two-dimensional planar packaging to more The development of highly integrated three-dimensional three-dimensional packaging forms, the traditional quadrilateral flat no-lead package is a typical two-dimensional planar packaging form, and the pins of a single circle are arranged around the chip carrier in a peripheral arrangement, which limits the increase in the number of I/Os and meets There is no need for ICs with high density and more I/O counts. The traditional lead frame has no step structure design, which cannot effectively lock the plastic material, resulting in low bonding strength between the lead frame and the plastic packaging material, which is easy to cause delamination of the lead frame and the plastic packaging material or even the falling off of the pin or chip carrier, and cannot effectively It prevents moisture from diffusing into the interior of the electronic package along the bonding interface between the lead frame and the plastic encapsulation material, thereby seriously affecting the reliability of the package. Traditional QFN products need to paste tape on the back of the lead frame in advance to prevent overflow during the plastic packaging process. After plastic packaging, cleaning processes such as removing the tape and molding compound flash need to be performed, which increases the packaging cost. Use a dicing knife to cut and separate traditional quad flat no-lead packages. The dicing knife will also cut the lead frame metal while cutting the plastic packaging material, which will not only reduce the cutting efficiency and shorten the life of the dicing blade, but also produce metal burrs. , affecting the reliability of the package. Therefore, in order to break through the bottleneck of low I/O quantity of traditional QFN, improve the reliability of the package body and reduce the packaging cost, it is urgent to develop a three-dimensional packaging structure based on QFN packaging with high reliability, low cost and high I/O density. and methods of manufacture thereof.

Utility model content

The utility model provides a semiconductor package-in-package (Package inPackage, PiP) system structure and manufacturing method based on QFN packaging, so as to achieve the purpose of breaking through the bottleneck of the low I/O quantity of the traditional QFN and improving the reliability of the package .

In order to achieve the above object, the utility model adopts the following technical solutions:

The utility model proposes a semiconductor package-in-package (PiP) system structure, which includes a lead frame, a first metal material layer, a second metal material layer, an IC chip with bumps, a wire-bonded IC chip, metal wires, an insulating Filling materials, pasting materials and molding materials. The lead frame has a stepped structure along the thickness direction, and has an upper surface, a lower surface and a stepped surface. The lead frame includes a chip carrier and a plurality of pins arranged in multiple turns around the chip carrier. The chip carrier is arranged in the central part of the lead frame, and the four edge parts of the chip carrier have a stepped structure along the thickness direction. The cross-sectional shape of the leads arranged in multiple circles around the chip carrier is circular or rectangular, wherein each lead includes an inner lead arranged on the upper surface and an outer lead arranged on the lower surface. The first metal material layer and the second metal material layer are arranged on the upper surface and the lower surface of the lead frame respectively. The edge filling material is arranged under the stepped structure of the lead frame, supports and protects the lead frame, and exposes the second metal material layer arranged on the lower surface of the lead frame. The wire-bonded IC chip is arranged on the first metal material layer on the upper surface of the lead frame through the adhesive sheet material, and is arranged on the central part of the chip carrier, and the multiple bonding pads on the wire-bonded IC chip are passed through the metal material layer. The wires are respectively connected to the inner pins of the multiple pins configured with the first metal material layer, and the plastic encapsulation material covers the wire-bonded IC chip, the paste material, the metal wire, the chip carrier and the multiple pins with the first metal material layer. pins to form a package. IC chips with bumps are placed on the inner pins of multiple pins with metal material layers through flip-chip mounting equipment, and the bumps on the IC chip are connected to the inner pins of the multi-turn pins by reflow soldering or thermocompression welding. Pin connection, the IC chip with bumps is arranged on the package after the first plastic sealing through the adhesive material, and the plastic sealing material covers the IC chip with bumps, the bumps, the package after the first plastic sealing, the adhesive material and A plurality of pins with a first layer of metal material forming an array of products.

According to an embodiment of the present invention, a semiconductor package-in-package (PiP) system architecture includes two packages.

Utility model According to an embodiment of the utility model, the lead frame has a plurality of pins arranged in three circles around the chip carrier.

According to an embodiment of the present invention, the chip carrier and the pins arranged in three circles around the chip carrier have a stepped structure.

According to an embodiment of the present invention, the cross-sectional shape of the pins arranged in three circles around the chip carrier is circular.

According to an embodiment of the present invention, the cross-sectional shape of the pins arranged in three circles around the chip carrier is rectangular.

According to an embodiment of the present invention, the pins on each side of the chip carrier are arranged in parallel.

According to an embodiment of the present invention, the pins on each side of the chip carrier are arranged in a staggered manner.

According to an embodiment of the present invention, the upper surface and the lower surface of the lead frame are respectively provided with a first metal material layer and a second metal material layer.

According to an embodiment of the present invention, the first metal material layer and the second metal material layer disposed on the upper surface and the lower surface of the lead frame respectively include nickel (Ni), palladium (Pd), and gold (Au) metal materials.

According to an embodiment of the present invention, the flip-chip soldering of the IC chip with bumps is arranged on the inner pins of the plurality of pins with the first metal material layer through the flip-chip on-chip equipment, and the bumps on the IC chip pass through Reflow soldering or thermocompression soldering for inner pin connections with multiple pins.

According to the embodiment of the present invention, the wire-bonded IC chip is arranged on the chip carrier through a heat-conducting adhesive material, and the IC chip with bumps is arranged on the package after the first plastic sealing.

According to an embodiment of the present invention, a wire bonded IC chip package has pins arranged in two circles. According to an embodiment of the present invention, the bumps on the IC chip with bumps are arranged in a single circle, and are respectively soldered and arranged on the outermost circle of the pins arranged in three circles.

According to an embodiment of the present invention, the bumps on the IC chip are lead-free solder bumps, lead-containing solder bumps or metal bumps.

According to an embodiment of the present invention, the wire-bonded IC chip is disposed between the IC chip with bumps and the lead frame.

According to an embodiment of the present invention, the insulating filling material is disposed under the stepped structure of the lead frame.

According to an embodiment of the present invention, the type of insulating filling material arranged under the stepped structure of the lead frame is a thermosetting plastic sealing material, or materials such as plugging resin, ink, and solder resist green oil.

The utility model proposes a manufacturing method of a semiconductor package-in-package (PiP) system structure, comprising the following steps:

Step 1: Configure the mask material layer

The sheet substrate is cleaned and pretreated, and a mask material layer pattern with windows is arranged on the upper surface and the lower surface of the sheet substrate.

Step 2: Configure the metal material layer

The first metal material layer and the second metal material layer are respectively arranged in the windows of the mask material layer arranged on the upper surface and the lower surface of the sheet substrate.

Step 3: Selective Partial Etching of Lower Surface

The mask material layer on the lower surface of the sheet substrate is removed, and the second metal material layer is used as a resist layer to selectively partially etch the lower surface of the sheet substrate to form grooves.

Step 4: Configure Insulation Filling Material

The insulating material is filled in the groove formed by selective half-etching under the sheet substrate.

Step 5: Selective Partial Etching of Upper Surface

Remove the mask material layer on the upper surface of the thin plate substrate, use the first metal material layer as the corrosion resistance layer, and selectively partially etch the upper surface of the thin plate substrate to form a lead frame with a stepped structure, including a separated chip carrier and multiturn pins.

Step 6: Configuring the Wire Bonded IC Chip

The wire-bonded IC chip is placed in the center of the chip carrier through a thermally conductive adhesive material such as epoxy resin containing silver particles or tape.

Step 7: Wire Bond Connections

The multiple bonding pads on the wire-bonded IC chip are respectively connected to inner pins of the multiple pins configured with the first metal material layer through metal wires, so as to realize electrical interconnection.

Step 8: First Plastic Seal

A package is formed by encapsulating the lead-bonded IC chip, the paste material, the metal wire, the chip carrier and the multiple leads with the first metal material layer with a plastic encapsulation material.

Step 9: Configure the IC chip with bumps

The IC chip with bumps is flip-chip-welded on the inner pins of multiple pins with the first metal material layer through flip-chip bonding equipment, and the bumps and multiple pins are realized by reflow soldering or thermocompression welding The inner pins are connected, and the IC chip with bumps is arranged on the package after the first plastic sealing through a heat-conducting adhesive material.

Step 10: Second plastic sealing

The product array is formed by encapsulating the IC chip with bumps, the package after the first plastic encapsulation, the pasting material and the multiple pins with the first metal material layer with the plastic encapsulation material.

Step 11: Print

Laser printing of product arrays in semiconductor package-in-package (PiP) system structures.

Step 12: Cutting Separate Products

Cut and separate products to form an independent single package system.

According to an embodiment of the present invention, the first metal material layer and the second metal material layer are configured by electroplating or electroless plating.

According to an embodiment of the present invention, the upper surface and the lower surface of the thin plate substrate are selectively partially etched respectively by using the first metal material layer and the second metal material layer as corrosion resist layers.

According to an embodiment of the present invention, the insulating filling material is disposed in the half-etched groove by methods such as screen printing or coating.

According to an embodiment of the present invention, the bumps on the IC chip are connected to the inner pins of the plurality of pins through reflow soldering or thermocompression soldering.

According to an embodiment of the present invention, a semiconductor package-in-package (PiP) system structure is formed through two plastic encapsulation processes.

According to the embodiment of the present invention, blade cutting, laser cutting or water jet cutting are used to cut and separate products, and only the plastic packaging material and insulating filling material are cut, and the lead frame is not cut.

Based on the above, according to the present utility model, the semiconductor package-in-package (PiP) system structure based on the traditional QFN package is a three-dimensional package, and the height can be controlled within 0.7 millimeters, with higher I/O density and integration, and the lead frame The stepped structure increases the bonding area with the plastic packaging material and insulating filling material, and has the effect of interlocking with the plastic packaging material and insulating filling material, which can effectively prevent the delamination of the lead frame, the plastic packaging material and the insulating filling material, as well as the lead or chip carrier The shedding of the package effectively prevents moisture from diffusing from the outside of the package structure to the inside. The small size of the outer pins can effectively prevent the bridging phenomenon during surface mounting. The first metal material on the upper surface and the lower surface of the lead frame are respectively arranged layer and the second metal material layer can effectively improve the quality of wire bonding, flip-chip soldering and surface mount quality. Since the individual packaging systems are only connected by plastic packaging materials and insulating filling materials, when using a dicing knife to cut and separate products, It will not cut the metal material of the lead frame, thereby improving the cutting efficiency, prolonging the life of the cutting knife, preventing the generation of metal burrs, and eliminating the need for pasting the adhesive film on the back of the lead frame before plastic sealing and after plastic sealing in the traditional QFN packaging process. Processes such as adhesive film and molding compound flash are removed to reduce packaging costs.

The above-mentioned features and advantages of the present utility model will be described in detail below with specific examples and accompanying drawings.

Description of drawings

FIG. 1A is a schematic diagram of the back side of a traditional QFN package structure;

剖面的剖面示意图；Figure 1B is along Figure 1A in the

a schematic sectional view of the section;

2A is a schematic diagram of the back side of the semiconductor package in package (PiP) system structure in which the pin cross section drawn according to an embodiment of the present invention is circular, and the pin arrangement on each side of the chip carrier is arranged in parallel;

2B is a schematic diagram of the back side of the semiconductor package in-package (PiP) system structure in which the cross-section of the pin drawn according to an embodiment of the present invention is rectangular, and the pin arrangement on each side of the chip carrier is arranged in parallel;

3A is a schematic diagram of the back side of a semiconductor package-in-package (PiP) system structure in which the cross-section of the pins drawn according to an embodiment of the present invention is circular, and the pin arrangement on each side of the chip carrier is a staggered arrangement;

3B is a schematic diagram of the back side of the semiconductor package in package (PiP) system structure in which the pin cross section drawn according to an embodiment of the present invention is rectangular, and the pin arrangement on each side of the chip carrier is a staggered arrangement;

Fig. 4 is drawn according to the embodiment of the present utility model, along the sectional schematic diagram of the I-I section in Fig. 2A-B and Fig. 3A-B;

5A to 5N are cross-sectional schematic diagrams of the manufacturing process of the semiconductor package-in-package (PiP) system structure drawn according to an embodiment of the present invention, and all the cross-sectional schematic diagrams are schematic cross-sectional diagrams along the section shown in FIG. 4 .

Symbols in the figure: 100. Traditional quadrilateral flat leadless package structure, 11. Lead frame, 111. Chip carrier, 112. Pin, 12. Plastic packaging material, 13. Bonding chip material, 14. IC chip, 15. Metal wire , 200, 200a, 200b, 200c, 200d. Semiconductor package-in-package (PiP) system structure, 201. Lead frame, 202. Chip carrier, 203. Pins, 20. Sheet substrate, 20a. Top surface of sheet substrate, The upper surface of the lead frame, 20b. the lower surface of the sheet substrate, the lower surface of the lead frame, 21a, 21b. the mask material layer, 22. the first metal material layer, 23. the second metal material layer, 22a. the first metal material layer surface, 23a. second metal material layer surface, 24. groove, 24a. stepped structure surface, 24b. stepped structure, 25. insulating filling material, 25a. insulating filling material surface, 26. pasting material, 27. leads Bonded IC chips, 28. metal wires, 29. plastic packaging materials, 30. IC chips with bumps, 31. bumps.

Detailed ways

Below in conjunction with accompanying drawing, the utility model is described in detail:

2A is a schematic diagram of the back side of a semiconductor package-in-package (PiP) system structure drawn according to an embodiment of the present invention, where the cross-section of the pins is circular and the pins on each side of the chip carrier are arranged in parallel. 2B is a schematic diagram of the back side of the semiconductor package-in-package (PiP) system structure drawn according to an embodiment of the present invention, where the cross-section of the pins is rectangular and the pins on each side of the chip carrier are arranged in parallel.

2A-B above, it can be seen that in this embodiment, the lead frame 201 of the semiconductor package (PiP) system structure 200a and 200b includes a chip carrier 202 and pins 203 arranged in multiple circles around the chip carrier 202, The pins 203 on each side of the chip carrier 202 are arranged in parallel, the second metal material layer 23 is disposed on the lower surface of the lead frame 201 , and the insulating filling material 25 is disposed in the lead frame 201 . The difference is that the pin cross section in the semiconductor package (PiP) system structure in FIG. 2A is circular, and the pin cross section in the semiconductor package (PiP) system structure in FIG. 2B is rectangular.

3A is a schematic diagram of the back side of a semiconductor package-in-package (PiP) system structure drawn according to an embodiment of the present invention, where the cross-section of the pins is circular and the pins on each side of the chip carrier are arranged in a staggered arrangement. 3B is a schematic diagram of the back side of a semiconductor package-in-package (PiP) system structure drawn according to an embodiment of the present invention with a rectangular pin cross section and a staggered arrangement of pins on each side of the chip carrier.

3A-B above, it can be seen that in this embodiment, the lead frame 201 of the semiconductor package (PiP) system structure 200c and 200d includes a chip carrier 202 and pins 203 arranged in multiple circles around the chip carrier 202, And the pins 203 on each side of the chip carrier 202 are arranged in a staggered arrangement, the second metal material layer 23 is disposed on the lower surface of the lead frame 201 , and the insulating filling material 25 is disposed in the lead frame 201 . The difference is that the pin cross section in the semiconductor package (PiP) system structure in FIG. 3A is circular, and the pin cross section in the semiconductor package (PiP) system structure in FIG. 3B is rectangular.

Fig. 4 is a schematic cross-sectional view drawn along the I-I section in Fig. 2A-B and Fig. 3A-B according to an embodiment of the present invention. 2A-B, 3A-B, referring to FIG. 4, in this embodiment, the semiconductor package package (PiP) system structure 200 includes a lead frame 201, a first metal material layer 22, a second metal material layer 23, Insulation filling material 25 , pasting material 26 , wire-bonded IC chip 27 , metal wire 28 , molding material 29 , IC chip 30 with bumps and bumps 31 .

In the embodiment of FIG. 4 , the lead frame 201 is used as a channel for conducting electricity, dissipating heat, and connecting external circuits, and has a stepped structure 24b along the thickness direction, with an upper surface 20a and a lower surface 20b opposite to the upper surface 20a, and a stepped structure Step surface 24a of 24b. The lead frame 201 includes a chip carrier 202 and pins 203 arranged in multiple turns around the chip carrier 202 . Both the chip carrier 202 and the leads 203 arranged in multiple turns around the chip carrier 202 have a stepped structure 24 b. The chip carrier 202 is disposed at the central part of the lead frame 201 , and the edge parts of the four sides of the chip carrier 202 have a stepped structure 24 b along the thickness direction. A plurality of pins 203 are arranged around the chip carrier 202, arranged in multiple circles around the chip carrier 202, and have a step structure 24b along the thickness direction, and its cross-sectional shape is circular or rectangular, wherein each pin 203 includes a The inner pins on the upper surface 20a and the outer pins are disposed on the lower surface 20b.

The first metal material layer 22 and the second metal material layer 23 are respectively arranged on the upper surface 20a position of the lead frame 201 and the lower surface 20b position of the lead frame 201, and the first metal material layer 22 and the inner pin of the pin 203 have the same Size, the second metal material layer 23 has the same size as the outer pin of the pin 203 . The first metal material layer 22 has a metal material layer surface 22a, and the second metal material layer 23 has a metal material layer surface 23a.

The insulating filling material 25 is disposed under the stepped structure 24 of the lead frame 201, and plays a role of supporting and protecting the lead frame 201. The insulating filling material 25 has an insulating filling material surface 25a, and the insulating filling material surface 25a and the metal material layer surface 23a on the same level.

A wire-bonded IC chip 27 is disposed at the center of the chip carrier 202 through a thermally conductive adhesive material 26 such as silver particle-containing epoxy resin or adhesive tape. The plastic encapsulation material 29 covers the wire-bonded IC chip 27 , the adhesive material 26 , the metal wire 28 , the chip carrier 202 and a plurality of pins 203 with the first metal material layer 22 to form a package. In this embodiment, the wire-bonded IC chip package has two rings of pins. The IC chip 30 with bumps is configured on the inner pins of the pins 203 through flip-chip mounting equipment, and is configured on the package after the first plastic packaging through the adhesive sheet material 26. The bumps 31 on the IC chip 30 Connect with the inner pins of the multi-turn pins 203 by reflow soldering or thermocompression welding, and the plastic encapsulation material 29 covers the IC chip 27 with bumps, the bumps 31, the package after the first plastic encapsulation, the adhesive material 26 and the A plurality of pins 203 of the first metal material layer 22 form a semiconductor package-in-package (PiP) system structure 200 product array. In this embodiment, the bumps 31 on the IC chip 30 with bumps are arranged in a single circle, and are respectively soldered to the outermost circle of the pins 203 arranged in three circles.

The manufacturing process of a semiconductor package-in-package (PiP) system structure will be described in detail below with reference to FIGS. 5A to 5N .

5A to 5N are cross-sectional schematic diagrams of the manufacturing process of the semiconductor package-in-package (PiP) system structure drawn according to an embodiment of the present invention, and all the cross-sectional schematic diagrams are schematic cross-sectional diagrams along the section shown in FIG. 4 .

Please refer to FIG. 5A , there is provided a sheet substrate 20 having an upper surface 20a and a lower surface 20b relative to the upper surface 20a, the material of the sheet substrate 20 can be copper, copper alloy, iron, iron alloy, nickel, nickel alloy and other applicable Metal material for making lead frame. The thickness of the sheet substrate 20 ranges from 0.1 mm to 0.25 mm, such as 0.127 mm, 0.152 mm, and 0.203 mm. The upper surface 20a and the lower surface 20b of the sheet substrate 20 are cleaned and pretreated, such as using plasma water to remove oil, dust, etc., to achieve the purpose of cleaning the upper surface 20a and the lower surface 20b of the sheet substrate 20.

Please refer to FIG. 5B , on the upper surface 20a and the lower surface 20b of the thin plate substrate 20, a mask material layer 21a and a mask material layer 21b with windows are respectively configured. and the sheet substrate 20 covered by the mask material layer 21b, the mask material layer 21a and the mask material layer 21b protect the sheet substrate 20 covered by it, and the mask material layer 21a and mask The sheet substrate 20 covered by the film material layer 21b is etched.

Please refer to FIG. 5C, the first metal material layer 22 is arranged in the window of the mask material layer 21a disposed on the upper surface 20a of the sheet substrate 20, the first metal material layer 22 has a first metal material layer surface 22a, and The second metal material layer 23 is disposed in the window of the mask material layer 21b disposed on the lower surface 20b of the sheet substrate 20, and the second metal material layer 23 has a second metal material layer surface 23a. The configuration methods of the first metal material layer 22 and the second metal material layer 23 are methods such as electroplating, electroless plating, evaporation, sputtering, and are allowed to be composed of different metal materials. In this embodiment, electroplating or electroless plating are preferred. As a configuration method of the first metal material layer 22 and the second metal material layer 23 . The materials of the first metal material layer 22 and the second metal material layer 23 are metal materials such as nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin (Sn) and alloys thereof. In the example, the first metal material layer 22 and the second metal material layer 23 are nickel-palladium-gold plating, for the first metal material layer 22, the outer gold plating and the middle palladium plating are to ensure that the metal wire 28 is in the lead frame. Wire bonding quality on 201 and flip-chip soldering quality on bump 31, the nickel plating inside is used as a diffusion barrier to prevent the formation of too thick eutectic compound caused by element diffusion-chemical reaction, too thick eutectic compound Affect the reliability of the bonding area. For the second metal material layer 23, the outer gold plating layer and the middle palladium plating layer are to ensure the wettability of the solder on the lead frame 201, and improve the surface mounting of the package on the PCB and other circuit boards. Quality, the nickel plating inside is used as a diffusion barrier to prevent the formation of excessively thick eutectic compounds caused by element diffusion-chemical reactions, and excessively thick eutectic compounds affect the reliability of surface mount soldering areas.

Please refer to FIG. 5D, remove the mask material layer 21b on the lower surface 20b of the sheet substrate 20, the removal method in this embodiment can be a chemical reaction method and a mechanical method, and the chemical reaction method is to select a soluble alkali An alkaline solution, such as potassium hydroxide (KOH), sodium hydroxide (NaOH), chemically reacts with the mask material layer 21b on the lower surface 20b of the sheet substrate 20 by spraying, etc., and dissolves it to achieve removal. To achieve the desired effect, an organic film removing solution can also be selected to remove the mask material layer 21b. After the mask material layer 21b is removed, only the second metal material layer 23 remains on the lower surface 20b of the sheet substrate 20 .

Please refer to FIG. 5E, the second metal material layer 23 on the lower surface 20b of the thin plate substrate 20 is used as an etching resist layer, and the lower surface 20b of the thin plate substrate 20 is selectively partially etched by spraying to form grooves. 24 and the stepped structure surface 24a, the etching depth range may be 40%-90% of the thickness of the sheet substrate 20 . In the present embodiment, the spraying method preferably adopts the upper spraying method, and the etching solution is preferably an alkaline etching solution, such as alkaline copper chloride etching solution, ammonium chloride and other alkaline etching solutions, so as to reduce the impact of the etching solution on the second The destructive effect of the metal material layer 23.

Please refer to FIG. 5F, the insulating filling material 25 is filled in the groove 24 formed by selective partial etching on the lower surface 20b of the thin plate substrate 20, and the insulating filling material 25 has a surface 25a, which is at a distance from the surface 23a of the second metal material layer. on the same level. In this embodiment, the insulating filling material 25 is an insulating material such as thermosetting plastic packaging material, plugging resin, ink, and solder resist green oil. The insulating filling material 25 has sufficient acid resistance and alkali resistance to ensure that subsequent processes will not damage the The insulating filling material 25 has been formed to cause damage. The filling method of the insulating filling material 25 is to fill it into the groove 24 by injection molding or screen printing, and remove the excessive insulating filling material 25 by mechanical grinding or chemical treatment after configuration. , to eliminate the flashing of the insulating filling material 25, so that the surface 25a of the insulating filling material 25 is on the same level as the second metal material layer 23a, and for the insulating filling materials 25 such as photosensitive solder resist green oil, the flashing is removed by a developing method .

Please refer to FIG. 5G , the mask material layer 21a on the upper surface 20a of the sheet substrate 20 is removed. The removal method in this embodiment can be a chemical reaction method and a mechanical method. The chemical reaction method is to select a soluble alkali An alkaline solution, such as potassium hydroxide (KOH), sodium hydroxide (NaOH), chemically reacts with the mask material layer 21a on the upper surface 20a of the sheet substrate 20 by spraying, etc., and dissolves it so as to achieve removal. As a result, the mask material layer 21a can also be removed by selecting an organic film removing solution. After the mask material layer 21a is removed, only the first metal material layer 22 remains on the upper surface 20a of the sheet substrate 20 .

Please refer to FIG. 5H, the first metal material layer 22 on the upper surface 20a of the thin plate substrate 20 is used as an etching resist layer, and the upper surface 20a of the thin plate substrate 20 is selectively partially etched by spraying, and the etching reaches a step. The structure surface 24a exposes the insulating filling material 25 . A lead frame 201 is formed, the lead frame 201 includes a chip carrier 202 and pins 203 arranged in multiple circles around the chip carrier 202, and an insulating filling material 25 is disposed in the lead frame 201, that is, the chip carrier 202 and the pins 203 arranged in multiple circles around the chip carrier 202 The pins 203 are fixed together by an insulating filling material 25 . The separated pins 203 formed after selective partial etching have inner pins and outer pins, and the inner pins are connected to bonding pads of wire-bonded IC chips 27 and IC chips with bumps 30 bumps 31, the outer pins are used as channels for connecting external circuits. A stepped structure 24b is formed having a stepped structured surface 24a. In this embodiment, the spraying method of the etching solution is preferably the upper spraying method, and the etching solution is preferably an alkaline etching solution, such as alkaline copper chloride etching solution, ammonium chloride and other alkaline etching solutions, to reduce the amount of etching solution Damage to the first metal material layer 22 .

Please refer to Fig. 5I, the IC chip 27 of wire bonding is arranged on the first metal material layer 22 position on the upper surface 20a of the lead frame through the adhesive material 26, and is fixed on the central part of the chip carrier 202. In this embodiment, the adhesive The material 26 may be a thermally conductive material such as die-bonding tape, epoxy resin containing silver particles, or the like.

Please refer to FIG. 5J , a plurality of bonding pads on a lead-bonded IC chip 27 are connected to a plurality of internal pins configured with a first metal material layer 22 through metal wires 28, so as to realize electrical interconnection. In this embodiment Among them, the metal wires 28 are gold wires, aluminum wires, copper wires, and palladium-plated copper wires.

Please refer to FIG. 5K , using injection molding method, the IC chip 27, the paste material 26, the metal wire 28, the partial area of the lead frame 201 and the first metal material layer 22 are covered by the plastic encapsulation material 29 to form a QFN package. Inner package. In this embodiment, the molding material 29 can be a material such as a thermosetting polymer, and the insulating filling material 25 filled has physical properties similar to the molding material 29, such as a coefficient of thermal expansion, so as to reduce product failure caused by thermal mismatch and improve For product reliability, the insulating filling material 25 and the molding material 29 can be the same material. Baking and curing after molding, the molding material 29 and the insulating filling material 25 have a mutual locking function with the lead frame 201 having a stepped structure 24b, which can effectively prevent the delamination of the lead frame 201 and the molding material 29 and the insulating filling material 25 and The lead 203 or the chip carrier 202 falls off, and effectively prevents the moisture from diffusing into the package along the bonding interface between the lead frame 201, the molding material 29 and the insulating filling material 25, thereby improving the reliability of the package.

Please refer to FIG. 5L, the IC chip 30 with bumps is configured on the inner pin of the pin 203 through the flip-chip mounting device, and is configured on the package after the first plastic sealing through the adhesive sheet material 26, the IC chip 30 The bumps 31 on the top are connected to the inner pins of the multi-turn pins 203 by reflow soldering or thermocompression soldering to realize electrical interconnection. In this embodiment, the bumps on the IC chip are lead-free solder bumps, lead-containing solder bumps or metal bumps.

Please refer to Fig. 5M, adopt injection molding method, cover the IC chip 27 with bump, bump 31, package after the first plastic sealing, paste material 26 and have the first metal material layer 22 by environment-friendly plastic sealing material 29 A plurality of pins 203 form a semiconductor package (PiP) system structure 200 product array. . In this embodiment, the bumps 31 on the IC chip 30 with bumps are arranged in a single circle, and are respectively welded and arranged on the outermost circle of the pins 203 arranged in three circles, and the plastic sealing material 29 can be a material such as a thermosetting polymer. , the filled insulating filling material 25 has similar physical properties as the molding material 29, such as thermal expansion coefficient, so as to reduce product failure caused by thermal mismatch and improve product reliability. After the semiconductor package-in-package (PiP) system structure 200 product array is formed, laser printing is performed on the product array.

Referring to FIG. 5N , the product array of the semiconductor-in-package (PiP) system structure 200 is cut, and the molding material 29 and insulating filling material 25 are completely cut and separated to form a single semiconductor-in-package (PiP) system structure 200 . In this embodiment, the method of separating a single product is blade cutting, laser cutting or water jet cutting, and only the molding material 29 and insulating filling material 25 are cut, and the metal material of the lead frame is not cut. Only the cutting separation is drawn in FIG. 5N The latter 2 semiconductor package-in-package (PiP) systems structure an array of 200 products.

The description of the embodiments of the utility model is for the purpose of effectively illustrating and describing the utility model, and is not intended to limit the utility model. Any person skilled in the art should understand that: without departing from the utility model concept and Variations can be made to the above-described examples under various conditions. It is intended, therefore, that the invention not be limited to the particular embodiments disclosed, but cover modifications within the spirit and scope of the invention as defined by the claims.

Claims (4)

1. A packaging system structure in a semiconductor package, characterized in that it comprises: A lead frame having a stepped structure along the thickness direction, having an upper surface, a lower surface, and a stepped surface, wherein the lead frame includes a chip carrier, a plurality of pins: The chip carrier is arranged in the central part of the lead frame, and the edge parts of the four sides of the chip carrier have a stepped structure along the thickness direction, and A plurality of pins are arranged around the chip carrier, arranged in multiple circles around the chip carrier, and have a stepped structure along the thickness direction, wherein each pin includes an inner pin configured on the upper surface and an outer pin configured on the lower surface pin; The first metal material layer is arranged on the upper surface of the lead frame; The second metal material layer is arranged on the lower surface of the lead frame; The wire-bonded IC chip is arranged on the first metal material layer on the upper surface of the lead frame through an adhesive material, and is arranged on the central part of the chip carrier; An IC chip with bumps is configured on the inner pins of the plurality of pins with the first metal material layer by flip-chip welding; The wire-bonded IC chip is arranged between the IC chip with bumps and the lead frame; the insulating filling material is arranged under the stepped structure of the lead frame; Metal wires, the plurality of bonding pads on the wire-bonded IC chip are respectively connected to the inner pins of the plurality of pins configured with the first metal material layer through metal wires; The plastic encapsulation material covers the IC chips bonded with wires, the IC chips with bumps, the adhesive material, the lead frame and the first metal material layer to form a package. 2. The packaging system structure in a semiconductor package according to claim 1, wherein the above-mentioned lead frame has a plurality of pins arranged around the chip carrier, the cross-sectional shape of the pins is circular or rectangular, and the number of circles arranged is It is single-turn, double-turn, three-turn or more than three turns, and the multi-turn pins are arranged in parallel or staggered. 3 . The packaging system structure in a semiconductor package according to claim 1 , wherein the bumps on the IC chip with bumps are arranged in a single circle, double circle or more than three circles. 4 . 4 . The packaging system structure in a semiconductor package according to claim 1 , wherein the bumps on the IC chip with bumps are lead-free solder bumps, lead-containing solder bumps or metal bumps.

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