CN103021451A - Device and method for threshold-voltage adjustment-based multistage temperature control self-refreshing storage - Google Patents

Abstract

The present invention relates to the field of memory technology, in particular to a multi-level temperature control self-refresh method based on threshold voltage adjustment. The storage device includes an oscillator, a frequency divider, a temperature sensor, a first selector, the temperature sensor and The first selector is connected, the oscillator is connected to the frequency divider, the frequency divider is connected to the first selector, the first selector is connected to the DRAM array, and the storage device also includes n substrate voltage stabilization modules and a second selection The n substrate voltage stabilization modules generate substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and the second selector selects from the substrate voltages VBB1, VBB2, VBBn under the control of the temperature voltage signal Vtemp generated by the temperature sensor. ...Select one of VBBn to output to the transistor substrate voltage of the DRAM array. The present invention overcomes the problems existing in the prior art, such as the large temperature range corresponding to the frequency of each stage, the large variation range of the threshold voltage, and the possible low efficiency or unreliability problems.

Description

A multi-level temperature-controlled self-refresh memory device and method based on threshold voltage adjustment

technical field

The invention relates to the technical field of memory, in particular to a multi-level temperature-controlled self-refresh method based on threshold voltage adjustment.

Background technique

DRAM can cause data corruption due to leakage current, so the data should be read out before the cell data is lost and then charged to the initial charge level. This recharging process is called refreshing. In addition, self-refresh means that the DRAM itself refreshes at a fixed period to maintain data in the memory cells in the standby state. On the other hand, the leakage current doubles for every 10°C rise in temperature. In other words, when the temperature rises by 10 degrees, the retention time of the memory cell data is reduced by 1/2, and when the temperature rises by 50 degrees, the retention time is reduced to 1/32. As described above, leakage current is closely related to temperature, therefore, temperature is an important factor affecting the refresh cycle. That is, the self-refresh period should be shorter at relatively higher temperatures.

In the prior art, the refresh frequency is controlled in multiple levels according to the temperature. Referring to FIG. The temperature sensor 103 has the function of sensing the temperature and processing it in stages, and provides voltage signals corresponding to the temperatures in different stages, which are output to the input terminal of the selector 104 . Frequency divider 102 generates various refresh frequencies. According to the voltage signals corresponding to different temperatures, the selector 104 selects a refresh frequency and outputs refrq. Referring to FIG. 2 , FIG. 2 is a graph of threshold voltage, multi-level refresh frequency, and temperature variation in the prior art. In the prior art, the threshold voltage Vth decreases as the temperature increases, and the refresh period corresponds to different periods in different temperature stages. At this time, the refresh period of each stage should meet the refresh requirements in the worst case in the temperature stage, and the reciprocal of the refresh period is the refresh frequency.

The prior art CN1734667A discloses a refresh cycle generating circuit. This refresh cycle generating circuit generates a refresh cycle when refreshing a DRAM cell, and includes: an oscillation circuit section that oscillates at a frequency that is temperature-dependent on the ambient temperature; and a frequency divider that divides the oscillation output of the oscillation circuit section. A frequency circuit; a temperature detector for detecting the ambient temperature; and according to the output of the temperature detector, switchably select and output frequency division outputs of a plurality of frequencies from the frequency division circuit, and output as the frequency of the refresh period A selection circuit of a reference signal, wherein the temperature dependence of the oscillating circuit unit has a positive temperature coefficient within a predetermined temperature range and does not have a positive temperature coefficient outside the predetermined temperature range, the selection circuit Switching of the frequency division output is performed outside the prescribed temperature range.

The disadvantage of the existing technology is that, usually, if it is not controlled, the refresh rate needs to be doubled every 12 degrees. Then the refresh frequency must be set in sections. The temperature range corresponding to the frequency of each stage is large, and the threshold voltage changes in a large range, which may cause low efficiency or unreliability problems.

Contents of the invention

In order to achieve the above object, the present invention proposes a multi-level temperature-controlled self-refresh storage device based on threshold voltage adjustment, including an oscillator, a frequency divider, a temperature sensor, a first selector, and the temperature sensor and the first selector connected, the oscillator is connected to the frequency divider, the frequency divider is connected to the first selector, the first selector is connected to the DRAM array, the storage device also includes n substrate voltage stabilization modules and the second selector, the n substrate voltage stabilization modules generate substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and the second selector selects from the substrate voltages VBB1, VBB2, ... VBBn under the control of the temperature voltage signal Vtemp generated by the temperature sensor Select one to output to the transistor substrate voltage of the DRAM array, where n is a natural number.

Preferably, the oscillator generates a refresh signal frq, which is then output to the frequency divider.

Preferably, the frequency divider divides the frequency of the refresh signal frq generated by the oscillator to generate a frequency-divided refresh frequency frqs.

Preferably, under the control of Vtemp, the first selector selects from a plurality of refresh frequencies frqs to give a final refresh frequency Refrq, and outputs it to the DRAM array.

Preferably, the substrate voltage stabilizing module includes three fixed value resistors, a transistor T1, a comparator and a charge pump.

Preferably, the triode is the same transistor as the transistor in the DRAM array, and is obtained from a redundant unit.

Preferably, the substrate voltage VBBn is obtained by adjusting three fixed value resistors.

Preferably, the second selector is a tri-state transmission gate.

In order to achieve the above object, the present invention also proposes a method, comprising the following steps: n substrate voltage stabilization modules generate substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and the temperature generated by the second selector at the temperature sensor Under the control of the voltage signal Vtemp, one of the substrate voltages VBB1, VBB2, . . . VBBn is selected and output to the transistor substrate voltage of the DRAM array, wherein n is a natural number.

The present invention overcomes the problems existing in the prior art, such as the large temperature range corresponding to the frequency of each stage, the large variation range of the threshold voltage, and the possible low efficiency or unreliability problems.

Description of drawings

Accompanying drawing 1 is the storage device of the prior art that controls refresh frequency according to temperature multilevel;

Accompanying drawing 2 is the graph of prior art threshold voltage and multi-level refresh frequency, temperature change;

Figure 3 is a multi-level temperature-controlled self-refresh storage device based on threshold voltage adjustment according to an embodiment of the present invention;

Accompanying drawing 4 is the circuit diagram of the substrate voltage stabilizing module 201 according to the embodiment of the present invention;

Accompanying drawing 5 is the circuit diagram of the substrate voltage stabilizing module 202 according to the embodiment of the present invention;

Figure 6 is a graph of threshold voltage, multi-level refresh frequency, and temperature change according to an embodiment of the present invention;

Accompanying drawing 7 is the circuit diagram of selector 300 according to the embodiment of the present invention;

Detailed ways

FIG. 3 is a multi-level temperature-controlled self-refresh storage device based on threshold voltage adjustment according to an embodiment of the present invention, and the same components are designated with the same reference numerals as those in FIG. 1 . The self-refresh storage device with multi-level temperature control based on threshold voltage adjustment includes an oscillator 101 , a frequency divider 102 and a temperature sensor 103 . According to an embodiment of the present invention, the multi-level temperature-controlled self-refresh memory device based on threshold voltage adjustment sets two selectors The selector 104 and the selectors 300, 400 are a DRAM array. The storage device is provided with a plurality of substrate voltage stabilizing modules 201, 202, ... 20n, where n is a natural number. Each of the substrate voltage stabilization modules 201, 202, ... 20n is connected to the selector 300, and the substrate voltage stabilization modules 201, 202, ... 20n generate substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and output to Selector 300. The temperature sensor 101 is used to generate a voltage Vtemp that depends on temperature fluctuations, and the temperature sensor 103 is connected to the selector 104 and the selector 300 at the same time. The selector 300 selects one of VBB1, VBB2 and VBBn to output to the transistor substrate voltage VBB of the DRAM array under the control of the temperature voltage signal Vtemp. The oscillator 101 generates a refresh signal frq, which is then output to a frequency divider for frequency division to generate a frequency-divided refresh frequency frqs. The refresh frequency Reffq, also under the control of Vtemp, is selected from a plurality of frequencies frqs by the selector 1 module 104 . That is, the temperature sensor 103 is connected to the selector 104 and the selector 300 respectively, and the temperature fluctuation-dependent voltage Vtemp output by the temperature sensor is output to the selector 104 and the selector 300, and the selector 300 is controlled by the temperature voltage signal Vtemp from VBB1 , VBB2 until VBBn select one to output to the transistor substrate voltage VBB of the DRAM array; at the same time, under the control of Vtemp, the selector 1 module 104 selects and gives from a plurality of frequencies ffqs.

Fig. 4 is a circuit diagram (201, 202, ..., 20n) of a substrate voltage stabilizing module according to an embodiment of the present invention. As an example, FIG. 4 shows a circuit diagram of the substrate voltage stabilization module 201 . The substrate voltage stabilization module 201 includes fixed value resistors R11, R12, R13, a transistor T1, a comparator and a charge pump. T1 is the same transistor as the transistor in the DRAM array, which can be taken from the redundant cell. One end of the resistor R12 is connected to the positive input end of the comparator, the other end of the R12 is connected to the power supply voltage VDD or a certain reference voltage Vref, and the other end of the R13 is grounded. One end of R11 is connected to the power supply voltage VDD or a certain reference voltage Vref, while the other end is connected to the drain and gate of the triode T1, and connected to the negative input end of the comparator, the output end of the comparator is connected to the charge pump, and the charge pump The output is VBB, and it is fed back to the triode at the same time. VBB1 is obtained by adjusting R11, R12, and R13; in 202, VBB2 is obtained by adjusting R21, R22, and R23. By analogy, in 20n, VBBn is obtained by adjusting the corresponding Rn1, Rn2, and Rn3. The transistor T1 here is the same transistor as the transistor in the DRAM array, and can be taken from the redundant unit. Similarly, FIG. 5 is a circuit diagram of the substrate voltage stabilizing module 202 according to an embodiment of the present invention. Since it has the same structure, it will not be introduced here one by one.

FIG. 6 is a graph of threshold voltage, multi-level refresh frequency, and temperature variation according to an embodiment of the present invention. After adopting the present invention, the threshold voltage remains unchanged in a certain temperature range, so the refreshing frequency can adopt a lower frequency in the range, thereby reducing the refreshing power consumption.

FIG. 7 is a circuit diagram of a selector 300 according to an embodiment of the present invention. 301, 302, ... 30n may be tri-state transmission gate circuits. The substrate voltages VBB1, VBB2, ... VBBn generated by the substrate voltage stabilizing modules 201, 202, ... 20n during the DRAM retention period are sequentially output to the tri-state transmission gate circuits 301, 302, ... 30n. Under the control of the temperature voltage signal Vtemp, select a voltage from VBB1, VBB2 until VBBn to output VBB.

According to an embodiment of the present invention, a method for refreshing a multi-level temperature-controlled self-refresh storage device based on threshold voltage adjustment is also proposed, the storage device includes an oscillator, a frequency divider, a temperature sensor, a first selector, and The temperature sensor is connected to the first selector, the oscillator is connected to the frequency divider, the frequency divider is connected to the first selector, and the first selector is connected to the DRAM array. The method includes n substrate voltage stabilizing modules generating substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and the second selector selects from substrate voltages VBB1, VBB2, VBBn under the control of temperature voltage signal Vtemp generated by a temperature sensor. ...Select one of VBBn to output to the transistor substrate voltage of the DRAM array, wherein, n is a natural number.

While preferred embodiments of the present invention have been shown and described, it would be obvious to those skilled in the art that many changes and modifications can be made without departing from the invention in its broader aspects.

Claims (9)

1. A multi-level temperature-controlled self-refresh storage device based on threshold voltage regulation, comprising an oscillator, a frequency divider, a temperature sensor, and a first selector, the temperature sensor is connected to the first selector, and the oscillator is connected to The frequency divider is connected with the first selector, and the first selector is connected with the DRAM array, and is characterized in that: The storage device also includes n substrate voltage stabilizing modules and a second selector, the n substrate voltage stabilizing modules generate substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and the second selector controls the temperature sensor Under the control of the generated temperature voltage signal Vtemp, select one of the substrate voltages VBB1, VBB2, ... VBBn to output to the transistor substrate voltage of the DRAM array, Among them, n is a natural number. 2. The multi-level temperature-controlled self-refresh memory device based on threshold voltage adjustment according to claim 1, wherein the oscillator generates the refresh signal frq, which is then output to the frequency divider. 3. The multi-level temperature-controlled self-refresh storage device based on threshold voltage adjustment according to claim 2, wherein the frequency divider divides the frequency of the refresh signal frq generated by the oscillator to generate a frequency-divided refresh frequency frqs . 4. The multi-level temperature-controlled self-refresh storage device based on threshold voltage adjustment according to claim 3, characterized in that, under the control of Vtemp, the first selector selects from a plurality of refresh frequencies frqs to give the final refresh frequency Refrq , output to the DRAM array. 5. The multi-level temperature-controlled self-refresh memory device based on threshold voltage adjustment according to claim 1, wherein the substrate voltage stabilization module includes three fixed value resistors, a transistor T1, a comparator and a charge pump. 6. The multi-level temperature-controlled self-refresh memory device based on threshold voltage adjustment according to claim 5, wherein the triode is the same transistor as that in the DRAM array, and is taken from a redundant unit. 7. The self-refresh storage device with multi-level temperature control based on threshold voltage adjustment according to claim 6, wherein the substrate voltage VBBn is obtained by adjusting three fixed-value resistors. 8. The multi-level temperature-controlled self-refresh memory device based on threshold voltage adjustment according to claim 1, wherein the second selector is a tri-state transmission gate. 9. A method for refreshing a multi-level temperature-controlled self-refresh storage device based on threshold voltage regulation, the storage device comprising an oscillator, a frequency divider, a temperature sensor, a first selector, the temperature sensor and a first selector The oscillator is connected to the frequency divider, the frequency divider is connected to the first selector, the first selector is connected to the DRAM array, and it is characterized in that: n substrate voltage stabilization modules generate substrate voltages VBB1, VBB2, ... VBBn during DRAM retention, and the second selector selects from the substrate voltages VBB1, VBB2, ... VBBn under the control of the temperature voltage signal Vtemp generated by the temperature sensor Select one to output to the transistor substrate voltage of the DRAM array, where n is a natural number.

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