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CN103000541B - 芯片封装结构的制造方法 - Google Patents

芯片封装结构的制造方法 Download PDF

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Publication number
CN103000541B
CN103000541B CN201110359998.0A CN201110359998A CN103000541B CN 103000541 B CN103000541 B CN 103000541B CN 201110359998 A CN201110359998 A CN 201110359998A CN 103000541 B CN103000541 B CN 103000541B
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chip
layer
conductive circuit
circuit layer
manufacturing
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CN103000541A (zh
Inventor
林殿方
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King Yuan Electronics Co Ltd
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Dawning Leading Technology Inc
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Abstract

本发明提出一种芯片封装结构的制造方法。该制造方法包含：提供一保护层；形成一导电线路层于保护层上；形成一粘着层于导电线路层上；放置一芯片于粘着层上；以及电性连接芯片与导电线路层。藉此，该制造方法所制造出的芯片封装结构可具有较小的厚度。

Description

芯片封装结构的制造方法
技术领域
本发明有关一种封装结构的制造方法，特别是关于一种芯片封装结构的制造方法。
背景技术
芯片封装结构有许多种，而其中一种大致包括：一芯片及一基板，该芯片放置于基板上，且芯片的连接垫(pad)与基板的电路相互电性连接，而芯片及基板可选择地再被一封装胶体包覆住。中国台湾专利第I343100号所揭露的，即为上述的芯片封装结构。
上述的芯片封装结构已发展多年，故其技术较成熟，良率也较高。然而，因为该芯片封装结构的基板是由多层材料堆叠而成，基板的厚度会较大，造成芯片封装结构的整体厚度难以缩减到预期值。在电子产品薄型化的趋势下，此种厚度较大的芯片封装结构的应用将会受限。
有鉴于此，提供一种可改善至少一种上述缺失的芯片封装结构的制造方法，这是此业界亟待解决的严肃问题。
发明内容
本发明的目的在于提供一种芯片封装结构及其制造方法，所制造出的芯片封装结构的基板可具有明显更薄的厚度，以使得芯片封装结构的厚度也减少。
为达上述目的，本发明的芯片封装结构包含：一导电线路层；一粘着层，设置于该导电线路层上；以及一芯片，粘于该粘着层上，并电性连接该导电线路层。
为达上述目的，本发明的芯片封装结构的制造方法包含：提供一保护层；形成一导电线路层于该保护层上；形成一粘着层于该导电线路层上；放置一芯片于该粘着层上；以及电性连接该芯片与该导电线路层。
本发明的有益效果是：因芯片与导电金属层之间可仅设有粘着层，故芯片封装结构的整体厚度可较少，以利应用于厚度较薄的电子产品中；芯片封装结构可包含转接元件，以减少芯片的打线距离及打线高度，且转接元件可包含天线、电容器、电感器等元件，以扩充芯片封装结构的功能；芯片封装结构可不包含保护层，以进一步减少芯片封装结构的厚度；以及芯片封装结构的制造方法可轻易地实施。
附图说明
图1为本发明第一较佳实施例的芯片封装结构的一侧视图；
图2为本发明第二较佳实施例的芯片封装结构的一侧视图；
图3为本发明第三较佳实施例的芯片封装结构的一侧视图；
图4为本发明第三较佳实施例的芯片封装结构的另一侧视图；
图5为本发明第四较佳实施例的芯片封装结构的一侧视图；
图6为本发明第五较佳实施例的芯片封装结构的一侧视图；
图7为本发明第六较佳实施例的芯片封装结构的一侧视图；
图8为本发明第七较佳实施例的芯片封装结构的一侧视图；
图9为本发明第七较佳实施例的芯片封装结构的另一侧视图；
图10为本发明第八较佳实施例的芯片封装结构的一侧视图；
图11为本发明的芯片封装结构的制造方法的第一较佳实施例的一流程图；
图12A为图11的步骤S101的示意图；
图12B为图11的步骤S105的示意图；
图12C为图11的步骤S107的示意图；及
图12D为图11的步骤S111的示意图。
主要元件符号说明
1-8芯片封装结构
11保护层
111贯穿孔
12导电线路层
121上表面
122下表面
12A金属层
13粘着层
131贯穿孔
13A粘着层
14芯片
141连接垫
15转接元件
16金属引线
16A金属引线
17芯片
18绝缘层
181贯穿孔
19金属凸块
20封装胶体
21A导电材料
21B金属凸块
具体实施方式
为让本发明的上述目的、特征和优点能更明显易懂，以下结合附图对本发明的具体实施方式作详细说明。首先需要说明的是，本发明并不限于下述具体实施方式，本领域的技术人员应该从下述实施方式所体现的精神来理解本发明，各技术术语可以基于本发明的精神实质来作最宽泛的理解。图中相同或相似的构件采用相同的附图标记表示。
请参阅图1所示，为本发明第一较佳实施例的芯片封装结构的一侧视图。第一较佳实施例的芯片封装结构1包括：一保护层11、一导电线路层12、一粘着层13及一芯片14，各元件将依序说明如下。
保护层(protectionlayer)11为芯片封装结构1的基层，可用以承载芯片封装结构1的其它元件。保护层11由不会导通电能的材料所制成，例如树脂、陶瓷等。
导电线路层(conductivetracelayer)12设置于保护层11上，换言之，保护层11设置于导电线路层12下。导电线路层12非布满整个保护层11的上表面121，而是构成一特定的线路图案。导电线路层12的制造材料可由包含铜等导电率良好的金属材料所构成，且导电线路层12可通过印刷、贴附或半导体工艺(沉积、蚀刻等)等方式设置于保护层11上。
粘着层(adhesionlayer)13设置于导电线路层12上，而本实施例中，粘着层13为直接地设置于导电线路层12上，因此粘着层13可接触、覆盖导电线路层12，并且还可接触未被导电线路层12覆盖的部分的保护层11。此外，粘着层13可为粘性胶带、可固化的粘胶等具有粘性且不会导通电能的物体，以使被粘着层13覆盖的导电线路层12不会有短路的问题。
粘着层13中另形成有至少一贯穿孔131(本实施例为二个贯穿孔)，以使得导电线路层12的一上表面121可部分地暴露于贯穿孔131中；如此，其它物体(例如后述的金属引线或金属凸块)可通过贯穿孔131，而接触到导电线路层12的上表面121。
芯片14贴附于粘着层13上，使得在制作工序中芯片14不易相对于粘着层13或导电线路层12造成移动。芯片14并进一步电性连接导电线路层12，使得芯片14可与导电线路层12相互电性传递(信号或数据)。
本实施例中，芯片14与导电线路层12的电性连接是通过打线(wirebonding)方式来达成。详言之，芯片封装结构1另包含多个金属引线16，金属引线16的一端会焊接于芯片14的其中一个连接垫141上，而金属引线16的另一端则会焊接于暴露于贯穿孔131中的导电线路层12的上表面121上，藉此导通连接垫141与导电线路层12。
本实施例的芯片封装结构1与现有的相比较，可具有较少的层数(例如导电线路层12与芯片14之间只有粘着层13)，故芯片封装结构1的整体厚度也可较小，以适于应用于薄型化的电子产品。
以上为第一较佳实施例的芯片封装结构1的说明，接着说明本发明的芯片封装结构的其它较佳实施例。为了简洁说明的目的，其他较佳实施例与第一较佳实施例相似之处，以及其他较佳实施例之间的相似之处，皆将不再予以叙述。
请参阅图2所示，其为本发明第二较佳实施例的芯片封装结构的一侧视图。第二较佳实施例的芯片封装结构2与前述芯片封装结构1的差异在于：芯片封装结构2的粘着层13A中并不需形成贯穿孔。
详言之，粘着层13A设置于部分的导电线路层12上，可仅分布在芯片14的下方(无须满板覆盖于导电线路层12上)。如此，没有被粘着层13A所覆盖的导电线路层12便可直接进行后续工序。且由于不需额外再增加一形成贯穿孔的工序，故其工艺时间及成本也可降低。
请参阅图3所示，其为本发明第三较佳实施例的芯片封装结构的一侧视图。第三较佳实施例的芯片封装结构3与前述这些芯片封装结构1、2的差异在于：芯片封装结构3还包括一转接元件(transferelement)15。
转接元件15设置于芯片14上，且可通过打线方式来电性连接芯片14或导电线路层12。转接元件15与芯片14之间也可设置另一粘着层(图未示)，以使工序中转接元件15不会相对于芯片14造成移动。转接元件15可为电路板(软性电路板、陶瓷电路板等)、芯片等可传递电能的元件，且转接元件15之中或其上可形成或包含天线、电容器、电感器等电子元件装置，以增加转接元件15的功能。
请参阅图4所示，其为本发明第三较佳实施例的芯片封装结构的另一侧视图。转接元件15可供另一芯片17设置于其上。由于转接元件15可传递电能至芯片14或导电线路层12，芯片17的电能可通过转接元件15传递至芯片14或导电线路层12。换言之，芯片17与导电线路层12之间可不需金属引线来电性连接，因此图4所示的金属引线16A实际上是可省略的。当金属引线16A省略后，芯片封装结构1的整体高度可大幅降低。可知，转接元件15对于芯片封装结构1而言，有降低整体封装高度的功效。
请参阅图5所示，其为本发明第四较佳实施例的芯片封装结构的一侧视图。第四较佳实施例的芯片封装结构4与前述这些芯片封装结构1至3的差异在于：芯片封装结构4还包括一绝缘层(isolationlayer)18。
详言之，绝缘层18设置于导电线路层12与粘着层13之间，使得粘着层13为间接地设置于导电线路层12上。绝缘层18可覆盖整个导电线路层12，并同样形成有贯穿孔181，使得导电线路层12的部分上表面121可暴露出。
请参阅图6所示，其为本发明第五较佳实施例的芯片封装结构的一侧视图。第五较佳实施例的芯片封装结构5与前述芯片封装结构1至4的差异在于：芯片14与导电线路层12的电性连接是通过倒装芯片(flipchip)方式来达成。
详言之，芯片封装结构5可包含多个金属凸块(metalbump)19，设置于粘着层13的贯穿孔131中及导电线路层12的上表面121上，而芯片14的连接垫141则朝向、面对导电线路层12的上表面121。如此，金属凸块19可同时接触芯片14的连接垫141与导电线路层12的上表面121，以导通连接垫141与导电线路层12。
请参阅图7所示，其为本发明第六较佳实施例的芯片封装结构的一侧视图。第六较佳实施例的芯片封装结构6与前述芯片封装结构1至5的差异在于：还包括一封装胶体(encapsulation)20。该封装胶体20至少可包覆芯片14、粘着层13及导电线路层12；若芯片封装结构5包含转接元件15、芯片17、金属引线16或金属凸块19时，封装胶体20也可一并将这些元件包覆住。被封装胶体20包覆住的物体较不会受到外界环境的影响。
请参阅图8及图9所示，分别为本发明第七较佳实施例的芯片封装结构的一侧视图。第七较佳实施例的芯片封装结构7与前述芯片封装结构1至6的差异在于：芯片封装结构7的保护层11中形成有至少一贯穿孔111，使得导电线路层12的一下表面122部分地暴露于贯穿孔111中。
此外，芯片封装结构7还包含至少一导电材料21A(如图8所示)或金属凸块21B(如图9所示)，设置于保护层11的贯穿孔111中，并接触导电线路层12的下表面122。如此，导电材料21A(或金属凸块21B)可作为芯片封装结构7与外部电子元件或电路板(图未示)连接用的媒介。需说明的是，导电材料21A可略高于保护层11。
请参阅图10所示，其为本发明第八较佳实施例的芯片封装结构的一侧视图。第八较佳实施例的芯片封装结构8与前述芯片封装结构1至6的差异在于：芯片封装结构8无包含保护层11，使得导电线路层12的下表面122可以皆露出。如此，导电线路层12的下表面122即可直接作为芯片封装结构8与外部电子元件或电路板(图未示)连接用的媒介。此外，因为没有了保护层11，芯片封装结构8的厚度可进一步地缩减。
以上为本发明的芯片封装结构的各实施例的说明。接着说明本发明的芯片封装结构的制造方法，该制造方法至少可制作出上述这些芯片封装结构1至8。然而需说明的是，本发明的芯片封装结构并不局限由本发明的芯片封装结构的制造方法来制作出。
请参阅图11所示，为本发明的芯片封装结构的制造方法的第一较佳实施例的一流程图。并请参阅图12A至12D图所示，分别为图11的其中一个步骤的示意图。本实施例的芯片封装结构的制造方法可从步骤S101开始，也就是先提供一个保护层11(如图12A所示)。
接着形成一金属层12A于保护层11上(步骤S103)，然后通过蚀刻等方式移除部分的金属层12A(步骤S105，如图12B所示)。没有被移除的金属层12A可构成一特定的线路图案，也就是导电线路层12。除了步骤S103及S105外，仍有其它方式可形成导电线路层12于保护层11上，例如通过印刷方式等。
导电线路层12形成后，接着可形成一粘着层13于导电线路层12上(步骤S107，如图12C所示)。粘着层13可直接地形成在导电线路层12，以接触导电线路层12及部分未被导电线路层12覆盖的保护层11。
或者，在导电线路层12形成后，也可先形成一绝缘层18于导电线路层12上(步骤S109，如图12D所示)，再形成一粘着层13于绝缘层18上(步骤S111，如图12D所示)，使得粘着层13为间接地形成于导电线路层12上。
粘着层13直接或间接形成于导电线路层12上后，可通过蚀刻等方式，移除部分的粘着层13，以在粘着层13中形成至少一贯穿孔131(步骤S113，如图1所示)。如此，导电线路层12的上表面121可部分地暴露于贯穿孔131中，以便于后续导电线路层12与芯片14的电性连接。若粘着层13仅形成于部分的导电线路层12上时(如图2所示)，则粘着层13可不用额外地被移除部分，换言之，步骤S113可视情况而省略。
下一步，放置一芯片14于粘着层13上，以使芯片14被粘着层13黏固，然后通过打线或倒装芯片等方式，电性连接芯片14与导电线路层12(步骤S115，如图1或图6所示)。
芯片14与导电线路层12耦接后，接着可放置一转接元件15于芯片14上，并且通过打线或倒装芯片等方式，电性连接芯片14与转接元件15(步骤S117，如图3所示)。之后，可放置另一芯片17于转接元件15上(步骤S119，如图4所示)，并使芯片17与转接元件15、芯片14及/或导电线路层12电性连接。
在步骤S115、S117或S119后，可将现阶段完成的芯片封装结构放入一模具(图未示)中，然后注入一封装胶体20。待封装胶体20固化后，封装胶体20可至少包覆芯片14、粘着层13及导电线路层12(步骤S121，如图7所示)。若芯片17或转接元件15存在时，封装胶体20也可一并将芯片17或转接元件15包覆。
需说明的是，若欲制造的芯片封装结构无封装胶体20的需求，则步骤S121可省略。
在封装胶体20固化后，可移除部分的保护层11，以在保护层11中形成至少一贯穿孔111(步骤S123，如图8或图9所示)。如此，导电线路层12的下表面122可部分地暴露于贯穿孔111中。接着，可设置至少一导电材料21A或金属凸块21B于贯穿孔111中，并使得导电材料21A或金属凸块21B接触导电线路层12(步骤S125，如图8或图9所示)。
或者，在封装胶体20固化后，可移除全部的保护层11，使得导电线路层12的下表面122皆暴露出(步骤S127，如图10所示)。
借助上述芯片封装结构的制造方法，各种芯片封装结构可被制造出。
综合上述，本发明的芯片封装结构及芯片封装结构的制造方法可至少具有以下特点：
1.因为芯片与导电金属层之间可仅设有粘着层，故芯片封装结构的整体厚度可较少，以利应用于厚度较薄的电子产品中。
2.芯片封装结构可包含转接元件，以减少芯片的打线距离及打线高度。且转接元件可包含天线、电容器、电感器等元件，以扩充芯片封装结构的功能。
3.芯片封装结构可不包含保护层，以进一步减少芯片封装结构的厚度。
4.芯片封装结构的制造方法可轻易地实施。
上述的实施例仅用来例举本发明的实施态样，以及阐释本发明的技术特征，并非用来限制本发明的保护范畴。任何熟悉此技术者可轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利保护范围应以申请专利范围为准。

Claims (11)

1.一种芯片封装结构的制造方法，其特征在于包含：
提供一保护层；
形成一导电线路层于该保护层上；
形成一粘着层于该导电线路层上；
放置一芯片于该粘着层上；
移除部分的该粘着层，以形成至少一贯穿孔于该粘着层中，使得该导电线路层的一上表面部分地暴露于该粘着层中的该贯穿孔中；以及
通过该粘着层中的该贯穿孔电性连接该芯片与该导电线路层。
2.根据权利要求1所述的芯片封装结构的制造方法，其特征在于该粘着层直接地形成于该导电线路层上，以接触该导电线路层。
3.根据权利要求1所述的芯片封装结构的制造方法，其特征在于还包含：
形成一绝缘层于该导电线路层上；以及
形成该粘着层于该绝缘层上。
4.根据权利要求1所述的芯片封装结构的制造方法，其特征在于该粘着层形成于部分的该导电线路层上。
5.根据权利要求1所述的芯片封装结构的制造方法，其特征在于形成一导电线路层于该保护层上的步骤中，还包含：
形成一金属层于该保护层上；以及
移除部分的该金属层，以形成该导电线路层。
6.根据权利要求1所述的芯片封装结构的制造方法，其特征在于该芯片与该导电线路层以打线方式或倒装芯片方式，来达成电性连接。
7.根据权利要求1所述的芯片封装结构的制造方法，其特征在于还包含：
移除部分的该保护层，以形成至少一贯穿孔于该保护层中，使得该导电线路层的一下表面部分地暴露于该保护层中的该贯穿孔中。
8.根据权利要求7所述的芯片封装结构的制造方法，其特征在于还包含：
设置至少一导电材料或金属凸块于该保护层中的该贯穿孔中，并接触该导电线路层。
9.根据权利要求1所述的芯片封装结构的制造方法，其特征在于还包含：
移除全部的该保护层。
10.根据权利要求1所述的芯片封装结构的制造方法，其特征在于还包含：
放置一转接元件于该芯片上，并电性连接该芯片与该转接元件。
11.根据权利要求1所述的芯片封装结构的制造方法，其特征在于还包含：
使用一封装胶体来包覆该芯片、该粘着层及该导电线路层。
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