CN103000224A - Method for erasing memory chip - Google Patents

Abstract

The invention discloses a method for erasing a memory chip. The common source of the memory chip is changed from being grounded to a current limiting device. The method includes: preprogramming the blocks in the memory unit; The unit is erased; the memory cell after erasing is verified; and the soft programming verification is performed in units of bit lines. Utilizing the present invention, while effectively shortening the erasing time, due to the use of the current limiting device, although multiple units are erased at the same time, the current flowing through the memory unit will not be too large to cause the memory unit to be destroyed. This ensures the reliability of the erasing operation, so it is especially suitable for large-capacity memory chips.

Description

A method for erasing a memory chip

technical field

The invention relates to the technical field of integrated circuits and nonvolatile memory chips, in particular to a method for erasing memory chips.

Background technique

Non-volatile memory is a rapidly developing field. Most storage devices used in non-volatile memory chips now use floating gate structure storage devices, and erasing the floating gate structure storage devices mostly uses electrically erasable Way. During erasing, a negative bias voltage is applied to the floating gate, and a positive bias voltage is applied to the substrate at the same time, thereby removing electrons on the floating gate to realize erasing of the storage device with a floating gate structure.

One problem with erasing floating gate memory devices is over-erasing. When the electrons on the floating gate are removed too much, over-erasing will occur. At this time, there will be a certain amount of positive charge on the floating gate, making the storage device in a slightly open state, and there will be leakage current in the device channel. exist. This will cause misreading and will hinder the next programming, because if you want to program completely, you need to add more electrons to the floating gate than normal to neutralize the positive charge present on the floating gate.

For memory cells with over-erased phenomena, soft programming is required, that is, to remove excess positive charges on the floating gate to restore the memory cells to normal conditions. During soft programming, a positive voltage lower than that during programming is applied to the gate terminal, and a certain positive voltage is applied to the drain terminal, so that a certain current flows in the channel, and some of the electrons will be captured on the floating gate, thereby neutralizing The positive charge left on the floating gate when over erased.

The existing commonly used method of erasing a memory chip is shown in Figure 1. First, the memory cells to be erased are pre-programmed, and then the erasing operation is performed, and then the bit (Byte) is erased and verified, and soft programming is performed. And soft programming verification is also Byte-by-Byte. The method is described in detail as follows:

(1) Pre-program the selected block (Sector), that is, add appropriate positive voltages (such as 7V and 4V) to the gate and drain of the memory cell respectively, so that the current flows in the channel of the memory cell, and the current The electrons in the floating gate are captured, thus programming all the selected memory cells to 0;

(2) Erase all memory cells, that is, apply an appropriate negative voltage (such as -9V) to the gate terminal of the memory cell, and apply an appropriate positive voltage (such as 7V) to the substrate to remove the electrons on the floating gate. Thus all memory cells are erased to 1;

(3) Verify the memory cell after erasing, that is, take Byte as the unit, add appropriate positive voltages (such as 5V and 1V respectively) to the gate terminal and drain terminal of the memory cell, and flow through the memory cell by reading The current in judges whether the erasing is successful. If the erasure is successful, the Byte address will be set to zero, and the erasure verification will be performed, otherwise, the Sector will be erased again. If the number of times of erasing the same Sector exceeds a certain number of times, such as MAX (8), in order to prevent damage to some normal cells, it is generally considered that the erasing is wrong, an error message is generated, and the erasing is exited;

(4) Erase verification (i.e. soft programming verification) has been performed in units of Bytes, that is, in units of Bytes, an appropriate positive voltage is applied to the gate and drain terminals of the memory cell (such as 5V and 1V respectively), and passed Read the current flowing through the memory cell to judge whether the erasing is successful. If it passes, then transfer to the next Byte address; otherwise, perform soft programming on the Byte, and then turn to erase verification; if the number of soft programming for the same Byte exceeds Maxu times, return an error message and enter the next Byte address until The last Byte in the selected Sector.

For a memory chip with a small storage capacity, this method has high reliability and a reasonable time, so it is a good choice. But when the storage capacity becomes large, this method will consume a long time to operate, which will be a serious disadvantage for the use of memory chips.

Contents of the invention

(1) Technical problems to be solved

Aiming at the problem that the existing erasing method takes too long, the main purpose of the present invention is to provide a method for erasing a memory chip, so as to shorten the erasing time and ensure the reliability of the chip.

(2) Technical solution

In order to achieve the above object, the present invention proposes a method for erasing the memory chip, changing the common source of the memory chip from the grounding mode to the current limiting device, the method includes: pre-programming the blocks in the memory unit ; Erase all the memory cells; verify the erased memory cells; and perform soft programming verification in units of bit lines.

In the above solution, the method of changing the common source of the memory chip from grounding to the current limiting device is to connect the source end of the storage unit of the memory chip to the drain end of the current limiting device.

In the above solution, the preprogramming of the block in the memory cell includes: respectively applying a positive voltage to the gate terminal and the drain terminal of the memory cell, so that a current flows in the channel of the memory cell, and the electrons in the current are captured by the floating gate, thus Program the memory cell to 0. The positive voltage applied to the gate terminal of the storage unit is 7V, and the positive voltage applied to the drain terminal of the storage unit is 4V.

In the above solution, the erasing of all memory cells includes: applying negative pressure to the gate terminals of the memory cells, and applying positive pressure to the substrate to remove electrons on the floating gates, thereby erasing all memory cells to 1. The negative voltage applied to the gate terminal of the memory cell is -9V, and the positive voltage applied to the substrate is 7V.

In the above solution, the verification of the memory cell after erasing includes: taking the bit line as a unit, applying positive voltage to the gate terminal and the drain terminal of the memory cell respectively, and judging whether to erase or not by reading the current flowing through the memory cell. If the erasing is successful, set the bit line address to zero and transfer to over-erasing verification, otherwise the block will be erased again; if the erasing times of the same block exceed a certain number of times, it will be considered that the erasing error , an error message is generated, and the erase is exited. The positive voltage applied to the gate terminal of the storage unit is 5V, and the positive voltage applied to the drain terminal of the storage unit is 1V.

In the above solution, the soft programming verification in units of bit lines includes: taking bit lines as units, respectively applying positive voltages to the gate terminal and drain terminal of the memory cell, and judging whether to erase or not by reading the current flowing through the memory cell. In addition, if the erasing is successful, then transfer to the next bit line address; otherwise, perform soft programming on the bit line, and then turn to erase verification; if the number of soft programming times for the same bit line exceeds the set maximum number of times, Then an error message is returned, and the address of the next bit line is entered until the last bit line in the selected block. The positive voltage applied to the gate terminal of the storage unit is 5V, and the positive voltage applied to the drain terminal of the storage unit is 1V.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. Compared with the conventional methods for erasing memory chips, the present invention does not need to make major changes to the circuit. It only needs to change the common source of the original memory array from the grounding mode to the current limiting device, and the current limiting The device is shown in FIG. 3 , the source terminal of the storage unit 320 is connected to the drain terminal of the current limiting device 322 , which is easy to implement.

2. While effectively shortening the erasing time, due to the use of the current limiting device, although multiple cells are erased at the same time, the current flowing through the storage unit will not be made (the mirror effect makes the current and the current in the current limiting device Proportional to the current) is too large to destroy the memory cell, which ensures the reliability of the erasing operation, so it is especially suitable for large-capacity memory chips.

Description of drawings

FIG. 1 is a flow chart of a conventional method for erasing a memory chip;

2 is a flowchart of a method for erasing a memory chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a current limiting device according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The method for erasing a memory chip proposed by the present invention, its basic idea is all aimed at a bit line (Bit line) when erasing verification, soft programming and soft programming verification, and the common source of the memory chip is grounded Connecting to the current limiting device specifically includes: pre-programming the blocks in the memory cells; erasing all the memory cells; verifying the memory cells after erasing; and performing soft programming verification in units of bit lines.

In order to damage the unit and circuit due to the excessive current flowing through the memory cell during erasing verification and soft programming verification, a current limiting device is added to the source end of the memory cell. In order to ensure the reliability of soft programming, a current limiting device is added to the source end of the memory cell so that the soft programming current does not exceed a certain value, so that under the condition of constant current, the cells with over-erased phenomenon are compared with those without over-erased Over-erased cells will flow more current, so that soft programming is mainly concentrated on cells with over-erased phenomena. Appropriate control circuits are added in the word line direction so that all word lines are selected during erasure verification, soft programming verification and soft programming.

FIG. 2 is a flow chart of a method for erasing a memory chip according to an embodiment of the present invention. The method is specifically described as follows:

(1) Pre-program the selected block (Sector), that is, add appropriate positive voltages (such as 7V and 4V) to the gate and drain of the memory cell respectively, so that the current flows in the channel of the memory cell, and the current The electrons in the floating gate are captured, thus programming all the selected memory cells to 0;

(2) Erase all memory cells, that is, apply an appropriate negative voltage (such as -9V) to the gate terminal of the memory cell, and apply an appropriate positive voltage (such as 7V) to the substrate to remove the electrons on the floating gate. Thus all memory cells are erased to 1;

(3) Verify the memory cell after erasing, that is, take the bit line (Bit line) as the unit, add appropriate positive voltages (such as 5V and 1V respectively) to the gate and drain of the memory cell, and pass the read Take the current flowing in the memory cell to judge whether the erasing is successful. If the erasure is successful, the Bitline address will be set to zero, and the erasure verification will be performed, otherwise, the Sector will be erased again. If the number of times of erasing the same Sector exceeds a certain number of times, such as MAX (8), it is generally considered that the erasing error occurs, an error message is generated, and the erasing is exited;

(4) Erase verification (i.e. soft programming verification) has been performed in the unit of Bit line, that is, in the unit of Bit line, an appropriate positive voltage is applied to the gate and drain of the memory cell (such as 5V and 1V respectively) , judge whether the erasing is successful by reading the current flowing through the memory cell. If it passes, turn to the next Bit line address; otherwise, perform soft programming on the Bit line, and then turn to erase verification; if the number of soft programming times for the same Bitline exceeds the set maximum number of times (Masu), an error will be returned Information, enter the next Bit line address, until the last Bit line in the selected Sector.

In order to improve the reliability of erasing verification, over-erasing verification and soft programming in the above solution, the present invention proposes a solution of adding a current limiting device at the source end of the storage unit. 3 is a schematic diagram of a current limiting device according to an embodiment of the present invention, wherein the first transistor 310 of the device, the second transistor 312 and the current limiting device 322 play a mirror image, and the source terminal of the storage unit 320 and the drain of the current limiting device 322 end connection. This is a current mirror structure, the current of the first transistor 310 is controlled by Vload, and the current mirror of the first transistor 310 is mirrored to the current limiting device 322 through the current mirror composed of the second transistor 312 and the current limiting device 322; the current limiting device 322 The drain terminal of is connected to the source terminal of the storage unit 320 . According to the principle of the mirror circuit, it can be known that the current flowing through the storage unit 320 is proportional to the current flowing through the first transistor 310, so adopting such a structure can effectively control the current flowing through the storage unit 320 by controlling the current of the first transistor 310. Current can protect circuits and memory cells. At the same time, since the current is constant, during soft programming, the current tends to flow through cells with over-erased phenomena, which improves the efficiency and reliability of soft programming.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A method for erasing a memory chip is characterized in that the common source of the memory chip is changed from a grounding mode to a current limiting device, the method comprising: pre-programming blocks in memory cells; Erase all memory cells; verifying the erased memory cell; and Soft programming verification is performed in units of bit lines. 2. The method for erasing a memory chip according to claim 1, wherein said changing the common source of the memory chip from the grounding mode to the current limiting device is to change the source of the storage unit of the memory chip The terminal is connected to the drain terminal of the current limiting device. 3. The method for erasing a memory chip according to claim 1, wherein said pre-programming the block in the storage unit comprises: A positive voltage is applied to the gate and drain of the memory cell, so that a current flows through the channel of the memory cell, and the electrons in the current are captured by the floating gate, thus programming the memory cell to 0. 4. The method for erasing a memory chip according to claim 3, wherein the positive voltage applied to the gate terminal of the storage unit is 7V, and the positive voltage applied to the drain terminal of the storage unit is 4V. 5. The method for erasing a memory chip according to claim 1, wherein said erasing all memory cells comprises: Negative voltage is applied to the gate terminal of the memory cell, and positive pressure is applied to the substrate to remove electrons on the floating gate, thus erasing all memory cells to 1. 6. The method for erasing a memory chip according to claim 5, wherein the negative voltage applied to the gate terminal of the memory cell is -9V, and the positive voltage applied to the substrate is 7V. 7. The method for erasing a memory chip according to claim 1, wherein said verifying the memory unit after erasing comprises: Take the bit line as the unit, apply positive voltage to the gate terminal and the drain terminal of the memory cell respectively, and judge whether the erasing is successful by reading the current flowing through the memory cell. If the erasing is successful, set the address of the bit line to zero and turn to If the erasure verification has been entered, otherwise the block will be erased again; if the same block has been erased for more than a certain number of times, it will be considered an error in the erasure, an error message will be generated, and the erasure will exit. 8 . The method for erasing a memory chip according to claim 7 , wherein the positive voltage applied to the gate terminal of the storage unit is 5V, and the positive voltage applied to the drain terminal of the storage unit is 1V. 9. The method for erasing a memory chip according to claim 1, wherein said performing soft programming verification in units of bit lines comprises: Take the bit line as the unit, apply positive voltage to the gate terminal and the drain terminal of the memory cell respectively, and judge whether the erasing is successful by reading the current flowing through the memory cell. If the erasing is successful, transfer to the next bit line address; Otherwise, perform soft programming on the bit line, and then turn to erase verification; if the number of soft programming times on the same bit line exceeds the set maximum number of times, return an error message and enter the next bit line address until the selected block last bit line. 10 . The method for erasing a memory chip according to claim 9 , wherein the positive voltage applied to the gate terminal of the storage unit is 5V, and the positive voltage applied to the drain terminal of the storage unit is 1V. 11 .

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