CN102983403A

CN102983403A - Azimuth calibration circuit for TACAN phased-array antenna

Info

Publication number: CN102983403A
Application number: CN2012105658136A
Authority: CN
Inventors: 文佳伟; 潘国翠; 任宏伟; 陈明权
Original assignee: Tianjin 764 Communication and Navigation Technology Corp
Current assignee: Tianjin 764 Communication and Navigation Technology Corp
Priority date: 2012-12-24
Filing date: 2012-12-24
Publication date: 2013-03-20

Abstract

The invention relates to an azimuth calibration circuit for a TACAN (tactical air navigation) phased-array antenna, which is formed by connecting a one-out-of-thirty-six circuit, four phase shifters and a BUTLER network, wherein the one-out-of-thirty-six circuit consists of an ARM (advanced reduced instruction-set computer machine) chip, an EEPROM (electrically erasable programmable read-only memory), a control unit, an FPGA (field programmable gate array) chip, a CPLD (complex programmable logic device) chip and a DG506AAK chip. According to the azimuth calibration circuit for the TACAN phased-array antenna, an ARM procedure, an FPGA procedure and a CPLD procedure are implemented; detection signals are collected by the ARM chip; and power modulation degree information of the signals emitted by poles is figured out. The electrically-tunable phase shifters can be controlled by antenna software to allow the four phase shifters to generate stepping phase shift that are required by 15Hz and 135Hz modulation for modulating carrier waves; and a nine-petal heart-shaped rotation azimuth picture is formed finally. The azimuth calibration circuit can monitor properties of the antenna and the emitted signals simultaneously, conducts the phase calibration on the antenna and has an angular adjustment function, a gate swing modification function and a power modulation degree detection function; and the adjustment and control in a whole frequency band can be achieved, so that the performance can be optimized.

Description

Tacan phased array antenna bearing calibration circuit

Technical field

The present invention relates to airmanship, particularly a kind of Tacan phased array antenna bearing calibration circuit.

Background technology

The major function of Tacan phased array antenna is the horizontal directivity pattern that produces a rotation, horizontal directivity pattern is that nine lobes are heart-shaped, with per second 15 week rotation, make transmitter output constant amplitude pulse signal be subject to the envelope modulation of 15Hz and 135Hz sinusoidal signal, the signal after the modulation and major-minor benchmark are determined the beacon orientation for airborne equipment together.The phased E-scan antenna of Tacan mainly is comprised of antenna body, antenna electronics unit, antenna monitoring unit three parts.Wherein antenna body comprises the cylindrical-array that 36 oscillator row consist of, a BUTLER network mould, 4 voltage controlled phase shifters and 36 sampling wave detectors.Tacan is operated in 962MHz～1213MHz band limits, and active service Tacan antenna performance is determined by antenna body hardware fully, can't realize that performance is best in the full frequency band, and the coherence request to hardware in the production process is very high, is difficult to realize, wastes time and energy.

Summary of the invention

Purpose of the present invention is exactly for overcoming the deficiencies in the prior art, a kind of design of Tacan phased array antenna bearing calibration circuit is provided, by the control of antenna software realization to voltage controlled phase shifter, so that 4 phase shifters produce 15Hz and the required stepping phase shift of 135Hz modulation, be used for modulated carrier, finally form the heart-shaped direction of rotation figure of nine lobes on the space; Simultaneously monitoring aerial and the performance that transmits and antenna carried out phase alignment, angle regulation function, door pendulum debugging functions, power modulation degree measuring ability is realized in the full frequency band adjustable controlledly, makes performance reach best.

The present invention realizes by such technical scheme: Tacan phased array antenna bearing calibration circuit, it is characterized in that, the 36 tunnel select 1 circuit, No. four phase shifters, BUTLER network connection to consist of by what ARM chip, eeprom memory, control unit, fpga chip, CPLD chip, DG506AAK chip formed; Tacan phased array antenna bearing calibration circuit gathers rectified signal by carrying out ARM program, FPGA program, CPLD program by the ARM chip, and calculates the power modulation degree information that each a period of time launches signal; The phase-modulation increment that calculates each phase shifter after receiving calibration command sends to fpga chip, and data are preserved in real time, and fpga chip reads the data that the ARM chip sends, and sends to the CPLD chip of electronic unit; Producing simultaneously primary standard, the accurate pulse of prothetic group delivers to main frame and realizes that orientation angles adjusts function; Produce the clock signal of the required 552960KHz of CPLD chip; Produce 15Hz undersuing INT to the ARM chip, the CPLD chip is finished the address decoding of 4 phase shifters and control, finishes 36 decoding and the controls of selecting 1 circuit.

Tacan phased array antenna bearing calibration circuit, its implementation comprises the steps:

1) power on after, the ARM chip reads the data of EEPROM the inside, data comprise: mode of operation, 4 phase shifter phase-modulation increments, angle adjustment value, and above parameter sent to fpga chip, fpga chip carries out work according to the mode of operation of ARM chip output, and with phase shifter phase-modulation incremental update to the CPLD chip, thereby make before state and the power down after powering on consistent;

2) starting point of sampling, the 15Hz clock signal that is provided by fpga chip are provided antenna calibration process: INT; ARM samples to the antenna rectified signal and calculates, and calculates the phase-modulation increment of four phase shifters, realizes the calibration of phase place.

3) observation process: the ARM chip receives after the start-up command, 36 oscillators of gating one by one, and calculate its power, the modulation degree of 135Hz modulation degree and 15Hz signal; The starting point of sampling, the 15Hz clock signal that is provided by fpga chip are provided INT;

4) fpga chip implementation method mainly contains two parts content: one, and control command transmission is read the TACAN/DME pattern that the ARM chip sends, switch command and the phase calibration values of 4 phase shifters, and is sent to the CPLD chip; Its two, clock generating and orientation angles adjustment produce major-minor reference signal (Tacan main frame with);

5) CPLD chip implementing method: the CPLD chip reads the data that fpga chip sends, decoding also realizes phase shifter and 36 road oscillators are selected 1 tunnel control, be specially: the phase shifter that sends according to the ARM chip number is to the obstruction assignment of four phase shifters, the phase shifter calibration value that sends according to ARM is to 4 phase shifter Data Update, i.e. data correction; The oscillator that sends according to ARM number is 1～36, realizes selecting 1 control to 36;

The ARM chip adopts LPC2378, and fpga chip adopts EP1C12Q240, and the CPLD chip adopts LCMXO640-T100.

The invention has the beneficial effects as follows: by the control of antenna software realization to voltage controlled phase shifter, so that 4 phase shifters produce 15Hz and the required stepping phase shift of 135Hz modulation, be used for modulated carrier, the final heart-shaped direction of rotation figure of nine lobes that forms on the space, simultaneously monitoring aerial and the performance that transmits and antenna carried out phase alignment, angle regulation function, door pendulum debugging functions, power modulation degree measuring ability realizes that full frequency band is interior adjustable controlled, makes performance reach best.

Description of drawings

Fig. 1, antenna calibration circuit hardware block diagram;

Fig. 2, calibration flow chart;

Fig. 3, power modulation degree monitoring flow chart;

Fig. 4, FPGA implementation method flow chart;

Fig. 5, CPLD implementation method flow chart.

For a more clear understanding of the present invention, describe in conjunction with the accompanying drawings and embodiments the present invention in detail:

To shown in Figure 5, the antenna calibration circuit hardware 36 the tunnel selects 1 circuit, No. four phase shifters to connect and compose by what ARM (chip), EEPROM (memory), control unit, FPGA (chip), CPLD (chip), DG506AAK (chip) formed such as Fig. 1;

By the control of antenna software realization to voltage controlled phase shifter, so that 4 phase shifters produce 15Hz and the required stepping phase shift of 135Hz modulation, be used for modulated carrier, finally form the heart-shaped direction of rotation figure of nine lobes on the space; Simultaneously monitoring aerial and the performance that transmits and antenna carried out phase alignment, angle regulation function, door pendulum debugging functions, power modulation degree measuring ability.

Software is comprised of 3 subprograms: ARM (LPC2378) program, FPGA(EP1C12Q240) program, CPLD(LCMXO640-T100) program, gather rectified signal by ARM, and calculate the power modulation degree information that each a period of time launches signal; The phase-modulation increment that calculates each phase shifter after receiving calibration command sends to FPGA, and data are preserved in real time.FPGA reads the data that ARM sends, and sends to the CPLD of electronic unit; Produce simultaneously primary standard, main frame (orientation angles adjustment function) is delivered in the accurate pulse of prothetic group; Produce the clock signal of the required 552960KHz of CPLD; Produce 15Hz undersuing INT to ARM.CPLD finishes the address decoding of 4 phase shifters and control; Finish 36 decoding and the controls of selecting 1 circuit.After powering on, ARM reads the data (mode of operation, 4 phase shifter phase-modulation increments, angle adjustment value) of EEPROM the inside, and above parameter sent to FPGA, FPGA carries out work according to the mode of operation of ARM output, and with phase shifter phase-modulation incremental update to CPLD, thereby make before state and the power down after powering on consistent.

As shown in Figure 2, the starting point of sampling, the 15Hz clock signal that is provided by FPGA are provided calibration flow chart: INT.ARM samples to the antenna rectified signal and calculates, and calculates the phase-modulation increment of four phase shifters, realizes the calibration of phase place.

As shown in Figure 3, power modulation degree monitoring flow process, ARM receives after the start-up command, 36 oscillators of gating one by one, and calculate its power, the modulation degree of 135Hz modulation degree and 15Hz signal.The starting point of sampling, the 15Hz clock signal that is provided by FPGA are provided INT.

As shown in Figure 4, FPGA implementation method: the FPGA implementation method mainly contains two parts content.One, control command transmission (read the TACAN/DME pattern that ARM sends, switch command and the phase calibration values of 4 phase shifters, and send to CPLD); Its two, clock generating and orientation angles adjustment (producing major-minor reference signal).

As shown in Figure 5, CPLD implementation method: CPLD reads the data that FPGA sends, and decoding also realizes phase shifter and 36 road oscillators are selected 1 tunnel control.Be specially: the phase shifter that sends according to ARM number is to the obstruction assignment of four phase shifters, and concrete agreement sees Table 1; The phase shifter calibration value that sends according to ARM is to 4 phase shifter Data Update, i.e. data correction; According to the oscillator number (1～36) that ARM sends, realize selecting 1 control to 36.

The meaning of table 1 phase shifter number

Phase shifter number	Meaning
			0	4 whole conductings of phase shifter
1	Phase shifter 1 conducting, other obstruction
		2	Phase shifter 2 conductings, other obstruction
3	Phase shifter 3 conductings, other obstruction
		4	Phase shifter 4 conductings, other obstruction
5	Phase shifter 1,2 conductings, other obstruction
		6	Phase shifter 3,4 conductings, other obstruction
7	4 phase shifters all block

Annotate: it is noted that during programming phase shifter that Tian Mao and match ounce company produce about obstruction during with positive and reverse return the increase and decrease definition possibility of number different.

Phase shifter control signal highest order is the phase shifter obstruction, low four groups of four figures for the rotation of control phase shifter.4 phase shifters are the low level conducting, and high level blocks.

Voltage controlled phase shifter to 4 basic 0/1 codings, is realized different phase shift states by digital control circuit.

According to the above description, can reproduce the present invention in conjunction with professional knowledge.

Claims

1. Tacan phased array antenna bearing calibration circuit is characterized in that, the 36 tunnel selects 1 circuit, No. four phase shifters, BUTLER network connection to consist of by what ARM chip, eeprom memory, control unit, fpga chip, CPLD chip, DG506AAK chip formed; Tacan phased array antenna bearing calibration circuit gathers rectified signal by carrying out ARM program, FPGA program, CPLD program by the ARM chip, and calculates the power modulation degree information that each a period of time launches signal; The phase-modulation increment that calculates each phase shifter after receiving calibration command sends to fpga chip, and data are preserved in real time, and fpga chip reads the data that the ARM chip sends, and sends to the CPLD chip of electronic unit; Producing simultaneously primary standard, the accurate pulse of prothetic group delivers to main frame and realizes that orientation angles adjusts function; Produce the clock signal of the required 552960KHz of CPLD chip; Produce 15Hz undersuing INT to the ARM chip, the CPLD chip is finished the address decoding of 4 phase shifters and control, finishes 36 decoding and the controls of selecting 1 circuit.

2. Tacan phased array antenna bearing calibration circuit as claimed in claim 1, its implementation comprises the steps:

2) starting point of sampling, the 15Hz clock signal that is provided by fpga chip are provided antenna calibration process: INT; ARM samples to the antenna rectified signal and calculates, and calculates the phase-modulation increment of four phase shifters, realizes the calibration of phase place;

4) fpga chip implementation method mainly contains two parts content: one, and control command transmission is read the TACAN/DME pattern that the ARM chip sends, switch command and the phase calibration values of 4 phase shifters, and is sent to the CPLD chip; Its two, clock generating and orientation angles adjustment produce major-minor reference signal;

5) CPLD chip implementing method: the CPLD chip reads the data that fpga chip sends, decoding also realizes phase shifter and 36 road oscillators are selected 1 tunnel control, be specially: the phase shifter that sends according to the ARM chip number is to the obstruction assignment of four phase shifters, the phase shifter calibration value that sends according to ARM is to 4 phase shifter Data Update, i.e. data correction; The oscillator that sends according to ARM number is 1～36, realizes selecting 1 control to 36.

3. Tacan phased array antenna bearing calibration circuit as claimed in claim 1 is characterized in that, the ARM chip adopts LPC2378, and fpga chip adopts EP1C12Q240, and the CPLD chip adopts LCMXO640-T100.