CN102968389B - Based on storing device and the storage means of multi-level flash memory cell - Google Patents
Based on storing device and the storage means of multi-level flash memory cell Download PDFInfo
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- CN102968389B CN102968389B CN201210423934.7A CN201210423934A CN102968389B CN 102968389 B CN102968389 B CN 102968389B CN 201210423934 A CN201210423934 A CN 201210423934A CN 102968389 B CN102968389 B CN 102968389B
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Abstract
The present invention is applicable to technical field of memory, provide a kind of storing device based on multi-level flash memory cell, the storage zone comprising flash controller and be made up of multi-level flash memory cell, described storage zone comprises the first logic subregion and the 2nd logic subregion, described first logic subregion is for storing data, when described flash controller and described first logic subregion carry out data transmission, described 2nd logic subregion makes the cache memory between described flash controller and the first logic subregion. The present invention is also corresponding provides a kind of storage means realized by said apparatus. Whereby, the present invention can effectively improve the storage speed of multi-level flash memory cell storing device.
Description
Technical field
The present invention relates to technical field of memory, particularly relate to a kind of storing device based on multi-level flash memory cell and storage means.
Background technology
Current NANDFlash mainly contains three types, it is single layer cell (Single-LevelCell respectively, be called for short SLC), multilevel-cell (Multi-LevelCell, be called for short MLC) and three-layer unit (Triple-LevelCell, abbreviation TLC). Wherein SLC can store 1bit/cell, and feature is that storage speed is fast, life-span length (about 100,000 times are erasable), but can storage space little and price is super expensive; TLC can store 3bit/cell, be characterized in that storage space is big, price cheap, but storage speed is slow and the life-span short (only can erasable 500-3000 time); MLC can store 2bit/cell, and the features such as its storage space, price, storage speed and life-span (about 10,000 times erasable) are all between SLC and TLC, and cost performance is relatively high.
For SLC Flash, only comprising a bit in each unit, when SLC programmes, the value of this bit position can only be changed between " 0 " and " 1 " two states. For MLC flash, each unit comprises a least significant bit (LeastSignificantBit, it is called for short LSB) and a highest significant position (MostSignificantBit is called for short MSB), the programming process of each MLC cell is as shown in Figure 1. If each bit is in the state that is wiped free of underlying " 1 " in MLC, so MLC is when erase status E, and MSB and LSB is all set to " 1 ". When being programmed by LSB, if LSB is set to " 1 ", so illustrate that LSB remains on erase status; If LSB is set to " 0 ", so MLC is transformed into state D1 from state E. When being programmed by MSB, if MSB is set to " 1 ", illustrate that MSB is at erase status E or state D1 (depending on the value of LSB); If MSB is set to " 0 ", then considering in two kinds of situation, the original state that a kind of situation is programming is E, then State Transferring is D3, and the original state that another kind of situation is programming is D1, then State Transferring is D2.
Owing to there being E, D1, D2 and D3 tetra-kinds of programming states under MLC flash, and it not that any two states can directly be changed mutually, therefore need cost more time relative to SLC programming. The programming time of usual SLC unit is about 200us, and the programming time of MLC cell is about 800us. In addition, the MLC programming process observing Fig. 1 finds, the programming of LSB is similar to SLC, and institute's spended time is close.
In summary, obviously there is inconvenience and defect in actual use, it is therefore necessary to improved in existing flash memory device.
Summary of the invention
For above-mentioned defect, it is an object of the invention to provide a kind of storing device based on multi-level flash memory cell and storage means.
In order to realize above-mentioned purpose, the present invention provides a kind of storing device based on multi-level flash memory cell, the storage zone comprising flash controller and be made up of multi-level flash memory cell, described storage zone comprises the first logic subregion and the 2nd logic subregion, described first logic subregion is for storing data, when described flash controller and described first logic subregion carry out data transmission, described 2nd logic subregion makes the cache memory between described flash controller and the first logic subregion.
Storing device according to the present invention, the capacity of described first logic subregion is greater than the capacity of the 2nd logic subregion.
Storing device according to the present invention, highest significant position in multi-level flash memory cell and least significant bit can be programmed by the flash array of described first logic subregion simultaneously, and the least significant bit in described multi-level flash memory cell can only be programmed by the flash array of described 2nd logic subregion.
Storing device according to the present invention, described storing device is solid state hard disc.
The present invention is also corresponding provides a kind of storage means realized by said apparatus, and described method comprises:
Described storage zone is divided into the first logic subregion and the 2nd logic subregion, and described first logic subregion is for storing data;
When described flash controller and described first logic subregion carry out data transmission, described 2nd logic subregion makes the cache memory between described flash controller and the first logic subregion.
Storage means according to the present invention, the capacity of described first logic subregion is greater than the capacity of the 2nd logic subregion.
Storage means according to the present invention, highest significant position in multi-level flash memory cell and least significant bit can be programmed by the flash array of described first logic subregion simultaneously, and the least significant bit in described multi-level flash memory cell can only be programmed by the flash array of described 2nd logic subregion.
The present invention is by being divided into two logic subregions by the multilevel-cell storage zone of storing device, first logic subregion and the 2nd logic subregion, using the first logic subregion as the main storage area being used for storing data, 2nd logic subregion is as cache memory, when first logic subregion and outside flash controller carry out data transmission, data are cushioned by the 2nd logic subregion, greatly improve the transmission speed of data whereby.
Accompanying drawing explanation
Fig. 1 is the programming schematic diagram of the flash cell of prior art;
Fig. 2 is the structural representation of the storing device of the present invention;
Fig. 3 is the schema of the storage means of the present invention.
Embodiment
In order to make the object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated. It is to be understood that specific embodiment described herein is only in order to explain the present invention, it is not intended to limit the present invention.
See Fig. 2, the present invention provides a kind of storing device based on multi-level flash memory cell, and it can be solid state hard disc, concrete, and this storing device 100 comprises Flash controller 10 and storage zone 20. Wherein, storage zone 20 is made up of multi-level flash memory cell MLC.
In embody rule, storage zone 20 is divided into two NANDFlash arrays by logic zoning, respectively corresponding first logic subregion 21 and the 2nd logic subregion 22, and when dividing, the capacity of the first logic subregion 21 need to be greater than the capacity of the 2nd logic subregion 22. First logic subregion 21 is for storing data, and when flash controller 10 and the first logic subregion 22 carry out data transmission, the 2nd logic subregion 22 is as the cache memory between flash controller 10 and the first logic subregion 10. Needs illustrate, least significant bit (LSB) can only be programmed by the MLC type NANDFlash array forming the 2nd logic subregion 22, namely MLC type NANDFlash array are used as SLC type and use, improve the program speed of NANDFlash array whereby; The programmed method of the MLC type NANDFlash array forming the first logic subregion 21 is conventional, can the highest significant position (MSB) in MLC and LSB be programmed simultaneously.
In one specific embodiment of the present invention, for the capacity of storage zone 20 as 32GB, MLC type NANDFlash array being divided into two portions of 4GB and 28GB size, namely the capacity of the first logic subregion 21 correspondence is 28GB, and the capacity of the 2nd logic subregion 22 is 4GB.
In practical application, the MLC type NANDFlash array of the 4GB of the 2nd logic subregion 22 is converted to the high speed MLC type NANDFlash array of 2GB, implementation is as follows: only programmed by LSB when the MLC of the 2nd logic subregion 22 being programmed, and abandon the operation to MSB, namely MLC is used as SLC application, such programmed method can make the storage space of MLC reduce by half, but program speed can significantly improve, thus is converted to the high speed MLC of 2GB. Now, using high speed MLC type NANDFlash array as speed buffering snubber, it is mainly used in cushioning pending data.
2nd logic subregion 22 is placed in as cache memory between Flash controller 10 and the first logic subregion 21, plays function served as bridge. Pending data are put into the 2nd logic subregion 22, Flash controller 10 and are directly read pending data from the 2nd logic subregion 22 by the first logic subregion 21. If Flash controller 10 directly reads the data of the first logic subregion 21, owing to the first logic subregion 21 program speed is much slower than Flash controller 10, the waste of controller resource can be caused, and the speed of cache memory can mate Flash controller 10, therefore this kind of mode can promote the processing speed of data effectively.
Concrete, when storing device 100 write operation, Flash controller 10 to writing order resolve, then data to be written are passed to fast the 2nd logic subregion 22, finally by the 2nd logic subregion 22, data are write in the first logic subregion 21; When storing device 100 reading operates, obtain the first logic subregion 21 reading operating command and transfer data to the 2nd logic subregion 22, read fast for Flash controller 10.
Referring back to Fig. 3, the present invention provides the storage means of a kind of data, and it is realized by storing device as shown in Figure 2, and concrete, the method comprises:
Step S301, the storage zone 20 of storing device 100 is divided into the first logic subregion 21 and the 2nd logic 22 subregion, and first the capacity of logic subregion 21 be greater than the capacity of the 2nd logic subregion 22, the first logic subregion 21 is for storing data, and it is as the main storage space of storage zone 20.
Step S302, when flash controller 10 and the first logic subregion 21 carry out data transmission, the 2nd logic subregion 22 is as the cache memory between flash controller 10 and the first logic subregion 21. Concrete implementation is as follows: the highest significant position in MLC and least significant bit can be programmed by the flash array of the first logic subregion 21 simultaneously, least significant bit in described MLC can only be programmed by the flash array of the 2nd logic subregion 22, make the 2nd logic subregion 22 use as SLC whereby, greatly improve the processing speed of data as Data Buffer Memory.
In sum, the present invention is by being divided into two logic subregions by the multilevel-cell storage zone of storing device, first logic subregion and the 2nd logic subregion, using the first logic subregion as the main storage area being used for storing data, 2nd logic subregion is as cache memory, when first logic subregion and outside flash controller carry out data transmission, data are cushioned by the 2nd logic subregion, greatly improve the transmission speed of data whereby.
Certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when can make various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection domain that all should belong to the claim appended by the present invention.
Claims (3)
1. the storing device based on multi-level flash memory cell, it is characterized in that, the storage zone comprising flash controller and be made up of multi-level flash memory cell, described storage zone comprises the first logic subregion and the 2nd logic subregion, described first logic subregion is for storing data, when described flash controller and described first logic subregion carry out data transmission, described 2nd logic subregion makes the cache memory between described flash controller and the first logic subregion, and the capacity of described first logic subregion is greater than the capacity of the 2nd logic subregion;
Highest significant position in multi-level flash memory cell and least significant bit can be programmed by the flash array of described first logic subregion simultaneously, and the least significant bit in described multi-level flash memory cell can only be programmed by the flash array of described 2nd logic subregion.
2. storing device according to claim 1, it is characterised in that, described storing device is solid state hard disc.
3. the storage means realized by device as claimed in claim 1, it is characterised in that, described method comprises:
Described storage zone is divided into the first logic subregion and the 2nd logic subregion, and described first logic subregion is for storing data;
When described flash controller and described first logic subregion carry out data transmission, described 2nd logic subregion makes the cache memory between described flash controller and the first logic subregion;
Wherein: the capacity of described first logic subregion is greater than the capacity of the 2nd logic subregion, and the highest significant position in multi-level flash memory cell and least significant bit can be programmed by the flash array of described first logic subregion, and the least significant bit in described multi-level flash memory cell can only be programmed by the flash array of described 2nd logic subregion simultaneously.
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| CN201210423934.7A CN102968389B (en) | 2012-10-30 | 2012-10-30 | Based on storing device and the storage means of multi-level flash memory cell |
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| CN201210423934.7A CN102968389B (en) | 2012-10-30 | 2012-10-30 | Based on storing device and the storage means of multi-level flash memory cell |
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| CN102968389B true CN102968389B (en) | 2016-06-01 |
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| WO2016095233A1 (en) * | 2014-12-19 | 2016-06-23 | 北京麓柏科技有限公司 | Method and apparatus for realizing non-volatile cache |
| CN106971372B (en) * | 2017-02-24 | 2020-01-03 | 北京大学 | Coding type flash memory system and method for realizing image convolution |
| CN107301023A (en) * | 2017-06-29 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of solid-state disk configuration information management method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101499315A (en) * | 2008-01-30 | 2009-08-05 | 群联电子股份有限公司 | Average wear method of flash memory and controller thereof |
| CN101556555A (en) * | 2008-04-08 | 2009-10-14 | 群联电子股份有限公司 | Block management method for flash memory, controller and storage system thereof |
| CN101814318A (en) * | 2009-02-25 | 2010-08-25 | 群联电子股份有限公司 | Multi-layer storage unit and non-type flash memory storage system and its controller and access method |
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| KR101464338B1 (en) * | 2007-10-25 | 2014-11-25 | 삼성전자주식회사 | DATA STORAGE DEVICE USING NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND COMPUTER SYSTEM |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101499315A (en) * | 2008-01-30 | 2009-08-05 | 群联电子股份有限公司 | Average wear method of flash memory and controller thereof |
| CN101556555A (en) * | 2008-04-08 | 2009-10-14 | 群联电子股份有限公司 | Block management method for flash memory, controller and storage system thereof |
| CN101814318A (en) * | 2009-02-25 | 2010-08-25 | 群联电子股份有限公司 | Multi-layer storage unit and non-type flash memory storage system and its controller and access method |
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