CN102968389A - Storage device and storage method based on multi-level flash memory cell - Google Patents
Storage device and storage method based on multi-level flash memory cell Download PDFInfo
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- CN102968389A CN102968389A CN2012104239347A CN201210423934A CN102968389A CN 102968389 A CN102968389 A CN 102968389A CN 2012104239347 A CN2012104239347 A CN 2012104239347A CN 201210423934 A CN201210423934 A CN 201210423934A CN 102968389 A CN102968389 A CN 102968389A
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Abstract
The invention is suitable for the technical field of the storage, which provides a storage device based on a multi-level flash memory cell. The storage device comprises a flash memory controller and a storage area consisting of the multi-level flash memory cell, wherein the storage area comprises a first logic subarea and a second logic subarea; the first logic subarea is used for storing data; and when the flash memory controller and the first logic subarea transmit data, the second logic subarea is used as a high-speed buffer memory between the flash memory controller and the first logic subarea. The invention also correspondingly provides a storage method realized by the device. Therefore, according to the invention, the storage speed of the storage device based on the multi-level flash memory cell can be effectively improved.
Description
Technical field
The present invention relates to technical field of memory, relate in particular to a kind of memory storage based on the multilayer flash cell and storage means.
Background technology
NAND Flash mainly contains three types at present, is respectively single layer cell (Single-Level Cell is called for short SLC), multilevel-cell (Multi-Level Cell is called for short MLC) and three-layer unit (Triple-LevelCell is called for short TLC).Wherein SLC can store 1bit/cell, and characteristics are that storage speed is fast, the life-span long (about 100,000 times erasable), but but storage space is little and price is super expensive; TLC can store 3bit/cell, is characterized in that storage space is large, low price, but storage speed is slow and the life-span short (only erasable 500-3000 time); MLC can store 2bit/cell, and all between SLC and TLC, cost performance is relatively high for the characteristics such as its storage space, price, storage speed and life-span (about 10,000 times erasable).
For the SLC flash memory, only comprise a bit in each unit, during the SLC programming, the value of this bit can only be changed between " 0 " and " 1 " two states.For the MLC flash memory, comprise a least significant bit (LSB) (Least Significant Bit is called for short LSB) and a highest significant position (Most SignificantBit is called for short MSB) in each unit, the programming process of each MLC unit is as shown in Figure 1.If each bit is being wiped free of set under the state among the MLC, MLC is when erase status E so, and MSB and LSB are all by set.When LSB is programmed, if LSB, illustrates so that LSB remains on erase status by set; If LSB is by reset, MLC is transformed into state D1 from state E so.When MSB is programmed, if MSB, illustrates that MSB is at erase status E or state D1 (value that depends on LSB) by set; If MSB, considers in two kinds of situation then that a kind of situation is that the original state of programming is E by reset, then state is converted to D3, and another kind of situation is that the original state of programming is D1, and then state is converted to D2.
Owing under the MLC flash memory E, D1, D2 and four kinds of programming states of D3 are arranged, and are not that any two states can directly be changed mutually, therefore need the cost more time with respect to the SLC programming.Usually the programming time of SLC unit is about 200us, and the programming time of MLC unit is about 800us.In addition, observe the MLC programming process of Fig. 1 and find that the programming of LSB is similar to SLC, institute's spended time is close.
In summary, existing flash memory device obviously exists inconvenience and defective in actual use, so be necessary to be improved.
Summary of the invention
For above-mentioned defective, the object of the present invention is to provide a kind of memory storage based on the multilayer flash cell and storage means.
To achieve these goals, the invention provides a kind of memory storage based on the multilayer flash cell, comprise flash controller and the memory block that is formed by the multilayer flash cell, described memory block comprises the first logical partition and the second logical partition, described the first logical partition is used for the storage data, when described flash controller and described the first logical partition carried out data transmission, described the second logical partition was made the cache memory between described flash controller and the first logical partition.
According to memory storage of the present invention, the capacity of described the first logical partition is greater than the capacity of the second logical partition.
According to memory storage of the present invention, the flash array of described the first logical partition can be simultaneously to the highest significant position in the multilayer flash cell and least significant bit (LSB) programming, and the flash array of described the second logical partition can only be programmed to the least significant bit (LSB) in the described multilayer flash cell.
According to memory storage of the present invention, described memory storage is solid state hard disc.
The present invention also provides a kind of storage means that realizes by said apparatus accordingly, and described method comprises:
Be the first logical partition and the second logical partition with described memory partitioning, described the first logical partition is used for the storage data;
When described flash controller and described the first logical partition carried out data transmission, described the second logical partition was made the cache memory between described flash controller and the first logical partition.
According to storage means of the present invention, the capacity of described the first logical partition is greater than the capacity of the second logical partition.
According to storage means of the present invention, the flash array of described the first logical partition can be simultaneously to the highest significant position in the multilayer flash cell and least significant bit (LSB) programming, and the flash array of described the second logical partition can only be programmed to the least significant bit (LSB) in the described multilayer flash cell.
The present invention is divided into two logical partitions by the multilevel-cell memory block with memory storage, the first logical partition and the second logical partition, with the first logical partition as the main storage area that is used for the storage data, the second logical partition is as cache memory, when the first logical partition and outside flash controller carry out data transmission, the second logical partition cushions data, greatly improves whereby data transfer speed.
Description of drawings
Fig. 1 is the programming synoptic diagram of the flash cell of prior art;
Fig. 2 is the structural representation of memory storage of the present invention;
Fig. 3 is the process flow diagram of storage means of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Referring to Fig. 2, the invention provides a kind of memory storage based on the multilayer flash cell, it can be solid state hard disc, and is concrete, this memory storage 100 comprises Flash controller 10 and memory block 20.Wherein, memory block 20 is comprised of multilayer flash cell MLC.
In concrete the application, memory block 20 is divided into two NAND Flash arrays by logic area, respectively corresponding the first logical partition 21 and the second logical partition 22, and when dividing, the capacity of the first logical partition 21 needs the capacity greater than the second logical partition 22.The first logical partition 21 is used for the storage data, and when flash controller 10 and the first logical partition 22 carried out data transmission, the second logical partition 22 was as the cache memory between flash controller 10 and the first logical partition 10.Need to illustrate that the MLC type NAND Flash array that consists of the second logical partition 22 can only namely be used as the SLC type to MLC type NANDFlash array and use least significant bit (LSB) (LSB) programming, improves whereby the program speed of NAND Flash array; The programmed method that consists of the MLC type NAND Flash array of the first logical partition 21 is conventional, can be simultaneously to the highest significant position among the MLC (MSB) and LSB programming.
In the specific embodiment of the present invention, 20 capacity is example as 32GB take the memory block, and MLC type NAND Flash array is divided into two parts of 4GB and 28GB size, and namely the capacity of the first logical partition 21 correspondences is 28GB, and the capacity of the second logical partition 22 is 4GB.
In the practical application, the MLC type NAND Flash array of the 4GB of the second logical partition 22 is converted to the high speed MLC type NAND Flash array of 2GB, implementation is as follows: only LSB is programmed when the MLC to this second logical partition 22 programmes, and abandon operation to MSB, namely MLC being used as SLC uses, such programmed method meeting is so that the storage space of MLC reduces by half, but program speed can significantly improve, thereby is converted to the high speed MLC of 2GB.At this moment, high speed MLC type NAND Flash array as the speed buffering impact damper, is mainly used in cushioning pending data.
The second logical partition 22 places between Flash controller 10 and the first logical partition 21 as cache memory, plays function served as bridge.The first logical partition 21 is put into the second logical partition 22 with pending data, and Flash controller 10 directly reads pending data from the second logical partition 22.If Flash controller 10 directly reads the data of the first logical partition 21, because the first logical partition 21 program speeds are much slower than Flash controller 10, can cause the waste of controller resource, and the speed of cache memory can be mated Flash controller 10, and therefore this mode can promote the processing speed of data effectively.
Concrete, when memory storage 100 write operation, 10 pairs of write orders of Flash controller are resolved, and then data to be written are passed to rapidly the second logical partition 22, by the second logical partition 22 data are write in the first logical partition 21 at last; When memory storage 100 read operation, the first logical partition 21 that obtains the read operation order transfers data to the second logical partition 22, reads fast for Flash controller 10.
Referring to Fig. 3, the invention provides a kind of data storage method again, it realizes that by memory storage as shown in Figure 2 concrete, the method comprises:
Step S301, the memory block 20 of memory storage 100 is divided into the first logical partition 21 and the second logic 22 subregions, and the capacity of the first logical partition 21 is greater than the capacity of the second logical partition 22, and the first logical partition 21 is used for the storage data, and it is as the primary storage space of memory block 20.
Step S302, when flash controller 10 and the first logical partition 21 carried out data transmission, the second logical partition 22 was as the cache memory between flash controller 10 and the first logical partition 21.Concrete implementation is as follows: the flash array of the first logical partition 21 can be simultaneously to the highest significant position among the MLC and least significant bit (LSB) programming, the flash array of the second logical partition 22 can only be programmed to the least significant bit (LSB) among the described MLC, the second logical partition 22 is used as SLC, greatly improve the processing speed of data as Data Buffer Memory.
In sum, the present invention is divided into two logical partitions by the multilevel-cell memory block with memory storage, the first logical partition and the second logical partition, with the first logical partition as the main storage area that is used for the storage data, the second logical partition is as cache memory, when the first logical partition and outside flash controller carried out data transmission, the second logical partition cushioned data, greatly improves whereby data transfer speed.
Certainly; the present invention also can have other various embodiments; in the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (7)
1. memory storage based on the multilayer flash cell, it is characterized in that, comprise flash controller and the memory block that is formed by the multilayer flash cell, described memory block comprises the first logical partition and the second logical partition, described the first logical partition is used for the storage data, when described flash controller and described the first logical partition carried out data transmission, described the second logical partition was made the cache memory between described flash controller and the first logical partition.
2. memory storage according to claim 1 is characterized in that, the capacity of described the first logical partition is greater than the capacity of the second logical partition.
3. memory storage according to claim 1, it is characterized in that, the flash array of described the first logical partition can be simultaneously to the highest significant position in the multilayer flash cell and least significant bit (LSB) programming, and the flash array of described the second logical partition can only be programmed to the least significant bit (LSB) in the described multilayer flash cell.
4. memory storage according to claim 1 is characterized in that, described memory storage is solid state hard disc.
5. one kind is passed through the as claimed in claim 1 storage means of device realization, it is characterized in that described method comprises:
Be the first logical partition and the second logical partition with described memory partitioning, described the first logical partition is used for the storage data;
When described flash controller and described the first logical partition carried out data transmission, described the second logical partition was made the cache memory between described flash controller and the first logical partition.
6. storage means according to claim 5 is characterized in that, the capacity of described the first logical partition is greater than the capacity of the second logical partition.
7. storage means according to claim 5, it is characterized in that, the flash array of described the first logical partition can be simultaneously to the highest significant position in the multilayer flash cell and least significant bit (LSB) programming, and the flash array of described the second logical partition can only be programmed to the least significant bit (LSB) in the described multilayer flash cell.
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| CN201210423934.7A CN102968389B (en) | 2012-10-30 | 2012-10-30 | Based on storing device and the storage means of multi-level flash memory cell |
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| CN201210423934.7A CN102968389B (en) | 2012-10-30 | 2012-10-30 | Based on storing device and the storage means of multi-level flash memory cell |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016095233A1 (en) * | 2014-12-19 | 2016-06-23 | 北京麓柏科技有限公司 | Method and apparatus for realizing non-volatile cache |
| CN106971372A (en) * | 2017-02-24 | 2017-07-21 | 北京大学 | A kind of code-shaped flash memory system and method for realizing image convolution |
| CN107301023A (en) * | 2017-06-29 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of solid-state disk configuration information management method and device |
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| US20090113112A1 (en) * | 2007-10-25 | 2009-04-30 | Ye Kyung-Wook | Data storage device, memory system, and computing system using nonvolatile memory device |
| CN101499315A (en) * | 2008-01-30 | 2009-08-05 | 群联电子股份有限公司 | Average wear method of flash memory and controller thereof |
| CN101556555A (en) * | 2008-04-08 | 2009-10-14 | 群联电子股份有限公司 | Block management method for flash memory, controller and storage system thereof |
| CN101814318A (en) * | 2009-02-25 | 2010-08-25 | 群联电子股份有限公司 | Multi-layer storage unit and non-type flash memory storage system and its controller and access method |
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Patent Citations (4)
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| US20090113112A1 (en) * | 2007-10-25 | 2009-04-30 | Ye Kyung-Wook | Data storage device, memory system, and computing system using nonvolatile memory device |
| CN101499315A (en) * | 2008-01-30 | 2009-08-05 | 群联电子股份有限公司 | Average wear method of flash memory and controller thereof |
| CN101556555A (en) * | 2008-04-08 | 2009-10-14 | 群联电子股份有限公司 | Block management method for flash memory, controller and storage system thereof |
| CN101814318A (en) * | 2009-02-25 | 2010-08-25 | 群联电子股份有限公司 | Multi-layer storage unit and non-type flash memory storage system and its controller and access method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016095233A1 (en) * | 2014-12-19 | 2016-06-23 | 北京麓柏科技有限公司 | Method and apparatus for realizing non-volatile cache |
| CN106971372A (en) * | 2017-02-24 | 2017-07-21 | 北京大学 | A kind of code-shaped flash memory system and method for realizing image convolution |
| CN106971372B (en) * | 2017-02-24 | 2020-01-03 | 北京大学 | Coding type flash memory system and method for realizing image convolution |
| CN107301023A (en) * | 2017-06-29 | 2017-10-27 | 郑州云海信息技术有限公司 | A kind of solid-state disk configuration information management method and device |
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