CN102956452B - Method for manufacturing metal plugs during manufacturing of metal grids - Google Patents
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- CN102956452B CN102956452B CN201110238003.5A CN201110238003A CN102956452B CN 102956452 B CN102956452 B CN 102956452B CN 201110238003 A CN201110238003 A CN 201110238003A CN 102956452 B CN102956452 B CN 102956452B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 224
- 239000002184 metal Substances 0.000 title claims abstract description 224
- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims description 29
- 238000005498 polishing Methods 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 5
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 claims description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910004129 HfSiO Inorganic materials 0.000 claims 1
- 230000000295 complement effect Effects 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 108091006146 Channels Proteins 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for manufacturing metal plugs during manufacturing of metal grids. The method includes firstly, manufacturing a first metal plug which is flush with a substitute grid or lower than a metal grid, connecting the first metal plug to an active area of a CMOS(complementary metal-oxide-semiconductor transistor) device, taking the first metal plug as a CMP(chemical mechanical planarization) stop layer, subjecting a dielectric layer above the substitute grid to CMP to expose the substitute grid, removing the substitute grid, filling metal into the substitute grid to obtain the metal grid; secondly, manufacturing a second metal plug above the first metal plug and forming a metal plug unit by the first metal plug and the second metal plug; thirdly, manufacturing a metal plug unit above the metal grid according to the same process during manufacturing of the second metal plug so as to connect the metal grid to the external. The communication between the metal plug and the active area is guaranteed during manufacturing of the grid by the method in actual application.
Description
Technical field
The present invention relates to the manufacturing technology of semiconductor device, particularly a kind of method making metal closures in making metal gates process.
Background technology
At present, semi-conductor industry is growth of device in wafer (wafer) device side of silicon substrate mainly, such as, and CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device.Generally adopt now two trap CMOS technology simultaneously to make on a silicon substrate p-type NMOS N-channel MOS N field effect transistor (MOSFET) that conducting channel is hole and conducting channel are the N-shaped channel mosfet of electronics, concrete steps are: first, by the zones of different in silicon substrate by doping become respectively with electronics be majority carrier (N-shaped) silicon substrate and with hole be majority carrier (p-type) silicon substrate after, shallow trench isolation is made from (STI) 101 between N-shaped silicon substrate and p-type silicon substrate, then cavity type doped diffusion region (P trap) 102 and electron doping diffusion region (N trap) 103 is formed respectively in the method for STI both sides ion implantation, then make in the wafer device side of P trap 102 and N trap 103 position the stacked grid be made up of gate dielectric layer 104 and metal gate 105 successively respectively, finally in P trap 102 and N trap 103, make source electrode and drain electrode respectively, source electrode and drain electrode are positioned at the both sides (not shown in FIG.) of stacked grid, N-shaped channel mosfet is formed in P trap, p-type channel mosfet is formed in N trap, obtain cmos device structure as shown in Figure 1.
Traditional stacked grid of oxynitrides/polysilicon, be using nitrogen oxide as gate dielectric layer, polysilicon is as grid.Along with the development of semiconductor technology, the cmos device of the stacked grid of oxynitrides/polysilicon, due to leakage current and the problem such as power consumption is excessive, can not meet the needs of small size semiconductor technology.Therefore, propose using high-dielectric coefficient (HK) material as gate dielectric layer, using metal material as the metal gates of metal gate.
Fig. 2 a ~ Fig. 2 d is that prior art is making the generalized section making the embodiment of the method one of metal closures in metal gates process, wherein,
As shown in Figure 2 a, in Semiconductor substrate 11, cmos device structure is formed according to the process described in Fig. 1, this cmos device structure comprises replacement gate 22, source electrode and drain electrode (source electrode and drain not shown), replacement gate 22 also has side wall 55, in this cmos device, also there is barrier layer 66; At barrier layer 66 deposited on silicon first medium layer 77;
Here, barrier layer 66 is titanium layer or titanium nitride layer, generally as etching stop layer;
Here, replacement gate also has metal gates for 22 times and adopts the gate dielectric layer (not shown) of HK material;
As shown in Figure 2 b, adopt chemical-mechanical planarization (CMP) mode to carry out polishing to first medium layer 77, until barrier layer 66 stops, then remove replacement gate;
As shown in Figure 2 c, at this cmos device surface deposition metal level 88, such as tungsten or aluminium lamination, fill replacement gate region, then adopts CMP to be etched to silicon nitride layer 66 and stop;
As shown in Figure 2 d, metal closures 99 is made on this cmos device surface;
When making, being exactly after deposition one deck dielectric layer, adopting photoetching and etching technics after metal closures region makes through hole, adopt metal filled after, form metal closures 99.When making through hole, using barrier layer as etching stop layer;
In above process, in the process described in Fig. 2 b, sunk area is there will be at dielectric layer, when subsequent figure 2c depositing metal layers 88, also sunk area can be deposited to, make in metal closures 99 process at 2d, if metal closures 99 is just in time positioned on sunk area, just cause when making through hole, to the metal level 88 of sunk area be deposited on as etching stop layer, namely etch into sunk area to stop, causing made metal closures 99 cannot connect the active region of this cmos device, cause final this cmos device open circuit made.
In order to overcome this problem, have employed the another kind of method making metal closures in making metal gates process, as shown in Fig. 3 a ~ Fig. 3 c, particularly:
As shown in Figure 3 a, in Semiconductor substrate 11, cmos device structure is formed according to the process described in Fig. 1, this cmos device structure comprises replacement gate 22, source electrode and drain electrode (source electrode and drain not shown), replacement gate 22 also has side wall 55, and this cmos device has barrier layer 66; At barrier layer 66 deposited on silicon first medium layer 77;
Here, barrier layer 66 is titanium layer or titanium nitride layer, generally as etching stop layer;
Here, replacement gate also has metal gates for 22 times and adopts the gate dielectric layer (not shown) of HK material;
As shown in Figure 3 b, first medium layer 77 makes metal closures 99;
In this step, adopt photoetching and etching technics after metal closures region makes through hole, adopt metal filled after, form metal closures 99; When making through hole, using barrier layer as etching stop layer;
As shown in Figure 3 c, CMP mode is adopted to carry out polishing to first medium layer 77, until silicon nitride layer 66 stops, then replacement gate is removed, at this cmos device surface deposition metal level 88, such as tungsten or aluminium lamination, fill replacement gate region, then adopt CMP to be etched to silicon nitride layer 66 and stop.
Due to before employing CMP mode polishing first medium layer 77, make metal closures 99, and this metal closures 99 connects the active region of this cmos device, make so the depression caused when adopting CMP to etch first medium layer 77 can not affect metal closures, solve and adopt the process described in Fig. 2 a ~ Fig. 2 d making in metal gates process the problem making metal closures and produce.
But, process also existing defects described in Fig. 3 a ~ Fig. 3 c, this is because, in employing CMP mode polishing first medium layer, the metal closures needing simultaneously polishing first medium layer and made, and in polishing process, ensure that first medium layer plane and made metal closures plane are equal to, because first medium layer is different with the material of metal closures, the polishing fluid used is also different, so in polishing process, be difficult to ensure that first medium layer plane and made metal closures plane are equal to, so Fig. 3 a ~ Fig. 3 c is just feasible in theory, but cannot realize in practical application.
Summary of the invention
In view of this, the invention provides a kind of method making metal closures in making metal gates process, the method can ensure that the metal closures made by making in gate process is communicated with active area in actual applications.
Technical scheme of the present invention is achieved in that
Making the method making metal closures in metal gates process, the method comprises:
At the cmos device face of Semiconductor substrate deposition first medium layer, described cmos device comprises replacement gate;
Adopt photoetching and etching technics after first medium layer forms the first contact hole, in the first contact hole, fill metal, form the first sub-metal closures, the first sub-metal closures height is not higher than described replacement gate;
Using the first sub-metal closures as polishing stop layer, polishing first medium layer, after removing described replacement gate, adopts the second metal level to fill described replacement gate region;
The second barrier layer and second dielectric layer is deposited successively in the cmos device face of Semiconductor substrate, adopt photoetching and etching technics, with the second barrier layer for etching stop layer, after second dielectric layer forms the second contact hole, the second metal level is filled in the second contact hole, after forming the second sub-metal closures, described first sub-metal closures and the second sub-metal closures form metal closures.
Described second barrier layer is silicon nitride.
Have the gate dielectric layer adopting high dielectric constant material under described replacement gate, described high dielectric constant material is hafnium oxide HfO2, hafnium silicon oxide HfSiO or hafnium silicon oxynitride HfSiNO.
The metal of filling in the first contact hole is tungsten or aluminium, in the first contact hole, fill metal, and form the first sub-metal closures, process is:
After first medium layer deposits the first metal layer, employing chemical-mechanical planarization CMP mode or dry etching mode remove the first metal layer on first medium layer, this the first metal layer is packed into the first contact hole, then dry etching is carried out to the metal level in the first contact hole, etch into not higher than the height of replacement gate, form the first sub-metal closures.
Described second contact hole, directly over described first contact hole, describedly fills the second metal level in the second contact hole, and the process forming the second sub-metal closures is:
In second dielectric layer after depositing second metal layer, adopt CMP mode or dry etching mode, remove the second metal level in second dielectric layer, this second metal level is packed into the second contact hole, forms the second sub-metal closures.
Sulphur hexafluoride SF6 is adopted during described dry etching.
Described employing photoetching and etching technics, with the second barrier layer for etching stop layer, after second dielectric layer forms the second contact hole, fill the second metal level in the second contact hole, while forming the second sub-metal closures, also comprises:
Adopt photoetching and etching technics, with the second barrier layer for etching stop layer, form the metal closures through hole being communicated with metal gates in second dielectric layer, at metal closures filling through hole second metal level of described connection metal gates, form the metal closures of metal gates.
As can be seen from such scheme, method provided by the invention is in making metal gates process, first the first sub-metal closures being more or less than metal gates with replacement gate etc. is made, this the first sub-metal closures is communicated with the active region of cmos device, then using this first sub-metal closures as CMP stop-layer, dielectric layer above CMP replacement gate, after exposed replacement gate, remove replacement gate, adopt metal filled replacement gate, obtain metal gates, belong to side beyond the Great Wall at the first interest again and make the second sub-metal closures, first sub-metal closures and the second sub-metal closures form metal closures, due to make the employing CMP mode in metal gates process with the first sub-metal closures for polishing stop layer polishing first medium layer before, just make the first sub-metal closures being more or less than metal gates with metal gates etc., so when adopting CMP mode polishing first medium layer, just polishing first medium layer, and the first sub-metal closures can not be polished to, so surface polishing can keep level, on the other hand, before employing CMP mode polishing first medium layer, make the first sub-metal closures, and this first sub-metal closures connects the active region of this cmos device and polishing is carried out using this first sub-metal closures as stop-layer, make so adopt CMP can not affect subsequent metal plug to the depression caused during the polishing of first medium layer.And follow-up when side makes the second sub-metal closures to the first interest genus beyond the Great Wall, also can not leave space, in addition, while the sub-metal closures of making second, also above metal gates, make metal closures according to same technological process, for metal gates is communicated to outside.Therefore, method provided by the invention ensures that the metal closures made by making in gate process is communicated with active area in actual applications.
Accompanying drawing explanation
Fig. 1 is the cmos device cross-sectional view of prior art;
Fig. 2 a ~ Fig. 2 d is that prior art is making the generalized section making the embodiment of the method one of metal closures in metal gates process;
Fig. 3 a ~ Fig. 3 c is that prior art is making the generalized section making the embodiment of the method two of metal closures in metal gates process;
Fig. 4 is a kind of method flow diagram making metal closures in making metal gates process provided by the invention;
Fig. 5 a ~ Fig. 5 f is a kind of process generalized section making metal closures in making metal gates process provided by the invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
The present invention also makes metal closures when making metal gates process simultaneously, process is: make the first sub-metal closures being more or less than metal gates with replacement gate etc., this the first sub-metal closures is communicated with the active region of cmos device, then using this first sub-metal closures as CMP stop-layer, dielectric layer above CMP replacement gate, after exposed replacement gate, remove replacement gate, adopt metal filled replacement gate, obtain metal gates, belong to side beyond the Great Wall at the first interest again and make the second sub-metal closures, the first sub-metal closures and the second sub-metal closures form metal closures.
Like this, due to make the employing CMP mode in metal gates process with the first sub-metal closures for polishing stop layer polishing first medium layer before, just make the first sub-metal closures being more or less than metal gates with metal gates etc., so when adopting CMP mode polishing first medium layer, just polishing first medium layer, and the first sub-metal closures can not be polished to, so surface polishing can keep level, on the other hand, before employing CMP mode polishing first medium layer, make the first sub-metal closures, and this first sub-metal closures connects the active region of this cmos device and polishing is carried out using this first sub-metal closures as stop-layer, make so adopt CMP can not affect subsequent metal plug to the depression caused during the polishing of first medium layer.And follow-up when side makes the second sub-metal closures to the first interest genus beyond the Great Wall, also can not leave space.
Therefore, method provided by the invention ensures that the metal closures made by making in gate process is communicated with active area in actual applications.
Fig. 4 is a kind of method flow diagram making metal closures in making metal gates process provided by the invention, provided by the invention a kind of process generalized section making metal closures in making metal gates process shown in composition graphs 5a ~ Fig. 5 f, is described in detail:
Step 401, in Semiconductor substrate 11, form cmos device structure, this cmos device structure comprises replacement gate 22, source electrode and drain electrode (source electrode and drain not shown), replacement gate 22 also has side wall 55, in this cmos device, namely cmos device surface has the first barrier layer 66; First barrier layer 66 deposits first medium layer 77, as shown in Figure 5 a;
In this step, the first barrier layer 66 is titanium nitride or titanium, adopts scheme same as the prior art, repeats no more here;
Here, replacement gate also has metal gates for 22 times and adopts the gate dielectric layer (not shown) of HK material;
Here, replacement gate only can have the gate dielectric layer adopting HK material for 22 times, as the protection of the gate dielectric layer of employing HK material;
Here, HK material is hafnium oxide (HfO2), hafnium silicon oxide (HfSiO) or hafnium silicon oxynitride (HfSiNO);
Here, replacement gate 22 is polysilicon;
Step 402, on first medium layer 77, form contact hole 101, as shown in Figure 5 b;
In this step, contact hole 101, for the sub-metal closures of follow-up making first, adopts photoetching and etching technics will form the region formation contact hole 101 of metal closures;
Step 403, on first medium layer 77, deposit the first metal layer 102 after, employing CMP mode or dry etching mode remove the metal level 102 on first medium layer 77, this metal level 102 is packed into contact hole 101, then dry etching is carried out to the metal level 102 in contact hole 101, etch into not higher than replacement gate 22, form the first sub-metal closures, as shown in Figure 5 c;
In this step, the metal material of the first metal layer 102 of deposition is tungsten or aluminium;
In this step, sulphur hexafluoride (SF6) is adopted when carrying out dry etching;
Step 404, with the first sub-metal closures for polishing stop layer, adopt CMP mode to carry out polishing to first medium layer 77, then remove replacement gate, as fig 5d;
In this step, using the first sub-metal closures as polishing stop layer, carry out CMP, can ensure that final made metal closures does not exist space;
Step 405, at this cmos device surface deposition metal level 88, such as tungsten or aluminium lamination, fill replacement gate region, then adopts CMP to be etched to the first barrier layer 66 and to stop, as depicted in fig. 5e;
Step 406, behind this cmos device surface deposition second barrier layer 103, second barrier layer 103 deposits second dielectric layer 104, then after second dielectric layer 104 forms the second contact hole 105, the second metal level 106 is filled in the second contact hole 105, form the second sub-metal closures, first sub-metal closures and the second sub-metal closures constitute metal closures, as shown in figure 5f;
In this step, the second contact hole 105 formed is above contact hole 101, and when formation the second contact hole 105, adopt photoetching and etching technics, the second barrier layer 103 is as etching stop layer;
The process of filling the second metal level 106 at the second contact hole 105 is: depositing second metal layer 106 in second dielectric layer 104, then adopts CMP to be only polished to the second barrier layer 103;
In this step, the second barrier layer 103 is silicon nitride layer etc., exists as etching stop layer.
In the process described in Fig. 4, in a step 406, also comprise the metal closures process made above metal gates, this metal closures can make metal gates be communicated to semiconductor device outside, and process is:
Adopt photoetching and etching technics, with the second barrier layer for etching stop layer, form the metal closures through hole being communicated with metal gates in second dielectric layer, at metal closures filling through hole second metal level of described connection metal gates, form the metal closures of metal gates.This process is shown in Fig. 5 f.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (7)
1. making the method making metal closures in metal gates process, the method comprises:
At the cmos device face of Semiconductor substrate deposition first medium layer, described cmos device comprises replacement gate;
Adopt photoetching and etching technics after first medium layer forms the first contact hole, in the first contact hole, fill metal, form the first sub-metal closures, the first sub-metal closures height is not higher than described replacement gate;
Using the first sub-metal closures as polishing stop layer, polishing first medium layer, after removing described replacement gate, adopts the second metal level to fill described replacement gate region;
The second barrier layer and second dielectric layer is deposited successively in the cmos device face of Semiconductor substrate, adopt photoetching and etching technics, with the second barrier layer for etching stop layer, after second dielectric layer forms the second contact hole, the second metal level is filled in the second contact hole, after forming the second sub-metal closures, described first sub-metal closures and the second sub-metal closures form metal closures.
2. the method for claim 1, is characterized in that, described second barrier layer is silicon nitride.
3. the method for claim 1, is characterized in that, have the gate dielectric layer adopting high dielectric constant material under described replacement gate, described high dielectric constant material is hafnium oxide HfO2, hafnium silicon oxide HfSiO or hafnium silicon oxynitride HfSiNO.
4. the method for claim 1, is characterized in that, the metal of filling in the first contact hole is tungsten or aluminium, in the first contact hole, fill metal, and form the first sub-metal closures, process is:
After first medium layer deposits the first metal layer, employing chemical-mechanical planarization CMP mode or dry etching mode remove the first metal layer on first medium layer, this the first metal layer is packed into the first contact hole, then dry etching is carried out to the metal level in the first contact hole, etch into not higher than the height of replacement gate, form the first sub-metal closures.
5. the method for claim 1, is characterized in that, described second contact hole, directly over described first contact hole, describedly fills the second metal level in the second contact hole, and the process forming the second sub-metal closures is:
In second dielectric layer after depositing second metal layer, adopt CMP mode or dry etching mode, remove the second metal level in second dielectric layer, this second metal level is packed into the second contact hole, forms the second sub-metal closures.
6. the method as described in claim 4 or 5, is characterized in that, adopts sulphur hexafluoride SF6 during described dry etching.
7. the method for claim 1, is characterized in that, described employing photoetching and etching technics, with the second barrier layer for etching stop layer, after second dielectric layer forms the second contact hole, in the second contact hole, fill the second metal level, while forming the second sub-metal closures, also comprise:
Adopt photoetching and etching technics, with the second barrier layer for etching stop layer, form the metal closures through hole being communicated with metal gates in second dielectric layer, at metal closures filling through hole second metal level of described connection metal gates, form the metal closures of metal gates.
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