CN102955308B - Array substrate for display device and method of fabricating the same - Google Patents

Abstract

Disclosed are an array substrate for a display device and a manufacturing method thereof. The device includes: a substrate; gate lines, the gate lines are formed on the substrate along a first direction; data lines, the data lines are formed above the substrate along a second direction, wherein the data lines and The gate lines intersect each other to define a pixel area; a thin film transistor formed in the pixel area and having a drain, a gate connected to the gate line, and a source connected to the data line a pixel electrode formed in the pixel region and connected to the drain; a first auxiliary gate pattern formed above the gate line and connected to the drain The gate line is contacted, and a first auxiliary data pattern is formed above and in contact with the data line.

Description

Array substrate for display device and manufacturing method thereof

This application claims priority to Korean Patent Application No. 10-2011-0082808 filed on August 19, 2011 and Korean Patent Application No. 10-2012-0067842 filed on June 25, 2012 for all purposes , said patent application is incorporated herein by reference as if said patent application were set forth herein in its entirety.

technical field

The present disclosure relates to an array substrate for a display device, in particular to an array substrate for a display device including thin film transistors, and a method for manufacturing the array substrate.

Background technique

With the rapid development of information technology, various display devices for displaying images are required. Flat panel display (FPD) devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and organic light emitting diode (OLED) devices have been proposed.

Among the FPD devices, LCD devices are widely used due to advantages of small size, light weight, thin profile, and low power consumption.

Active matrix type display devices including pixels arranged in a matrix and switching elements for controlling on/off of the respective pixels have been widely used. An active matrix display device includes an array substrate on which gate lines, data lines, switching elements, and pixel electrodes are formed. The array substrate will be described below with reference to the accompanying drawings.

FIG. 1 is a plan view illustrating an array substrate for a display device according to the related art.

In FIG. 1 , gate lines 22 and data lines 52 cross each other to define a pixel region P. Referring to FIG. The thin film transistor T is connected to the gate line 22 and the data line 52 .

The thin film transistor T includes a gate 24 , an active layer 42 , a source 54 and a drain 56 . The gate 24 is connected to the gate line 22 , the source 54 is connected to the data line 52 , and the drain 56 is separated from the source 54 . The active layer 42 is exposed between the source electrode 54 and the drain electrode 56 , and the exposed portion of the active layer 42 becomes a channel of the thin film transistor T. Referring to FIG.

The pixel electrode 72 is formed in the pixel region P and connected to the drain 56 of the thin film transistor T through the drain contact hole 62 .

A cross-sectional structure of an array substrate for a display device according to the related art will be described with reference to FIG. 2 .

FIG. 2 is a cross-sectional view illustrating an array substrate for a display device according to the related art, and FIG. 2 corresponds to a cross-section taken along line II-II of FIG. 1 .

In FIG. 2 , a gate line 22 and a gate 24 connected to the gate line 22 are formed on a substrate 10 , and a gate insulating layer 30 is formed on the gate line 22 and the gate 24 .

An active layer 42 of intrinsic silicon is formed on the gate insulating layer 30 and above the gate 24 , and an ohmic contact layer 44 doped with silicon is formed on the active layer 42 .

A data line 52 , a source electrode 54 and a drain electrode 56 are formed on the ohmic contact layer 44 . A passivation layer 60 is formed on the data line 52 , the source electrode 54 and the drain electrode 56 . The passivation layer 60 includes a drain contact hole 62 exposing the drain electrode 56 .

A pixel electrode 72 is formed on the passivation layer 60 , and the pixel electrode 72 is connected to the drain electrode 56 through the drain contact hole 62 .

Recently, since a display device is required to have a large size and high definition, the length of signal lines such as the gate line 22 and the data line 52 has become longer. Then, the resistance of the signal line increases, causing signal delay. In addition, as the driving speed increases, the load applied to the signal line increases. Various attempts have been made to solve these problems.

For example, the resistance of a signal line can be reduced by widening the width of the signal line. In this case, since the area of the pixel region is reduced, the aperture ratio is reduced and the luminance is reduced. Here, brightness can be improved by increasing the amount of supplied light. However, this increases power consumption and reduces luminous efficiency.

Alternatively, the resistance of the signal line can be reduced by thickening the thickness of the signal line. However, the signal line is formed by depositing a metal material to form a metal layer and selectively patterning the metal layer. Therefore, in order to thicken the thickness of the signal line, the thickness of the metal layer should be thickened, and thus the amount of metal material used for deposition also increases. In addition, the amount of etchant used to pattern the metal layer also increases. Therefore, the manufacturing cost of the array substrate increases.

Meanwhile, some metallic materials have poor properties in contact with the substrate, and when formed thickly, may be broken or peeled off from the substrate. Therefore, there is a limit to the increase in the thickness of the signal line.

Contents of the invention

Accordingly, the present invention is directed to an array substrate for a display device and a method of manufacturing the array substrate that substantially obviate one or more of the problems due to limitations and disadvantages of the related art .

An advantage of the present invention is to provide an array substrate for a display device and a manufacturing method of the array substrate capable of reducing signal line resistance.

Another advantage of the present invention is to provide an array substrate for a display device capable of improving aperture ratio and brightness and a method for manufacturing the array substrate.

Additional features and advantages of the invention will be set forth in the description which follows, and some of them will be obvious from the description, or can be learned by practice of the invention. These and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description, claims hereof as well as the appended drawings.

To achieve these and other advantages, according to the purpose of the embodiments of the present invention, as specifically and generally described herein, an array substrate for a display device includes: a substrate; formed on the substrate; a data line, the data line is formed above the substrate along a second direction, wherein the data line and the gate line cross each other to define a pixel area; a thin film transistor, the thin film transistor Formed in the pixel area, and has a drain, a gate connected to the gate line, and a source connected to the data line; a pixel electrode, the pixel electrode is formed in the pixel area, and is connected with the the drain connection; a first auxiliary gate pattern formed over and in contact with the gate line; and a first auxiliary data pattern, the first auxiliary data pattern Patterns are formed over and in contact with the data lines.

In addition, the above array substrate for a display device may further include: a gate insulating layer covering the gate line and the gate electrode, and under the data line; a passivation layer, the passivation layer a passivation layer is formed on the data line and the gate insulating layer; a first contact hole is formed in the passivation layer and the gate insulating layer, and is exposed along the first direction the gate line; and a second contact hole formed in the passivation layer and exposing the data line along the second direction, wherein the first auxiliary gate pattern may be formed in the first contact hole; and the first auxiliary data pattern may be formed in the second contact hole.

In addition, the above array substrate for a display device may further include: a drain contact pattern, wherein the passivation layer may be further formed on the drain and include a drain contact hole, and the drain contact pattern may be formed on The drain contact hole is in and contacts the drain, and the pixel electrode may cover and contact the drain contact pattern.

In addition, the above array substrate for a display device may further include: a second auxiliary gate pattern formed on the first auxiliary gate pattern to cover, contact and protect the first auxiliary gate pattern. an auxiliary gate pattern; and a second auxiliary data pattern formed on the first auxiliary data pattern to cover, contact and protect the first auxiliary data pattern.

In addition, in the above array substrate for a display device, the second auxiliary gate pattern and the second auxiliary data pattern may be formed of the same material as that of the pixel electrode.

In addition, in the above array substrate for a display device, the first auxiliary gate pattern and the first auxiliary data pattern may be formed by plating.

In addition, in the above array substrate for a display device, the drain contact pattern, the first auxiliary gate pattern and the first auxiliary data pattern may be formed by a plating method.

In addition, in the above array substrate for a display device, the first auxiliary gate pattern and the first auxiliary data pattern may be formed of copper, chrome or nickel.

In addition, in the above array substrate for a display device, the drain contact pattern, the first auxiliary gate pattern, and the first auxiliary data pattern may be formed of copper, chromium, or nickel.

In addition, in the above array substrate for a display device, the first auxiliary data pattern may be integrally formed along the data line.

In addition, the above array substrate for a display device may further include: a common line formed between adjacent gate lines and parallel to the gate lines, wherein the gate insulating layer may further cover the a common line; a capacitive electrode formed above the common line, the capacitive electrodes and the common line overlapping each other are insulated from the gate between the capacitive electrodes and the common line layers together form a storage capacitor; and a capacitive contact pattern, wherein the passivation layer may be further formed on the capacitive electrode, and the passivation layer includes a capacitive contact hole, and the capacitive contact pattern may be formed on the capacitive contact holes and contact the capacitive electrodes, and the pixel electrodes may cover and contact the capacitive contact patterns.

In addition, in the above array substrate for a display device, the drain contact pattern, the first auxiliary gate pattern, the first auxiliary data pattern, and the capacitance contact pattern may be formed by a plating method.

In addition, in the above array substrate for a display device, the drain contact pattern, the first auxiliary gate pattern, the first auxiliary data pattern, and the capacitance contact pattern may be formed of copper, chromium, or nickel.

In addition, in the above array substrate for a display device, each of the first auxiliary gate pattern and the first auxiliary data pattern may include a first plating layer formed of copper and A second plating layer formed of nickel on the surface, and the second plating layer is thinner than the first plating layer.

In another aspect, a method of manufacturing an array substrate for a display device includes the steps of: forming a gate line on the substrate along a first direction, and forming a gate on the substrate, wherein the gate is formed from the extending the gate line; forming a gate insulating layer covering the gate line and the gate; forming an active layer above the gate on the gate insulating layer, and forming an ohmic contact layer on the active layer; A data line is formed on the gate insulating layer along a second direction, and a source electrode and a drain electrode are formed on the ohmic contact layer, wherein the data line and the gate line cross each other to define a pixel area, the source A pole extends from the data line, and the drain and the source are separated above the gate; a first auxiliary gate pattern is formed to contact the gate line, and a first auxiliary data pattern is formed contacting the data line; and forming a pixel electrode in the pixel area, the pixel electrode being connected to the drain.

In addition, the above method may further include the steps of: forming a passivation layer on the data line, the source electrode, and the drain electrode; and forming a first contact hole in the passivation layer and the gate insulating layer to expose the gate line, and form a second contact hole in the passivation layer to expose the data line, wherein the first auxiliary gate pattern may be formed in the first contact hole, and the A first auxiliary data pattern may be formed in the second contact hole.

In addition, the above method may further include the steps of: forming a drain contact hole in the passivation layer to expose the drain electrode; and forming a drain contact pattern in the drain contact hole to contact the drain electrode. pole.

In addition, in the step of forming the pixel electrode, a second auxiliary gate pattern may be formed on the first auxiliary gate pattern to cover and contact the first auxiliary gate pattern, and may be formed on the first auxiliary data pattern. A second auxiliary data pattern is formed to cover and contact the first auxiliary data pattern.

Also, in the above method, the second auxiliary gate pattern and the second auxiliary data pattern may be formed of the same material as that of the pixel electrode.

In addition, in the step of forming the gate lines, a common line may be formed between adjacent gate lines and parallel to the gate lines; in the step of forming the gate insulating layer, the gate insulating layer may further cover the common line; in the step of forming the active layer, a capacitive electrode may be formed above the common line, and the capacitive electrode and the common line overlapping each other may be connected with the capacitive electrode and the common line The gate insulating layer between them together forms a storage capacitor; in the step of forming a drain contact hole, a capacitor contact hole may be formed in the passivation layer to expose the capacitor electrode; when forming the first auxiliary gate In the step of patterning, a capacitive contact pattern may be formed in the capacitive contact hole to contact the capacitive electrode; and in the step of forming a pixel electrode, the pixel electrode may further cover and contact the capacitive contact pattern.

In addition, in the above method, the first auxiliary gate pattern and the first auxiliary data pattern may be formed by a plating method.

In addition, in the above method, the drain contact pattern, the first auxiliary gate pattern, and the first auxiliary data pattern may be formed by a plating method.

In addition, in the above method, the capacitance contact pattern, the drain contact pattern, the first auxiliary gate pattern, and the first auxiliary data pattern may be formed by a plating method.

Also, in the above method, the first auxiliary gate pattern and the first auxiliary data pattern may be formed of copper, chrome, or nickel.

Also, in the above method, the drain contact pattern, the first auxiliary gate pattern, and the first auxiliary data pattern may be formed of copper, chromium, or nickel.

Also, in the above method, the capacitance contact pattern, the drain contact pattern, the first auxiliary gate pattern, and the first auxiliary data pattern may be formed of copper, chrome, or nickel.

Also, in the above method, the first auxiliary data pattern may be integrally formed along the data line.

In addition, in the above method, forming the first auxiliary gate pattern and the first auxiliary data pattern may include forming a first plating layer formed of copper and forming a first plating layer formed of nickel on the first plating layer. Two plating layers, and wherein the second plating layer is thinner than the first plating layer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the invention and together with the description serve to explain the principles of the invention.

In the attached picture:

1 is a plan view illustrating an array substrate for a display device according to the prior art;

2 is a cross-sectional view showing an array substrate for a display device according to the prior art, and FIG. 2 corresponds to a cross-section taken along line II-II of FIG. 1;

3 is a plan view illustrating an array substrate for a display device according to an exemplary embodiment of the present invention;

Fig. 4 is a sectional view taken along line IV-IV of Fig. 3;

5A to 5D are plan views illustrating an array substrate in various steps of a method of manufacturing an array substrate according to an exemplary embodiment of the present invention;

6A to 6F are cross-sectional views showing the array substrate in various steps of a method for manufacturing an array substrate according to an exemplary embodiment of the present invention, and FIGS. 6A to 6F correspond to sections taken along line VI-VI of FIGS. 5A to 5D cross section;

Figure 7 is a flow chart representing the process of electroless plating (electroless plating) method according to the present invention;

8 is a cross-sectional view illustrating another array substrate for a display device according to an exemplary embodiment of the present invention;

9 is a plan view showing an array substrate for a display device according to another embodiment of the present invention; and

FIG. 10 is a sectional view taken along line IX-IX of FIG. 9 .

Detailed ways

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings.

FIG. 3 is a plan view illustrating an array substrate for a display device according to an exemplary embodiment of the present invention. FIG. 4 is a sectional view taken along line IV-IV of FIG. 3 .

In FIGS. 3 and 4 , gate lines 122 and gates 124 of conductive material are formed on a transparent insulating substrate 110 . The gate lines 122 are formed along a first direction, and the gate electrodes 124 extend from the gate lines 122 . A common line 126 is formed between adjacent gate lines 122 and is parallel to the gate lines 122 .

A gate insulating layer 130 of silicon nitride or silicon oxide is formed on the gate line 122 , the gate 124 and the common line 126 , and the gate insulating layer 130 covers the gate line 122 , the gate 124 and the common line 126 .

An active layer 142 of intrinsic amorphous silicon is formed on the gate insulating layer 130 and above the gate 124 . An ohmic contact layer 144 doped with amorphous silicon is formed on the active layer 142 .

A data line 152 of conductive material such as metal, a source electrode 154 and a drain electrode 156 are formed on the ohmic contact layer 144 . The data line 152 is formed in a second direction perpendicular to the first direction, and the data line 152 crosses the gate line 122 and the common line 126 . The data line 152 defines a pixel region P together with the gate line 122 . The source electrode 154 extends from the data line 152 , and the drain electrode 156 and the source electrode 154 are spaced apart above the gate electrode 124 . A capacitive electrode 158 is formed on the gate insulating layer 130 over the common line 126 and is formed of the same material as that of the data line 152 , the source 154 and the drain 156 . Here, an intrinsic silicon pattern and a doped silicon pattern are formed under each of the data line 152 and the capacitance electrode 158 .

The source 154 and the drain 156 , the active layer 142 and the gate 124 form a thin film transistor T, and the active layer 142 exposed between the source 154 and the drain 156 becomes a channel of the thin film transistor T. The capacitive electrode 158 and the common line 126 overlapping each other form a storage capacitor together with the gate insulating layer 130 as a dielectric therebetween.

A passivation layer 160 is formed on the data line 152 , the source electrode 154 and the drain electrode 156 and the capacitor electrode 158 . The passivation layer 160 is formed of an inorganic insulating material such as silicon nitride and silicon oxide or an organic insulating material such as acrylic resin. The passivation layer 160 includes a drain contact hole 162 exposing the drain electrode 156 and a capacitor contact hole 164 exposing the capacitor electrode 158 . The passivation layer 160 further includes a first contact hole 166 exposing the gate line 122 in a first direction together with the gate insulating layer 130 , and the passivation layer 160 further includes a second contact hole 168 exposing the data line 152 in a second direction.

A drain contact pattern 172 is formed in the drain contact hole 162 and contacts the drain electrode 156 . Capacitive contact patterns 174 are formed in the capacitive contact holes 164 and contact the capacitive electrodes 158 . A first auxiliary gate pattern 176 is formed in the first contact hole 166 and contacts the gate line 122 . A first auxiliary data pattern 178 is formed in the second contact hole 168 and contacts the data line 152 .

The drain contact pattern 172, the capacitor contact pattern 174, the first auxiliary gate pattern 176, and the first auxiliary data pattern 178 are formed by a plating method, and fill the contact holes 162, 164, 166, and 168, respectively. The drain contact pattern 172 , the capacitor contact pattern 174 , the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 may have the same height as the passivation layer 160 or may be higher than the passivation layer 160 . The drain contact pattern 172, the capacitor contact pattern 174, the first auxiliary gate pattern 176, and the first auxiliary data pattern 178 may have the same thickness, and thus the drain contact pattern 172, the capacitor contact pattern 174, and the first auxiliary data pattern 178 may have the same thickness. The passivation layer 160 may be higher than the first auxiliary gate pattern 176 .

A pixel electrode 182 of a transparent conductive material is formed on the passivation layer 160 in the pixel region P. Referring to FIG. The pixel electrode 182 covers and contacts the drain contact pattern 172 and the capacitor contact pattern 174 , and the pixel electrode 182 is electrically connected to the drain electrode 156 and the capacitor electrode 158 . In addition, a second auxiliary gate pattern 184 and a second auxiliary data pattern 186 are respectively formed on the first auxiliary gate pattern 176 and the first auxiliary data pattern 178, and the second auxiliary gate pattern 184 and the second auxiliary data pattern 186 It is formed of the same material as the pixel electrode 182 . The second auxiliary gate pattern 184 and the second auxiliary data pattern 186 cover, contact and protect the first auxiliary gate pattern 176 and the first auxiliary data pattern 178, respectively.

In an embodiment of the present invention, when the drain contact hole 162 and the capacitance contact hole 164 are formed, the first contact hole 166 and the second contact hole 168 respectively exposing the gate line 122 and the data line 152 are formed, and A first auxiliary gate pattern 176 and a first auxiliary data pattern 178 are respectively formed in the first contact hole 166 and the second contact hole 168 . Thus, the resistance of the gate line 122 and the data line 152 can be reduced. Therefore, signal delay can be prevented, and the load can be reduced. In addition, the widths of the gate lines 122 and the data lines 152 can be reduced, and an aperture ratio and brightness can be improved.

A method of manufacturing an array substrate will be described in detail with reference to FIGS. 5A to 5D , 6A to 6F , 3 and 4 . 5A to 5D are plan views illustrating an array substrate in various steps of a method of manufacturing an array substrate according to an exemplary embodiment of the present invention. 6A to 6F are cross-sectional views showing the array substrate in various steps of a method for manufacturing an array substrate according to an exemplary embodiment of the present invention, and FIGS. 6A to 6F correspond to sections taken along line VI-VI of FIGS. 5A to 5D section.

In FIGS. 5A and 6A , by depositing a conductive material such as metal by using a sputtering method and patterning the conductive material by a photolithography process using a photomask, the conductive material such as glass or plastic Gate lines 122 , gate electrodes 124 and common lines 126 are formed on the transparent insulating substrate 110 . The gate lines 122 are formed along a first direction, and the common line 126 is disposed between adjacent gate lines 122 and parallel to the gate lines 122 . The gate 124 extends from the gate line 122 .

The gate line 122, the gate electrode 124, and the common line may be formed of aluminum, molybdenum, nickel, chromium, copper, or alloys thereof. Here, since copper has relatively low resistivity, using copper can more effectively reduce the resistance of the wire and prevent signal delay. When copper is used, a buffer layer may be formed under the copper layer to improve the surface properties with the substrate 110 . The buffer layer 110 may be formed of molybdenum, titanium, tantalum or alloys thereof.

In FIG. 5B and FIG. 6B to FIG. 6D, a gate insulating layer 130 is formed on the gate line 122, the gate 124 and the common line 126, and then an active layer 130 is formed on the gate insulating layer 130 through a photolithography process using a photomask. layer 142 , ohmic contact layer 144 , data line 152 , source 154 , drain 156 and capacitor electrode 158 .

This will be described in more detail below.

In FIG. 6B , a gate insulating layer 130 , an intrinsic silicon layer 140 , a doped silicon layer 141 and a metal layer 150 are sequentially formed on the gate line 122 , the gate electrode 124 and the common line 126 . Here, the gate insulating layer 130, the intrinsic silicon layer 140, and the doped silicon layer 141 may be formed by a chemical vapor deposition (CVD) method. The metal layer 150 may be formed by a physical vapor deposition (PVD) method such as sputtering. The gate insulating layer 130 may be formed of silicon nitride (SiNx) or silicon oxide (SiO ₂ ). The intrinsic silicon layer 140 may be formed of intrinsic amorphous silicon, and the doped silicon layer 141 may be formed of boron-doped or phosphorus-doped amorphous silicon. The metal layer 150 may be formed of aluminum, molybdenum, nickel, chromium, copper or alloys thereof. Here, since copper has relatively low resistivity, using copper can more effectively reduce the resistance of the wire and prevent signal delay. When copper is used, a buffer layer may be formed under the copper layer to improve the surface properties with the substrate 110 . The buffer layer 110 may be formed of molybdenum, titanium, tantalum or alloys thereof.

A photoresist layer (not shown) is formed on the metal layer 150 , and a mask M is disposed over the photoresist layer. The mask M includes a light blocking portion BA for blocking light, a light transmitting portion TA for transmitting light, and a semi-transmitting light portion HTA for partially transmitting light. The semi-transmissive light part HTA may include a semi-transparent layer or a plurality of slits.

Next, light such as ultraviolet rays is irradiated through the mask M to the photoresist layer, and the photoresist layer is exposed. The exposed photoresist layer is developed to form a first photoresist pattern 192 and a second photoresist pattern 194 . The first photoresist pattern 192 corresponds to the light shielding portion BA of the mask M, and has a first thickness. The second photoresist pattern 194 corresponds to the semi-transmission light part HTA, and has a second thickness thinner than the first thickness. The second photoresist pattern 194 is disposed over the gate 124 , and the first photoresist pattern is disposed on both sides of the second photoresist pattern 194 and over the common line 126 .

In FIG. 6C, the metal layer 150 of FIG. 6B, the doped silicon layer 141 of FIG. 6B are sequentially etched by using the first photoresist pattern 192 and the second photoresist pattern 194 of FIG. And the intrinsic silicon layer 140 of FIG. 6B , thereby forming the data line 152 , the source-drain pattern 150 a , the doped semiconductor pattern 141 a , the active layer 142 and the capacitor electrode 158 . Here, the metal layer 150 in FIG. 6B may be wet-etched by an etchant, and the doped silicon layer 141 in FIG. 6B and the intrinsic silicon layer 140 in FIG. 6B may be dry-etched by an etching gas.

The data line 152 is formed along a second direction perpendicular to the first direction, and crosses the gate line 122 and the common line 126 . The data line 152 and the gate line 122 define the pixel area P. The source-drain pattern 150 a is connected to the data line 152 . The active layer 142, the doped semiconductor pattern 141a and the source-drain pattern 150a are sequentially disposed over the gate. The capacitor electrode 158 is disposed above the common line 126 and overlaps the common line 126 . Here, an intrinsic silicon pattern and a doped silicon pattern are formed under each of the data line 152 and the capacitance electrode 158 .

Then, the second photoresist pattern 194 of FIG. 6B is removed through an ashing process, thereby exposing the source-drain pattern 150 a above the gate 124 . At this time, the first photoresist pattern 192 is partially removed, and the thickness of the first photoresist pattern 192 is reduced.

In FIG. 6D, the source-drain pattern 150a of FIG. 6C and the doped semiconductor pattern 141a of FIG. 6C are etched by using the first photoresist pattern 192 of FIG. 6C as an etching mask, thereby forming the source electrode 154 and The drain electrode 156 and the ohmic contact layer 144 expose the active layer 142 . The source electrode 154 is connected to the data line 152 , and the drain electrode 156 faces the source electrode 154 and is spaced apart from the source electrode 154 with respect to the gate electrode 124 .

Next, the first photoresist pattern 192 is removed.

Here, the active layer 142 is formed through the same photolithography process as that for forming the data line 152 , the source electrode 154 and the drain electrode 156 . The active layer 142 may also be formed through a photolithography process different from the photolithography process for forming the data line 152 , the source electrode 154 and the drain electrode 156 .

Then, in FIGS. 5C and 6E , the passivation layer 160 is formed by depositing an inorganic insulating material such as silicon nitride or silicon oxide, and the passivation layer 160 is patterned by a photolithography process using a photomask, thereby A drain contact hole 162, a capacitor contact hole 164, a first contact hole 166, and a second contact hole 168 are formed. At this time, the gate insulating layer 130 corresponding to the first contact hole 166 is also selectively removed. The drain contact hole 162 exposes the drain electrode 156 , and the capacitor contact hole 164 exposes the capacitor electrode 158 . The first contact hole 166 exposes the gate line 122 between adjacent data lines 152 , and the second contact hole 168 exposes the data line 152 between adjacent gate lines 122 .

Meanwhile, the passivation layer 160 may be formed of an organic insulating material such as acrylic resin, and in this case, the passivation layer 160 has a flat top surface.

In FIG. 5D and FIG. 6F, the drain contact pattern 172, the capacitor contact pattern 174, the second contact hole 168 are respectively formed in the drain contact hole 162, the capacitor contact hole 164, the first contact hole 166 and the second contact hole 168 by plating. An auxiliary gate pattern 176 and a first auxiliary data pattern 178 . Here, the drain contact pattern 172, the capacitance contact pattern 174, the first auxiliary gate pattern 176, and the first auxiliary data pattern 178 may have a thickness of about 0.2 micrometers to about 5 micrometers. Beneficially, the drain contact pattern 172, the capacitive contact pattern 174, the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 may have a thickness of about 2 microns to about 3 microns to reduce the resistance of the line and prevent the The alignment problem of the liquid crystal molecules caused by the steps. The drain contact pattern 172, the capacitor contact pattern 174, the first auxiliary gate pattern 176, and the first auxiliary data pattern 178 may fill the drain contact hole 162, the capacitor contact hole 164, the first contact hole 166, and the second contact hole 168, respectively. , and may be higher than the passivation layer 160 .

The drain contact pattern 172, the capacitor contact pattern 174, the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 may be formed of a conductive material such as copper, chrome or nickel. Beneficially, the drain contact pattern 172, the capacitor contact pattern 174, the first auxiliary gate pattern 176, and the first auxiliary data pattern 178 may be formed of copper to further reduce the resistance of the lines.

In this embodiment of the present invention, the second contact hole 168 may be formed over the data line 152 between adjacent gate lines 122 . The second contact hole 168 may be formed over the data line 152 crossing the gate line 122 and may extend to the next pixel region P. Referring to FIG. Adjacent second contact holes 168 may be connected to each other. Therefore, the first auxiliary data pattern 178 in the second contact hole 168 may be integrally formed along the data line 152 to further reduce the resistance of the line. In other words, all of the first auxiliary data patterns may be continuously formed along the data lines.

The drain contact hole 172, the capacitive contact pattern 174, the first auxiliary gate pattern 176, and the first auxiliary data pattern 178 may be formed through an electroless plating method, which will be described later.

Next, in FIGS. 3 and 4 , a transparent conductive material is deposited, and the transparent conductive material is patterned by a photolithography process using a photomask, thereby forming the pixel electrode 182, the second auxiliary gate pattern 184 and The second auxiliary data pattern 186 . The pixel electrode 182 is disposed on the passivation layer 160 in the pixel region P. As shown in FIG. The pixel electrode 182 contacts and covers the drain contact pattern 172 and the capacitor contact pattern 174 , and the pixel electrode 182 is electrically connected to the drain electrode 156 and the capacitor electrode 158 . The second auxiliary gate pattern 184 contacts and covers the first auxiliary gate pattern 176 , and the second auxiliary data pattern 186 contacts and covers the first auxiliary data pattern 178 . The transparent conductive material may be indium tin oxide or indium zinc oxide.

The second auxiliary gate pattern 184 and the second auxiliary data pattern 186 prevent oxidation of the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 and protect the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 .

The electroless plating method according to the present invention will be described with reference to FIG. 7 . Fig. 7 is a flowchart showing the electroless plating process according to the present invention. The copper plating method will be explained as an example.

In FIG. 7, in the first step ST1, in order to increase the adhesion between the base layer and the plating layer, a cleaning process is performed to remove particles or organic substances, thereby cleaning the surface of the base layer. At this time, the substrate including the base layer thereon, which may include copper, may be exposed to the organic solution for about 30 seconds.

Then, in the second step ST2, a conditioning process is performed to remove the oxide film on the base layer. The surface of the base layer has polarity, for example, positive (+) polarity. At this time, the substrate including the base layer thereon may be exposed to a solution including sulfuric acid (H ₂ SO ₄ ) for about 30 seconds. Here, the second step ST2 may be omitted.

Next, in the third step ST3, an activating process is performed to adsorb palladium (Pd) to the surface of the base layer. Palladium acts as a catalyst. The substrate including the base layer thereon may be exposed to an acid solution having palladium ions dissolved therein for about 60 seconds. The copper in the base layer loses electrons due to the catalytic performance of substitution-type palladium ions and becomes ions. Palladium ions are reduced and adsorbed to the surface of the base layer. Here, the acid solution may be a sulfuric acid (H ₂ SO ₄ ) based solution.

In the fourth step ST4, an electroless plating process is performed to form a copper plating layer on the base layer. At this time, a copper plating solution is used. The copper plating solution includes metal salt, reducing agent, complexant (complexant), stabilizer and accelerator (exaltant) (or accelerator), and the copper plating solution is alkaline (alkali).

The reducing agent donates electrons to the copper ions. The potential of the reducing agent may be lower than the equilibrium potential of copper ions. The reducing agent may include one of formaldehyde, dimethylamineborane (DMAD), and sodium hypophosphite. For example, when formaldehyde is used as a reducing agent, hydrogen ions (H+) and hydroxide ions (OH-) may be generated due to the reduction process of formaldehyde, and the pH of the plating solution may be changed.

The complexing agent combines with the copper ions to prevent the reaction and precipitation of the copper ions with the reducing agent. The complexing agent may include one of sodium potassium tartrate (sodium potassium tartrate), ethylenediaminetetraacetic acid (EDTA), glycolic acid (glycolic acid) and triethanolamine (triethanol amine), and the sodium potassium tartrate may be called For Rochelle (Rochelle) salt.

The stabilizer adsorbs onto dust or copper particles, preventing copper ions from coming into contact with the reducing agent. The stabilizer may include one of oxygen, thiourea, 2-mercaptobenzothiazole, diethyldithiocarbamate, and vanadium pentoxide.

Accelerators (or accelerators) are used to increase plating speed. The accelerator may contain one of cyanide, proprionitrile, and O-phenanthroline.

Therefore, when the substrate including the palladium-adsorbed base layer is exposed to a copper plating solution, electrons are generated due to a reduction process of a reducing agent, and copper ions are combined with the electrons and educed on a palladium catalyst, thereby forming a copper plating layer. In addition, the plated copper acts as an autocatalyst and further forms a copper plating layer.

Here, the thickness of the copper plating layer varies according to the composition, composition ratio, and exposure time of the copper plating solution. For example, when the substrate layer is exposed to a copper plating solution comprising formaldehyde, Rochelle salt, and 2-mercaptobenzothiazole for about 1200 seconds, a copper plating layer of about 1.5 microns may be formed.

In this embodiment of the present invention, the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 are formed by an electroless plating method. The first auxiliary gate pattern 176 and the first auxiliary data pattern 178 may also be formed by an electro plating method. More particularly, in order to avoid static electricity during the manufacture of the array substrate and to check electrical conditions after the manufacture of the array substrate, shorting bars connecting gate lines and data lines are formed. The first auxiliary gate pattern 176 and the first auxiliary data pattern 178 may be formed by an electroplating method using a short bar.

In this embodiment of the present invention, the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 are respectively formed on the gate line 122 and the data line 152 by a plating method. The resistance of the gate line 122 and the data line 152 is reduced, and signal delay is prevented. The load on the line can be reduced. At this time, since the widths of the gate lines 122 and the data lines 152 can be reduced, and the pixel region P can be enlarged, an aperture ratio and brightness can be improved. The improvement of the aperture ratio depends on the size and resolution of the display device. Compared with the prior art, the aperture ratio can be increased by about 10% to about 50%, and as the resolution of the display device becomes higher, the aperture ratio can be further increased.

Since the auxiliary patterns 176 and 178 are simultaneously formed by the plating method after the gate line 122 and the data line 152 are exposed when the drain contact hole 162 and the capacitance contact hole 164 are formed, it is different from separately plating the gate line 122 and the data line. Compared with the case of line 152, the process can be simplified, the manufacturing cost can be reduced and the time can be shortened.

In addition, if the gate line 122 and the data line 152 are separately plated, the gate line 122 and the data line 152 are plated twice at their crossing portion, which results in a relatively high step at the crossing portion. Then, due to the steps, the layers formed on the intersection portions may be disconnected. However, in the present invention, since the gate lines 122 are not plated at the crossing portions, disconnection of layers formed on the crossing portions can be avoided. In addition, if the gate line 122 and the data line 152 are separately plated, the electrode of the thin film transistor T may be plated, which has problems such as deterioration of the thin film transistor T. However, in the present invention, the electrode of the thin film transistor T is not plated, and this problem is avoided.

Meanwhile, if the side surfaces of the contact holes 162, 164, 166, and 168 are inverted tapered when the contact holes 162, 164, 166, and 168 are formed by patterning the passivation layer 160, the back-formed Layers may be disconnected. However, in the present invention, metal patterns are formed in the contact holes 162, 164, 166, and 168 by a plating method. Thus, even if the side faces of the contact holes 162, 164, 166, and 168 are inversely tapered, disconnection of layers formed later can be prevented.

In the above embodiments, the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 have a single layer structure. The first auxiliary gate pattern 176 and the first auxiliary data pattern 178 may also have a multilayer structure by plating different materials. In particular, when the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 include copper, a nickel plating layer may be further formed on the copper plating layer in order to prevent oxidation and reduce contact resistance with subsequent layers.

This will be described with reference to FIG. 8 . FIG. 8 is a cross-sectional view illustrating another array substrate for a display device according to an exemplary embodiment of the present invention. The same reference numerals will be used to designate the same components as in the above embodiment, and explanations for the same components will be omitted.

In FIG. 8, the first auxiliary gate pattern 176 and the first auxiliary data pattern 178 each include a first plating layer 176a or 178a and a second plating layer 176b or 178b. The second plating layer 176b or 178b has a thickness smaller than that of the first plating layer 176a or 178a. Here, the drain contact pattern 172 and the capacitor contact pattern 174 also have a double layer structure of the first plating layer 172a or 174a and the second plating layer 172b or 174b.

For example, the first plating layers 172a, 174a, 176a, and 178a are formed by copper plating, and the second plating layers 172b, 174b, 176b, and 178b are formed by nickel plating. The second plating layers 172b, 174b, 176b, and 178b prevent the first plating layers 172a, 174a, 176a, and 178a from being oxidized, and reduce the contact between the pixel electrode 182, the second auxiliary gate pattern 184, and the second auxiliary data pattern 186. The contact resistance between the first plating layer 172a, 174a, 176a or 178a.

The first plating layers 172a, 174a, 176a, and 178a may have a thickness of greater than or equal to about 0.2 microns and less than or equal to about 5 microns, and advantageously may have a thickness of greater than or equal to about 2 microns and less than or equal to about 3 microns. The second plating layers 172b, 174b, 176b, and 178b may have a thickness greater than or equal to about 0.02 microns and less than or equal to about 0.1 microns.

In the above embodiments of the present invention, the common line and the capacitive electrode overlapping each other constitute a storage capacitor. Alternatively, the structure of the storage capacitor may be changed, which will be described with reference to FIGS. 9 and 10 .

FIG. 9 is a plan view illustrating an array substrate for a display device according to another embodiment of the present invention. FIG. 10 is a sectional view taken along line IX-IX of FIG. 9 .

In FIGS. 9 and 10 , gate lines 222 and gates 224 of conductive material are formed on a transparent insulating substrate 210 . The gate lines 222 are formed along the first direction, and the gate electrodes 224 extend from the gate lines 222 .

A gate insulating layer 230 of silicon nitride or silicon oxide is formed on the gate line 222 and the gate 224 , and the gate insulating layer 230 covers the gate line 222 and the gate 224 .

An active layer 242 of intrinsic amorphous silicon is formed on the gate insulating layer 230 and above the gate 224 . An ohmic contact layer 244 doped with amorphous silicon is formed on the active layer 242 .

A data line 252 of a conductive material such as metal, a source electrode 254 and a drain electrode 256 are formed on the ohmic contact layer 244 . The data line 252 is formed in a second direction perpendicular to the first direction, and the data line 252 crosses the gate line 222 to define a pixel region P. Referring to FIG. The source 254 extends from the data line 252 , and the drain 256 faces the source 254 and is separated from the source 254 above the gate 224 . A capacitor electrode 258 is formed on the gate insulating layer 230 over the first portion of the gate line 222 , and the capacitor electrode 258 is formed of the same material as the data line 252 , the source electrode 254 and the drain electrode 256 . Here, an intrinsic silicon pattern and a doped silicon pattern are formed under each of the data line 252 and the capacitance electrode 258 .

The source 254 and the drain 256 , the active layer 242 and the gate 224 form a TFT T, and the active layer 242 exposed between the source 254 and the drain 256 becomes a channel of the TFT T. The capacitor electrode 258 and the gate line 222 overlapping each other with the gate insulating layer 230 serving as a dielectric therebetween form a storage capacitor.

A passivation layer 260 is formed on the data line 252 , the source electrode 254 and the drain electrode 256 and the capacitor electrode 258 . The passivation layer 260 is formed of an inorganic insulating material such as silicon nitride and silicon oxide or an organic insulating material such as acrylic resin. The passivation layer 260 includes a drain contact hole 262 exposing the drain electrode 256 and a capacitor contact hole 264 exposing the capacitor electrode 258 . The passivation layer 260 further includes a first contact hole 266 exposing the second portion of the gate line 222 together with the gate insulating layer 230 , and the passivation layer 260 further includes a second contact hole 268 exposing the data line 252 .

A drain contact pattern 272 is formed in the drain contact hole 262 and contacts the drain electrode 256 . Capacitive contact patterns 274 are formed in the capacitive contact holes 264 and contact the capacitive electrodes 258 . A first auxiliary gate pattern 276 is formed in the first contact hole 266 and contacts the gate line 222 . A first auxiliary data pattern 278 is formed in the second contact hole 268 and contacts the data line 252 .

The drain contact pattern 272, the capacitor contact pattern 274, the first auxiliary gate pattern 276, and the first auxiliary data pattern 278 are formed by a plating method, and fill the contact holes 262, 264, 266, and 268, respectively. The drain contact pattern 272 , the capacitance contact pattern 274 , the first auxiliary gate pattern 276 and the first auxiliary data pattern 278 may have the same height as that of the passivation layer 260 or may be higher than the passivation layer 260 . The drain contact pattern 272, the capacitor contact pattern 274, the first auxiliary gate pattern 276, and the first auxiliary data pattern 278 may have the same thickness, and thus the drain contact pattern 272, the capacitor contact pattern 274, and the first auxiliary data pattern 278 may have the same thickness. The passivation layer 260 may be higher than the first auxiliary gate pattern 276 .

A pixel electrode 282 of a transparent conductive material is formed on the passivation layer 260 in the pixel region P. Referring to FIG. The pixel electrode 282 covers and contacts the drain contact pattern 272 and the capacitor contact pattern 274 , and the pixel electrode 282 is electrically connected to the drain electrode 256 and the capacitor electrode 258 . In addition, a second auxiliary gate pattern 284 and a second auxiliary data pattern 286 are respectively formed on the first auxiliary gate pattern 276 and the first auxiliary data pattern 278, and the second auxiliary gate pattern 284 and the second auxiliary data pattern 286 It is formed of the same material as the pixel electrode 282 . The second auxiliary gate pattern 284 and the second auxiliary data pattern 286 cover, contact and protect the first auxiliary gate pattern 276 and the first auxiliary data pattern 278, respectively.

Meanwhile, the capacitor electrode 258 may be omitted, and in this case, the pixel electrode 282 may overlap the gate line 222 to form a storage capacitor.

An array substrate according to another embodiment of the present invention may be manufactured through the processes of FIGS. 5A to 5D , 6A to 6F , 3 and 4 .

In the array substrate and the method for manufacturing the array substrate according to the present invention, auxiliary patterns are formed on the gate lines and the data lines. Thus, the resistance of the line can be reduced, and signal delay can be prevented. It is possible to reduce the load on the line. In addition, the width of the lines can be reduced, and the aperture ratio and brightness can be improved. At this time, auxiliary patterns are simultaneously formed on the gate lines and the data lines through a plating process, which simplifies the process. Manufacturing costs and time are reduced.

At the same time, the gate line is not plated at the crossing portion of the gate line and the data line, and it is possible to avoid disconnection of layers formed above the crossing portion. In addition, electrodes of thin film transistors are not plated. Thus, deterioration of the thin film transistor can be avoided.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention that come within the scope of the appended claims and their equivalents.

Claims (26)

1., for an array base palte for display device, the described array base palte for display device comprises:

Substrate;

Grid line, described grid line is formed on the substrate along first direction;

Data line, described data line is formed in the top of described substrate along second direction, wherein said data line and described grid line intersected with each other to limit pixel region;

Thin film transistor (TFT), described thin film transistor (TFT) is formed in described pixel region, and the source electrode that there is drain electrode, the grid be connected with described grid line and be connected with described data line;

Passivation layer, described passivation layer is in described drain electrode and comprise drain contact hole;

Drain contact pattern, described drain contact pattern to be formed in described drain contact hole and to contact described drain electrode, and the outermost border of wherein said drain contact pattern is arranged in the outermost border of described drain electrode; Pixel electrode, described pixel electrode is formed in described pixel region, and is connected with described drain electrode, and wherein said pixel electrode covers and contacts described drain contact pattern, makes described drain contact pattern setting between described drain electrode and described pixel electrode;

First auxiliary grid pattern, described first auxiliary grid pattern is formed in the top of described grid line and contacts with described grid line; And

First auxiliary data pattern, described first auxiliary data pattern be formed in described data line top and with described data line contact.

2. the array base palte for display device according to claim 1, comprises further:

Gate insulation layer, described gate insulation layer covers described grid line and described grid, and in the below of described data line;

Described passivation layer, described passivation layer is formed on described data line and described gate insulation layer;

First contact hole, described first contact hole is formed in described passivation layer and described gate insulation layer, and exposes described grid line along described first direction; And

Second contact hole, described second contact hole is formed in described passivation layer, and exposes described data line along described second direction,

Wherein said first auxiliary grid pattern is formed in described first contact hole; And described first auxiliary data pattern is formed in described second contact hole.

3. the array base palte for display device according to claim 1, comprises further:

Second auxiliary grid pattern, described second auxiliary grid pattern is formed on described first auxiliary grid pattern, to cover, to contact and to protect described first auxiliary grid pattern; And

Second auxiliary data pattern, described second auxiliary data pattern is formed on described first auxiliary data pattern, to cover, to contact and to protect described first auxiliary data pattern.

4. the array base palte for display device according to claim 3, wherein said second auxiliary grid pattern is formed by the material identical with described pixel electrode with described second auxiliary data pattern.

5. the array base palte for display device according to claim 1 and 2, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.

6. the array base palte for display device according to claim 2, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.

7. the array base palte for display device according to claim 1 and 2, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.

8. the array base palte for display device according to claim 2, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.

9. the array base palte for display device according to claim 1 and 2, wherein said first

Auxiliary data pattern is integrally formed along described data line.

10. the array base palte for display device according to claim 2, comprises further:

Concentric line, described concentric line is formed between adjacent grid line, and parallel with described grid line, and wherein said gate insulation layer covers described concentric line further;

Capacitance electrode, described capacitance electrode is formed in the top of described concentric line, and the described capacitance electrode wherein overlapped each other and described concentric line form holding capacitor together with the described gate insulation layer between described capacitance electrode and described concentric line; And

Capacitance contact pattern,

Wherein said passivation layer is formed on described capacitance electrode further, and described passivation layer comprises capacitance contact hole, described capacitance contact pattern to be formed in described capacitance contact hole and to contact described capacitance electrode, and described pixel electrode covers and contacts described capacitance contact pattern.

11. array base paltes for display device according to claim 10, wherein said drain contact pattern, described first auxiliary grid pattern, described first auxiliary data pattern and described capacitance contact pattern are formed by plating method.

12. array base paltes for display device according to claim 10, wherein said drain contact pattern, described first auxiliary grid pattern, described first auxiliary data pattern and described capacitance contact pattern are formed by copper, chromium or nickel.

13. array base paltes for display device according to claim 1, wherein said first auxiliary grid pattern and described first auxiliary data pattern each comprise the first plating layer of being formed by copper and the second plating layer formed by nickel on described first plating layer, and described second plating layer is thinner than described first plating layer.

14. 1 kinds of manufactures are used for the method for the array base palte of display device, said method comprising the steps of:

Substrate forms grid line along first direction, and forms grid on the substrate, wherein said grid extends from described grid line;

Form the gate insulation layer covering described grid line and described grid;

Described gate insulation layer is formed with active layer above described grid, described active layer forms ohmic contact layer;

Described gate insulation layer forms data line along second direction, and on described ohmic contact layer, form source electrode and drain electrode, wherein said data line and described grid line intersected with each other to limit pixel region, described source electrode extends from described data line, and described drain electrode and described source electrode are separated above described grid;

Described drain electrode forms passivation layer, and described passivation layer comprises drain contact hole;

In described drain contact hole, form drain contact pattern, and drain described in described drain contact pattern contacts, the outermost border of wherein said drain contact pattern is arranged in the outermost border of described drain electrode;

Form the first auxiliary grid pattern to contact described grid line, and form the first auxiliary data pattern to contact described data line; And

In described pixel region, form pixel electrode, described pixel electrode is connected with described drain electrode, and wherein said pixel electrode covers and contacts described drain contact pattern, makes described drain contact pattern setting between described drain electrode and described pixel electrode.

15. methods according to claim 14, further comprising the steps:

Described data line and described source electrode form described passivation layer; And

In described passivation layer and described gate insulation layer, form the first contact hole, to expose described grid line, and form the second contact hole in described passivation layer, to expose described data line,

Wherein said first auxiliary grid pattern is formed in described first contact hole, and described first auxiliary data pattern is formed in described second contact hole.

16. methods according to claim 14, wherein in the step forming pixel electrode, described first auxiliary grid pattern forms the second auxiliary grid pattern, to cover and to contact described first auxiliary grid pattern, and on described first auxiliary data pattern, form the second auxiliary data pattern, to cover and to contact described first auxiliary data pattern.

17. methods according to claim 16, wherein said second auxiliary grid pattern is formed by the material identical with described pixel electrode with described second auxiliary data pattern.

18. methods according to claim 16, wherein:

In the step forming grid line, between adjacent grid line, form concentric line abreast with described grid line;

In the step forming gate insulation layer, described gate insulation layer covers described concentric line further;

In the step being formed with active layer, above described concentric line, form capacitance electrode, and the described capacitance electrode overlapped each other and described concentric line and the described gate insulation layer between described capacitance electrode and described concentric line together form holding capacitor;

In the step forming drain contact hole, in described passivation layer, form capacitance contact hole, to expose described capacitance electrode;

In the step of formation first auxiliary grid pattern, in described capacitance contact hole, form capacitance contact pattern, to contact described capacitance electrode; And

In the step forming pixel electrode, described pixel electrode covers further and contacts described capacitance contact pattern.

19. methods according to claim 14, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.

20. methods according to claim 15, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.

21. methods according to claim 18, wherein said capacitance contact pattern, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by plating method.

22. methods according to claim 14, wherein said first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.

23. methods according to claim 15, wherein said drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.

24. methods according to claim 18, wherein said capacitance contact pattern, described drain contact pattern, described first auxiliary grid pattern and described first auxiliary data pattern are formed by copper, chromium or nickel.

25. methods according to claim 14, wherein said first auxiliary data pattern is integrally formed along described data line.

26. methods according to claim 14, wherein form described first auxiliary grid pattern and described first auxiliary data pattern comprise the first plating layer of being formed and being formed by copper and on described first plating layer, form the second plating layer formed by nickel, and wherein said second plating layer is thinner than described first plating layer.