KR20080070320A - Display substrate and manufacturing method thereof - Google Patents

Abstract

Disclosed are a display substrate and a method of manufacturing the same for reducing defects. The display substrate includes a first metal pattern, a first electrode, a first insulating layer, a second metal pattern, a second insulating layer, and a second electrode. The first metal pattern is formed on the substrate and includes a gate wiring and a storage common wiring extending parallel to the gate wiring. The first electrode is formed on the substrate on which the first metal pattern is formed corresponding to the unit pixel, and covers at least a portion of the storage common wiring. The first insulating layer is formed on the substrate on which the first electrode is formed. The second metal pattern is formed on the first insulating layer and includes data lines. The second insulating layer is formed on the first insulating layer on which the second metal pattern is formed. The second electrode is formed on the second insulating layer corresponding to the unit pixel. Accordingly, by forming the first electrode to cover a part or the entirety of the storage common wiring, the area where the storage common wiring is exposed to the developer during the photolithography process of patterning the first electrode can be reduced.

Description

DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view illustrating a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 to 9 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: display substrate 200: opposing substrate

300: liquid crystal layer 400: liquid crystal display panel

STL: Storage Common Wiring 120: Gate Insulation Layer

CE: first electrode PE: second electrode

160: passivation layer GP: gate pad

The present invention relates to a display substrate and a method of manufacturing the same, and more particularly, to a display substrate and a method of manufacturing the same for reducing defects.

Recently, various liquid crystal mode technologies, including IPS (In-Plane Switching) mode, have been developed to implement a wide viewing angle of a liquid crystal display panel. In particular, the FFS (Fringe Field Switching) mode developed by the wide viewing angle mass production technology has a similar concept to the IPS mode, which is a conventional wide viewing angle mode. Unlike the IPS mode, it uses the birefringence phenomenon caused by the difference between the twist and tilt of the liquid crystal by the electric field diagonal to the substrate.

Specifically, the FFS mode liquid crystal display panel includes a display substrate, an opposing substrate, and a liquid crystal layer interposed between the display substrate and the opposing substrate, and the display substrate includes a plurality of units by gate lines and data lines intersecting each other. Pixels are defined.

In the unit pixel, a thin film transistor connected to a gate line and a data line, a storage common line formed of a gate metal pattern similar to the gate line, a common electrode, and a pixel electrode are formed. The common electrode and the pixel electrode are formed corresponding to the unit pixel, and are formed to face each other with an insulating layer interposed therebetween. In this case, the common electrode is in contact with the storage common wiring to receive a common voltage. The pixel electrode is formed on the common electrode with the insulating layer interposed therebetween, and a plurality of opening patterns spaced at predetermined intervals are formed to form a transverse electric field between the pixel electrode and the common electrode.

Accordingly, the technical problem of the present invention is focused on such a conventional point, and an object of the present invention is to provide a display substrate for reducing defects.

Another object of the present invention is to provide a method of manufacturing the display substrate.

In order to achieve the above object of the present invention, the display substrate according to the embodiment includes a first metal pattern, a first electrode, a first insulating layer, a second metal pattern, a second insulating layer, and a second electrode. The first metal pattern is formed on a substrate, and includes a gate wiring and a storage common wiring extending parallel to the gate wiring. The first electrode is formed on the substrate on which the first metal pattern is formed corresponding to the unit pixel, and covers at least a portion of the storage common wiring. The first insulating layer is formed on the substrate on which the first electrode is formed. The second metal pattern is formed on the first insulating layer and includes a data line. The second insulating layer is formed on the first insulating layer on which the second metal pattern is formed. The second electrode is formed on the second insulating layer corresponding to the unit pixel.

According to another aspect of the present invention, there is provided a method of manufacturing a display substrate, including forming a first metal pattern including a gate wiring and a storage common wiring extending in parallel to the gate wiring; Forming a first electrode on the substrate on which the first metal pattern is formed corresponding to the unit pixel, and covering at least a portion of the storage common wiring; and forming a first electrode on the substrate on which the first electrode is formed. Forming an insulating layer, forming a second metal pattern including data lines on the first insulating layer, and forming a second insulating layer on the substrate on which the second metal pattern is formed. And forming a second electrode on the second insulating layer corresponding to the unit pixel.

According to the display substrate and the method of manufacturing the same, the area where the storage common wiring is exposed to the developer during the photolithography process for patterning the first electrode can be reduced, so that when the first metal pattern and the first electrode are simultaneously exposed to the developer It can reduce the battery effect that occurs in.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a liquid crystal display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, the liquid crystal display panel 400 includes a display substrate 100, an opposing substrate 200, and a liquid crystal layer 300 interposed between the display substrate 100 and the opposing substrate 200. It includes.

The display substrate 100 includes a base substrate 110. The base substrate 110 is made of a transparent material through which light can pass. In one example, the base substrate 110 is a glass substrate. A plurality of unit pixels P are defined on the base substrate 110 by gate lines GL and data lines DL intersecting the gate lines GL. In the unit pixel P, a thin film transistor TFT connected to the gate line GL and the data line DL, a storage common line STL extending in the same direction as the gate line GL, and a first line. The electrode CE and the second electrode PE are formed.

In detail, the gate lines GL and the storage common line STL are gate metal patterns formed by patterning the same metal layer. The common voltage is applied to the storage common line STL from an external driving circuit unit. In addition, the gate metal pattern may include a gate electrode G protruding from the gate line GL.

The first electrode CE corresponding to the unit pixel P is formed on the base substrate 110 on which the gate metal pattern including the gate lines GL, the gate electrode G, and the storage common line STL is formed. ) Is formed. The first electrode CE is made of a transparent conductive material. As the transparent conductive material, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, and the like may be used. Preferably, the amorphous indium tin oxide is used. Made of oxide.

In this case, the first electrode CE may cover a part of the storage common wiring STL formed in the unit pixel P or may cover the whole.

The first electrode CE contacts the storage common line STL and receives a common voltage from the storage common line STL.

The gate insulating layer 120 is formed on the base substrate 110 on which the first electrode CE is formed. The gate insulating layer 120 may be formed of, for example, silicon nitride (SiNx).

A first hole (not shown) and a second hole (not shown) are formed in the gate insulating layer 120 to expose one end of the gate line GL and one end of the storage common line STL, respectively. .

The active layer A overlapping the gate electrode G is formed on the gate insulating layer 120. For example, the active layer A may have a structure in which a semiconductor layer 131 made of amorphous silicon and an ohmic contact layer 132 made of n + ion-doped amorphous silicon are sequentially stacked.

A data metal pattern including the data line DL, the source electrode S, and the drain electrode D is formed on the gate insulating layer 120 on which the active layer A is formed.

The source electrode S protrudes from the data line DL and partially overlaps the gate electrode G. The drain electrode D is formed spaced apart from the source electrode S by a predetermined interval and partially overlaps the gate electrode G.

The gate electrode G, the active layer A, the source electrode S, and the drain electrode D constitute the thin film transistor TFT.

In this case, the ohmic contact layer 132 is removed from the source electrode S and the drain electrode D to expose the semiconductor layer 131. The exposed region of the semiconductor layer 131 is a region in which an electrical channel of the thin film transistor TFT is formed.

The data metal pattern covers one end of the gate wiring GL exposed in the first hole and one end of the storage common wiring STL exposed in the second hole. It may further include a first cover pattern (CP).

The passivation layer 160 is formed on the base substrate 110 on which the thin film transistor TFT is formed. The passivation layer 160 is made of, for example, silicon nitride (SiNx), and a contact hole (CH) exposing one end of the drain electrode (D) is formed in the passivation layer (160), and the data line The data pad hole DH exposing one end of the DL, the gate pad hole GH exposing one end of the gate line GL, and the storage pad hole SH exposing one end of the storage common line STL. ) Is formed.

The second electrode PE is formed on the passivation layer 160 to correspond to the unit pixel P. Preferably, the second electrode PE is made of a transparent conductive material. As the transparent conductive material, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like may be used.

The second electrode PE is electrically connected to the drain electrode D through the contact hole CH, and receives a pixel voltage provided from the data line DL.

In this case, a plurality of opening patterns OP spaced at predetermined intervals are formed in the second electrode PE. For example, the opening patterns OP may extend in the first direction X, and the plurality of opening patterns OP may be arranged to be spaced apart from each other in the second direction Y by a predetermined interval.

Since different voltages are applied to the first electrode CE and the second electrode PE, a transverse electric field is formed between the first electrode CE and the second electrode PE by the opening patterns OP. Is formed. Therefore, the liquid crystal molecules of the liquid crystal layer 300 are rearranged by the transverse electric field.

Accordingly, light provided from the rear surface of the liquid crystal display panel 400 is transmitted to display an image on the counter substrate 200.

On the other hand, a second cover made of a transparent conductive material constituting the second electrode PE on the passivation layer and covering the data pad hole DH, the gate pad hole GH, and the storage pad hole SH. The pattern CP2 may be further formed.

Accordingly, a gate pad GP is formed at one end of the gate line GL, a data pad DP is formed at one end of the data line DL, and one end of the storage common line STL. The storage pad STP is formed in the unit.

Hereinafter, a method of manufacturing a display substrate according to an exemplary embodiment of the present invention will be described.

3 to 9 are process diagrams illustrating a method of manufacturing a display substrate according to an exemplary embodiment of the present invention.

1 and 3, a first metal layer (not shown) is formed on the base substrate 110. The first metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the first metal layer may be formed of two or more layers having different physical properties. In one example, the first metal layer is made of aluminum neodymium alloy.

Subsequently, a photoresist film (not shown) is formed on the first metal layer. The photoresist film is made of, for example, a positive photoresist in which the exposed region is dissolved by a developer.

Next, the first mask MASK1 is aligned on the base substrate 110 on which the first photoresist film is formed. The first mask MASK1 includes a light transmitting part 4 for transmitting light and a light blocking part 2 for blocking light. Next, the photoresist film is exposed using the first mask MASK1, and a series of photolithography (PHOTOLITHOGRAPHY) processes for developing and curing the exposed first photoresist film are performed. Accordingly, the first photoresist pattern PR1 is formed on the metal layer.

Subsequently, the first metal layer is patterned by an etching process using the first photoresist pattern PR1 to form a gate metal pattern including gate lines GL, a gate electrode G, and a storage common line STL. do.

The gate lines GL extend in parallel to each other on the base substrate 110. The gate electrode G is formed to protrude from the gate line GL. The storage common line STL extends in parallel with the gate lines GL between the gate lines GL.

An etching process of forming the gate metal pattern is, for example, a wet etching process. After the etching process is completed, a strip process of removing the first photoresist pattern PR1 remaining on the gate metal pattern is performed.

On the other hand, the photoresist film may be made of a negative photoresist. In this case, the arrangement of the light blocking portion 2 and the light transmitting portion 4 is reversed in the first mask MASK1.

Referring to FIG. 4, a transparent conductive material layer is formed on the base substrate 110 on which the gate metal pattern is formed. The transparent conductive material layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be deposited by a sputtering method. In one example, the transparent conductive material layer is made of amorphous indium tin oxide.

Next, a second photoresist film is coated on the transparent conductive material layer and the second photoresist film is patterned by a photolithography process using a second mask MASK2 to form a second photoresist pattern PR2.

Subsequently, the transparent conductive material layer is patterned by an etching process using the second photoresist pattern PR2 to form a first electrode CE corresponding to the unit pixel P. In this case, the first electrode CE is formed to cover at least a portion of the storage common wiring STL. That is, the first electrode CE may cover a portion of the storage common line STL in the unit pixel P or may cover an entire area of the storage common line STL.

When the etching process for forming the first electrode CE is completed, the strip process of removing the second photoresist pattern PR2 remaining on the first electrode CE is performed.

As described above, according to the present invention, the gate metal pattern is first formed, and the first electrode CE is formed on the gate metal pattern to cover a part or the entirety of the storage common wiring STL. ), The area of the gate metal pattern exposed to the developer may be reduced during the photolithography process. When the gate metal pattern and the first electrode CE are simultaneously exposed to the developer, the gate metal may be caused by a battery effect between the metal material constituting the gate metal pattern and the material constituting the first electrode CE. Lifting failure of the pattern may occur. This battery effect is further intensified when the gate metal pattern is formed of an aluminum neodymium alloy and the first electrode is made of amorphous indium tin oxide.

However, in the present invention, since the first electrode CE covers a part or the entirety of the storage common wiring STL having the gate metal pattern, the rate at which the lifting failure occurs due to the battery effect can be reduced. Accordingly, poor wiring of the display substrate 100 can be reduced, and reliability of the display substrate 100 can be improved.

1 and 5, the gate insulating layer 120 is formed on the base substrate 110 on which the gate metal pattern and the first electrode CE are formed by using a chemical vapor deposition method. For example, the gate insulating layer 120 may be formed of silicon nitride or silicon oxide. In addition, the gate insulating layer 120 may be formed in a double layer structure having different materials and forming processes.

Subsequently, the semiconductor layer 131 and the ohmic contact layer 132 are sequentially formed on the gate insulating layer 120 using the chemical vapor deposition method.

Subsequently, a photoresist film is coated on the ohmic contact layer 132 and the photoresist film is patterned by a photolithography process using a third mask MASK3 to form a third photoresist pattern PR3. Next, the semiconductor layer 131 and the ohmic contact layer 132 are simultaneously patterned by an etching process using the third photoresist pattern PR3 to form an active layer A overlapping the gate electrode G. FIG. do. When the etching process for forming the active layer A is completed, the strip process of removing the third photoresist pattern PR3 is performed.

1 and 6, a fourth photoresist is formed by coating a photoresist film on the base substrate 110 on which the active layer A is formed, and patterning the photoresist film by a photolithography process using a fourth mask MASK4. The pattern PR4 is formed.

Next, the gate insulating layer 120 corresponding to one end of the gate line GL and one end of the storage common line STL is etched by an etching process using the fourth photoresist pattern PR4. Accordingly, a first hole H1 exposing one end of the gate line GL and a second hole H2 exposing one end of the storage common line STL are formed.

1 and 7, a second metal layer (not shown) is formed on the gate insulating layer 120 where the gate pad hole GH is formed. The second metal layer may be formed of, for example, a metal such as chromium, aluminum, tantalum, molybdenum, titanium, tungsten, copper, silver, or an alloy thereof, or the like, and is deposited by a sputtering process. In addition, the second metal layer may be formed of two or more layers having different physical properties.

Subsequently, a photoresist film is coated on the second metal layer and the photoresist film is patterned by a photolithography process using a fifth mask MASK5 to form a fifth photoresist pattern PR5. Next, the second metal layer is patterned by an etching process using the fifth photoresist pattern PR5 to form a data metal pattern including a data line DL, a source electrode S, and a drain electrode D. FIG. . The data metal pattern may further include a first cover pattern CP1 covering the gate pad hole GH and the storage pad hole SH.

Subsequently, the ohmic contact layer 132 exposed at the spaced portion between the source electrode S and the drain electrode D is etched to expose the semiconductor layer 131. Accordingly, a thin film transistor TFT is formed on the base substrate 110.

Meanwhile, when the etching process of the ohmic contact layer 132 is finished, a strip process of removing the fifth photoresist pattern PR5 remaining on the data metal pattern is performed.

1 and 8, the passivation layer 160 is formed on the base substrate 110 on which the thin film transistor TFT is formed by using a chemical vapor deposition method. The passivation layer 160 may be made of, for example, silicon nitride or silicon oxide.

Subsequently, a photoresist film is coated on the passivation layer 160, and the photoresist film is patterned by a photolithography process using a sixth mask to form a sixth photoresist pattern PR6. Next, the passivation layer 160 is patterned by an etching process using the sixth photoresist pattern PR6 to form a contact hole CH exposing one end of the drain electrode D. FIG. The data pad hole DH exposing one end of the data line DL, the gate pad hole GH corresponding to one end of the gate line GL, and one end of the storage common line STL. A corresponding storage pad hole SH is formed.

1 and 9, a transparent conductive material layer is formed on the passivation layer 160. The transparent conductive material layer may be formed of, for example, indium tin oxide, indium zinc oxide, amorphous indium tin oxide, or the like, and may be deposited by a sputtering method. Next, a photoresist film is coated on the transparent conductive material layer and the photoresist film is patterned by a photolithography process using a seventh mask MASK7 to form a seventh photoresist pattern PR7.

Subsequently, the transparent conductive material layer is patterned by an etching process using the seventh photoresist pattern PR7 to form a second electrode PE corresponding to the unit pixel P.

In the second electrode PE, a plurality of opening patterns OP spaced at predetermined intervals are formed. For example, the opening patterns OP may extend in the first direction X, and the plurality of opening patterns OP may be arranged to be spaced apart from each other in the second direction Y by a predetermined interval. A transverse electric field is formed between the first electrode CE and the second electrode PE by the opening patterns OP.

In the meantime, a second layer covering one end of the gate line GL, one end of the data line DL, and one end of the storage common line STL in a photolithography process of forming the second electrode PE. The cover pattern CP2 may be further formed.

According to the present invention, by forming the first electrode CE to cover a portion or the entirety of the storage common wiring STL, the storage common wiring STL is exposed to the developer during the photolithography process of patterning the first electrode CE. The area to be reduced can be reduced. Accordingly, the lifting failure of the storage common wiring STL due to the battery effect caused when the storage common wiring STL and the first electrode CE are simultaneously exposed to the developer may be reduced.

As described above, according to the present invention, the first electrode is formed to cover a part or the entirety of the storage common wiring in the display substrate in the FFS mode so that the storage common wiring is exposed to the developer during the photolithography process of patterning the first electrode. The area can be reduced. Accordingly, the lifting failure of the storage common wiring due to the battery effect generated when the storage common wiring and the first electrode are simultaneously exposed to the developer can be reduced.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (11)

A first metal pattern formed on the substrate, the first metal pattern including a gate wiring and a storage common wiring extending parallel to the gate wiring; A first electrode formed on the substrate on which the first metal pattern is formed corresponding to the unit pixel and covering at least a portion of the storage common line; A first insulating layer formed on the substrate on which the first electrode is formed; A second metal pattern formed on the first insulating layer and including data lines; A second insulating layer formed on the first insulating layer on which the second metal pattern is formed; And And a second electrode formed on the second insulating layer corresponding to the unit pixel. The display substrate of claim 1, wherein a plurality of opening patterns arranged in a predetermined direction are formed in the second electrode to form a transverse electric field between the first electrode and the first electrode. The display substrate of claim 1, further comprising a thin film transistor connected to the gate line and the data line and formed in the unit pixel. The display substrate of claim 3, wherein the first electrode receives a common voltage from the storage common line, and the second electrode receives a pixel voltage from the thin film transistor. The display substrate of claim 1, wherein the first metal pattern comprises aluminum. The display substrate of claim 1, wherein the first electrode is made of a transparent conductive material. Forming a first metal pattern on the substrate, the first metal pattern including a gate wiring and a storage common wiring extending parallel to the gate wiring; Forming a first electrode formed on the substrate on which the first metal pattern is formed corresponding to a unit pixel and covering at least a portion of the storage common wiring; Forming a first insulating layer on the substrate on which the first electrode is formed; Forming a second metal pattern including data lines on the first insulating layer; Forming a second insulating layer on the substrate on which the second metal pattern is formed; And And forming a second electrode on the second insulating layer corresponding to the unit pixel. The method of claim 7, wherein forming the second electrode Forming a conductive material layer on the second insulating layer; And Etching the conductive material layer to form a plurality of opening patterns arranged in a predetermined direction in the unit pixel. 8. The method of claim 7, further comprising forming a first hole that exposes one end of the gate line by etching the first insulating layer. The method of claim 9, wherein the forming of the second metal pattern comprises: The method of claim 1, further comprising forming a cover pattern covering the first hole. The method of claim 7, further comprising forming a thin film transistor in the unit pixel, wherein the forming of the thin film transistor is performed. Forming a gate electrode protruding from the gate wiring using the first metal pattern; Forming an active layer on the first insulating layer so as to overlap the gate electrode; And Forming a source electrode partially overlapping the active layer and a drain electrode partially overlapping the active layer with a predetermined distance from the source electrode, using the second metal pattern; .

Images