CN102881631B - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- CN102881631B CN102881631B CN201110195504.XA CN201110195504A CN102881631B CN 102881631 B CN102881631 B CN 102881631B CN 201110195504 A CN201110195504 A CN 201110195504A CN 102881631 B CN102881631 B CN 102881631B
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- CN
- China
- Prior art keywords
- semiconductor substrate
- gate oxide
- layer
- barrier layer
- diffusion barrier
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052802 copper Inorganic materials 0.000 claims abstract description 46
- 239000010949 copper Substances 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 19
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 8
- 239000002243 precursor Substances 0.000 claims abstract description 8
- XZMCDFZZKTWFGF-UHFFFAOYSA-N Cyanamide Chemical compound NC#N XZMCDFZZKTWFGF-UHFFFAOYSA-N 0.000 claims abstract description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001257 hydrogen Substances 0.000 claims abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 28
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 3
- 239000000428 dust Substances 0.000 claims description 3
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 abstract 2
- 230000001939 inductive effect Effects 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps: providing a semiconductor substrate, forming a grid structure on the semiconductor substrate and forming active/drain regions at the two sides of the grid structure; forming dielectric layers on the semiconductor substrate and forming copper metal interconnecting lines in the dielectric layers; and copper diffusion impervious layers are formed on the dielectric layers and the copper interconnecting lines, wherein a precursor material used for forming the copper interconnecting lines comprising hexamethyldisilazane, cyanamide and ammonia. According to the manufacturing method of the semiconductor device, hydrogen can be effectively prevented from entering a gate oxide through copper diffusion to inducing leakage by the gate oxide, so that the reliability of the gate oxide can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, adopt new copper metal diffusion barrier layer to improve the method for gate oxide leaky in particular to a kind of.
Background technology
Along with IC manufactures improving constantly of integrated level, the gate oxide of MOS device thins down.Although operating voltage is minimized, day by day microminiaturized and the improving constantly of performance of device makes the electric field strength putting on gate oxide higher.Electric field strength is higher, and gate oxide leaky is more serious, occur through time dielectric breakdown (TDDB) time shorter, therefore, more and more higher to the requirement of reliability of the gate oxide.
The factor affecting reliability of the gate oxide is a lot, and the performance of the constituent material of such as gate oxide own, the method forming gate oxide, subsequent technique are on the impact (such as stress influence) etc. of gate oxide.There are some researches show, after the metal interconnected technique of enforcement copper, the interface trap density of the gate oxide measured by charge pump (charge-pumping) method is increased, namely the defect in gate oxide increases, increasing of defect counts makes the leaky of gate oxide increase, so occur through time dielectric breakdown (TDDB) possibility greatly improve.This needs in the process owing to implementing the metal interconnected technique of copper to form the barrier layer stoping the diffusion of copper metal, for stoping lower floor's copper metal to upper strata dielectric layer and upper copper metal to the diffusion of lower floor's dielectric layer, usual employing silicon nitride, as the material of described copper metal diffusion barrier layer, forms silicon nitride and usually makes silane (SiH by plasma enhanced chemical vapor deposition (PECVD)
4) and ammonia (NH
3) react to prepare.There is a large amount of si-h bonds (Si-H) in silicon nitride prepared by this method, hydrogen wherein can be diffused in gate oxide by copper metal under the effect of electric field, and induction gate oxide produces defect, and then affects the reliability of gate oxide.
Therefore, need to propose a kind of method to form new copper metal diffusion barrier layer, to avoid hydrogen to induce gate oxide to produce electric leakage, affect the reliability of gate oxide.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, be formed with grid structure on the semiconductor substrate, and be formed with source/drain region in the both sides of described grid structure; Form dielectric layer on the semiconductor substrate, and form copper metal interconnecting wires in described dielectric layer; Described dielectric layer and copper metal interconnecting wires form copper diffusion barrier layer, and the precursor material forming described copper diffusion barrier layer comprises hexamethyldisiloxane.
Preferably, chemical vapor deposition method is adopted to form described copper diffusion barrier layer.
Preferably, the flow of hexamethyldisiloxane is 100-1000sccm.
Preferably, the precursor material forming described copper diffusion barrier layer also comprises cyanamide.
Preferably, the flow of cyanamide is 100-1000sccm.
Preferably, the precursor material forming described copper diffusion barrier layer also comprises ammonia.
Preferably, the flow of ammonia is 100-1000sccm.
Preferably, adopt helium as the carrier gas of described chemical vapour deposition (CVD).
Preferably, the flow of helium is 1000-2000sccm.
Preferably, described chemical vapor deposition processes is at pressure 3-7Torr, carries out under the condition of power 150-1000W.
Preferably, the thickness of described copper diffusion barrier layer is 100-2000 dust.
Preferably, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually.
Preferably, described gate dielectric is gate oxide.
Preferably, described dielectric layer is the material layer with low-k.
According to the present invention, can effectively avoid hydrogen to diffuse into gate oxide by copper metal, induction gate oxide produces electric leakage, improves the reliability of gate oxide.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 C is that the new copper metal diffusion barrier layer of employing that the present invention proposes is to improve the schematic cross sectional view of each step of the method for gate oxide leaky;
Fig. 2 is that the new copper metal diffusion barrier layer of employing that the present invention proposes is to improve the flow chart of the method for gate oxide leaky.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, proposing detailed step by following description, how to adopt new copper metal diffusion barrier layer to improve the leaky of gate oxide to explain the present invention.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Below, the new copper metal diffusion barrier layer of employing that the present invention proposes is described to improve the detailed step of the method for gate oxide leaky with reference to Figure 1A-Fig. 1 C and Fig. 2.
With reference to Figure 1A-Fig. 1 C, illustrated therein is the new copper metal diffusion barrier layer of employing that the present invention proposes to improve the schematic cross sectional view of each step of the method for gate oxide leaky.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.Isolation channel is formed with, buried regions in Semiconductor substrate 100, and various trap (well) structure, in order to simplify, omitted in diagram.
Described Semiconductor substrate 100 is formed with grid structure 102, and as an example, described grid structure 102 comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.Gate dielectric can be oxide skin(coating), such as, and silicon dioxide (SiO
2) layer; Gate material layers can be polysilicon layer; Grid hard masking layer can be oxide skin(coating).
In addition, exemplarily, described Semiconductor substrate 100 is also formed is positioned at described grid structure 102 both sides and near the clearance wall structure 103 of grid structure.Wherein, clearance wall structure can comprise at least one deck oxide skin(coating) and/or at least one deck nitride layer.
Source region 104 and drain region 105 is formed respectively in the Semiconductor substrate of described grid structure 102 both sides.
Before the described grid structure 102 of formation, monoxide layer 101 can be formed in described Semiconductor substrate 100, to make Semiconductor substrate 100 in subsequent process steps from unnecessary loss.
Then, as shown in Figure 1B, described Semiconductor substrate 100 is formed a dielectric layer 106, it typically is the material layer with low-k, in the present embodiment, adopt silicon oxide layer.The groove for filling metal interconnecting wires is formed in described dielectric layer 106.Deposit a metal level, such as copper metal layer, on described dielectric layer 106, and fill up the groove in described dielectric layer 106.Adopt chemical mechanical milling tech to remove unnecessary copper metal layer, be ground to the surface termination of described dielectric layer 106, in described dielectric layer 106, form copper metal interconnecting wires 107.
Then, as shown in Figure 1 C, described dielectric layer 106 and copper metal interconnecting wires 107 form a barrier layer 108.Described barrier layer 108 is for stoping lower floor's copper metal to upper strata dielectric layer and upper copper metal to the diffusion of lower floor's dielectric layer.Chemical vapor deposition method is adopted to form described barrier layer 108, wherein, with the carrier gas of helium (He) as chemical vapour deposition (CVD), with hexamethyldisiloxane (C
6h
19nSi
2), cyanamide (CH
2n
2) and ammonia (NH
3) as the precursor material forming described barrier layer 108, C
6h
19nSi
2, CH
2n
2and NH
3react and form carbonitride of silicium (Si
xc
yn
z) as the material on described barrier layer 108, reduce hydrogen to the impact of reliability of the gate oxide.
The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 3-7Torr, power 150-1000W, C
6h
19nSi
2flow be 100-1000sccm, CH
2n
2flow be 100-1000sccm, NH
3flow be the flow of 100-1000sccm, He be 1000-2000sccm.The thickness on the described barrier layer 108 that deposition is formed is 100-2000 dust.
So far, whole processing steps that the method according to an exemplary embodiment of the present invention that completes is implemented, according to the present invention, can effectively avoid hydrogen to diffuse into gate oxide by copper metal, and induction gate oxide produces electric leakage, improves the reliability of gate oxide.
With reference to Fig. 2, illustrated therein is the new copper metal diffusion barrier layer of employing that the present invention proposes to improve the flow chart of the method for gate oxide leaky, for schematically illustrating the flow process of whole manufacturing process.
In step 201, provide Semiconductor substrate, be formed with grid structure on the semiconductor substrate, and be formed with source/drain region in the both sides of described grid structure;
In step 202., form dielectric layer on the semiconductor substrate, and form copper metal interconnecting wires in described dielectric layer;
In step 203, described dielectric layer and copper metal interconnecting wires form copper diffusion barrier layer, the precursor material forming described copper diffusion barrier layer comprises hexamethyldisiloxane, cyanamide and ammonia.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, is formed with grid structure on the semiconductor substrate, and be formed with source/drain region in the both sides of described grid structure;
Form dielectric layer on the semiconductor substrate, and form copper metal interconnecting wires in described dielectric layer;
Described dielectric layer and copper metal interconnecting wires form copper diffusion barrier layer, and the precursor material forming described copper diffusion barrier layer comprises hexamethyldisiloxane, cyanamide and ammonia, to avoid the diffusion of the hydrogen in described precursor material.
2. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described copper diffusion barrier layer.
3. method according to claim 1, is characterized in that, the flow of hexamethyldisiloxane is 100-1000sccm.
4. method according to claim 1, is characterized in that, the flow of cyanamide is 100-1000sccm.
5. method according to claim 1, is characterized in that, the flow of ammonia is 100-1000sccm.
6. method according to claim 2, is characterized in that, adopts helium as the carrier gas of described chemical vapour deposition (CVD).
7. method according to claim 6, is characterized in that, the flow of helium is 1000-2000sccm.
8. method according to claim 2, is characterized in that, described chemical vapor deposition processes is at pressure 3-7Torr, carries out under the condition of power 150-1000W.
9. method according to claim 1 and 2, is characterized in that, the thickness of described copper diffusion barrier layer is 100-2000 dust.
10. method according to claim 1, is characterized in that, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually.
11. methods according to claim 10, is characterized in that, described gate dielectric is gate oxide.
12. methods according to claim 1, is characterized in that, described dielectric layer is the material layer with low-k.
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|---|---|---|---|
| CN201110195504.XA CN102881631B (en) | 2011-07-13 | 2011-07-13 | Manufacturing method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110195504.XA CN102881631B (en) | 2011-07-13 | 2011-07-13 | Manufacturing method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| CN102881631A CN102881631A (en) | 2013-01-16 |
| CN102881631B true CN102881631B (en) | 2014-12-17 |
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|---|---|---|---|
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| CN105448724B (en) * | 2014-08-22 | 2019-03-22 | 无锡华润上华科技有限公司 | A kind of semiconductor devices and its manufacturing method, electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200746356A (en) * | 2005-08-15 | 2007-12-16 | Renesas Tech Corp | Semiconductor integrated circuit device and method for manufacture thereof |
| CN101252087A (en) * | 2007-02-16 | 2008-08-27 | 东京毅力科创株式会社 | SiCN film formation method and apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002198325A (en) * | 2000-12-26 | 2002-07-12 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
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- 2011-07-13 CN CN201110195504.XA patent/CN102881631B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200746356A (en) * | 2005-08-15 | 2007-12-16 | Renesas Tech Corp | Semiconductor integrated circuit device and method for manufacture thereof |
| CN101252087A (en) * | 2007-02-16 | 2008-08-27 | 东京毅力科创株式会社 | SiCN film formation method and apparatus |
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| CN102881631A (en) | 2013-01-16 |
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