CN102880770B - Central processing unit (CPU) access sequence simulation model based on macro-instruction queue - Google Patents
Central processing unit (CPU) access sequence simulation model based on macro-instruction queue Download PDFInfo
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Abstract
The invention discloses a central processing unit (CPU) access sequence simulation model based on a macro-instruction queue. The CPU access sequence simulation model comprises an instruction buffer module, a secondary cache and elimination buffer module, a secondary request processing module, a flow control module, an instruction scheduling module and an instruction decoding module, wherein the instruction buffer module comprises instruction buffers of which the number is the same as that of the suspended buffers in a Cache non-hit request inside the CPU, wherein the transmitted instruction carries a buffer number where the instruction buffers are positioned by utilizing the redundant field, so that the correctness is checked according to the instruction buffer number returned by the original response sample; the secondary cache and elimination buffer module is used for simulating the operation of secondary cache and elimination buffer and checking the validity of the secondary request and response; the secondary request processing module is used for simulating the processing function of the secondary request, receiving the secondary request and returning the response of corresponding types; the flow control module is used for simulating the flow control functions of the primary request queue and response queue; the instruction scheduling module is used for scheduling an instruction from multiple instruction buffers for execution; and the instruction decoding module is used for executing conversion from an instruction format of the instruction buffers to a format packet of logic interfaces between the CPU and consistency protocol hardware.
Description
Technical field
The present invention relates to computing technique field, more particularly, the present invention relates to a kind of CPU memory access sequence realistic model based on macro instruction queue.
Background technology
Along with the develop rapidly of semiconductor fabrication process, the dominant frequency of single core processor approaches the limit gradually, in order to improve the arithmetic speed of processor further, people form on-chip multi-processor (Chip Multi mono-Processor, CMP) on a single die by integrated for multiple processor core.
In CMP, shared the make contradiction of gaps between their growth rates processor and primary memory between of multiple processor core to single internal memory space is more outstanding, therefore CMP design must adopt multilevel cache (Cache), alleviates this contradiction by the storage organization of stratification.CMP system must solve the Cache consistency problem and consistency checking problem that cause therefrom.
Cache coherence protocol is as the important component part in polycaryon processor, and directly have influence on correctness design and the performance of polycaryon processor, Cache coherence protocol verification technique becomes one of the gordian technique in polycaryon processor design verification stage.
The checking of consistency protocol, needs a CPU model to emulate the memory access behavior of CPU, and real CPU model is very complicated.So, desirable to provide a kind of CPU memory access sequence realistic model that can simplify true CPU model when carrying out verifying consistency protocol.
Summary of the invention
Technical matters to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of CPU memory access sequence realistic model based on macro instruction queue that can simplify true CPU model when carrying out verifying consistency protocol.
According to the present invention, provide a kind of CPU memory access sequence realistic model based on macro instruction queue, it comprises: instruction buffer module, it comprise with the Cache of CPU inside not hit requests hang and cushion the identical multiple instruction buffers of number quantity, the instruction sent utilizes redundant field to carry the buffering number of place instruction buffer, to carry out Correctness checking according to this instruction buffer number of returning of response former state; Second-level cache and superseded buffer module, for simulating second-level cache and eliminating the operation cushioned, and check the legitimacy of secondary request and response; Secondary request processing module, for simulating the processing capacity to secondary request, receiving secondary request, and returning the response of respective type; Flow Control module, for simulating the Flow Control function of a request queue and response queue; Instruction scheduling module, performs for dispatching an instruction from multiple instruction buffer; Instruction decode module, for performing the conversion of instruction buffer order format to the form bag of the logic interfacing between CPU and consistency protocol hardware.
Preferably, load one group of instruction sequence in each instruction buffer, the instruction sequences of filling in instruction buffer module will meet the real behavior rule of CPU.
Preferably, load the instruction sequence that a group address has correlativity in each instruction buffer, the instruction in same instruction buffer, by serial transmission, just launches a rear instruction after only having last instruction to receive response.
Preferably, the instruction in each instruction buffer of instruction buffer module can circulate transmission.
Preferably, the instruction of different instruction buffer does not have address correlations, transmitted in parallel.
Preferably, test and excitation is configured to Random Test Stimulus or the special test and excitation of focus.
Preferably, Flow Control module is used for controlling, and makes when only having a response of once asking to return, and has the next one of address correlations once to ask to send from CPU.
Preferably, Flow Control module is used for controlling, if make in consistency protocol hardware logic request queue not have space, cpu instruction can not be launched.
Preferably, Flow Control module is used for controlling, if make the response queue of CPU inside not have space, then the response in consistency protocol hardware logic cannot return, and corresponding once request also cannot complete process.
Preferably, the time delay of secondary request process and response unloading can be configured to fixed value or random value, to simulate different congestion situations.
Thus, the invention provides a kind of CPU memory access sequence realistic model based on macro instruction queue that can simplify true CPU model when carrying out verifying consistency protocol.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows the CPU memory access sequence realistic model based on macro instruction queue according to the embodiment of the present invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
When carrying out verifying consistency protocol, the embodiment of the present invention constructs one based on the CPU simplified model of macro instruction queue, emulates the memory access behavior of CPU.
Be provided with multiple instruction buffer in this model, can fill in a request sequence of memory access in buffering according to testing requirement, the instruction sequence between multiple instruction buffer can be launched at random or according to appointment order.Whole model construction is comparatively simple, and manual compiling instruction sequence controls excitation, can carry out, specially to focus test, also can carrying out random test.
Further, the cpu instruction excitation relevant to consistency protocol only simulated by this model, and relative true CPU model, model is simple, and full software programming is more added with preferably can be handling, can test the various extreme cases of consistency protocol preferably.
Specifically, Fig. 1 schematically shows the CPU memory access sequence realistic model MODEL1 based on macro instruction queue by software simulating according to the embodiment of the present invention.The main body of this CPU memory access sequence realistic model MODEL1 is multiple instruction buffers, verifier can fill in different cpu instruction sequences according to testing requirement, wherein filled in instruction sequences will meet the real behavior rule of CPU, and the instruction sequence between multiple instruction buffer is random or launch according to appointment order by instruction scheduling.
Generally speaking, CPU and consistency protocol hardware logic have the bag of four kinds of different Virtual Channels mutual: once ask, the response of once asking, secondary request and secondary request response.In order to simulate the transmitting situation of cpu instruction really, CPU memory access sequence realistic model MODEL1 not only wants the transmitting of consistance request that is virtually reality like reality, also need to simulate consistency function relevant to consistency treatment parts in CPU, can jointly complete complete process flow to consistency protocol with consistency protocol hardware module H1 thus.
More particularly, as shown in Figure 1, comprise according to the CPU memory access sequence realistic model MODEL1 based on macro instruction queue of the embodiment of the present invention:
Instruction buffer module: comprise with the Cache of CPU inside not hit requests hang and cushion the identical instruction buffer of number quantity; Specifically, if hit requests hangs buffering number to the Cache of CPU inside is n, then instruction buffer number corresponding be set to n (the first instruction buffer 1, second instruction buffer 2 ... n-th instruction buffer n); Further, the instruction sequence that a group address is relevant in each instruction buffer, can be loaded, between the instruction of different buffering, there is not any address correlationship, can transmitted in parallel; Instruction random schedule between instruction buffer is launched, or launches according to appointment order.The complete serial transmission of instruction process in each instruction buffer, i.e. the response of previous instruction sends out next instruction after returning again.Executing instructions between instruction buffer.The transmission capable of circulation of each instruction buffer.The instruction sent utilizes redundant field to carry the buffering number of place instruction buffer, also can carry this instruction buffer number (that is, identical buffering number is carried in request and response thereof), carry out Correctness checking with this when response is returned.Further, the instruction sequences of filling in instruction buffer module will meet the real behavior rule of CPU.
Second-level cache and superseded buffer module M1: for simulating second-level cache and eliminating the operation cushioned, and the legitimacy of secondary request and response is checked; Specifically, some cpu instruction can cause second-level cache and eliminate the action of buffering, therefore needs to simulate correlation function, and checks the legitimacy of secondary request and response.
Secondary request processing module M2: some is once asked, consistency protocol can generate secondary request and mail to CPU, CPU should return response, the processing capacity of this module simulation to secondary request, receive secondary request, and return the response of respective type, make consistency treatment be able to complete carrying out.
Flow Control module M3: the Flow Control function simulating a request queue and response queue; Specifically, such as, Flow Control module M3 controls, and makes, when only having a response to return, to send the next instruction of identical address from CPU, and whether the instruction therefore in instruction buffer can launch the restriction of the request address be not yet disposed; In addition, Flow Control module M3 controls, if make a request queue in consistency protocol hardware logic H1 not have space, cpu instruction can not be launched; And Flow Control module M3 controls, if make the response queue of CPU inside not have space, then the response in consistency protocol hardware logic H1 cannot return, and corresponding once request also cannot complete process.
Instruction scheduling module M4: dispatch an instruction execution at random or according to appointment order from multiple instruction buffer; As mentioned above, the instruction in same instruction buffer is the instruction that address is relevant, is entirely serial and performs, an instruction after just performing after only having last instruction to receive response, the executing instructions between different instruction buffer.
Instruction decode module M5: be cpu instruction due to what fill in instruction buffer, and the process of consistency protocol hardware logic is consistency protocol bag, this module in charge completes the conversion of instruction buffer order format to the form bag of the logic interfacing between CPU and consistency protocol hardware, generates manageable once request of consistency protocol hardware logic and wraps.
Thus, according to the embodiment of the present invention based in the CPU memory access sequence realistic model MODEL1 of macro instruction queue, the process of secondary request processing module M2 secondary request can flexible configuration become fixed value also to can be configured to random value with the time delay of response unloading, to simulate different congestion situations, the test of multiple congestion situations can be realized thus.
And, according to the embodiment of the present invention based in the CPU memory access sequence realistic model MODEL1 of macro instruction queue, test and excitation can be configured to the special test and excitation of Random Test Stimulus and focus two kinds of patterns;
1. Random Test Stimulus: what fill in each instruction buffer is random excitation, specifically relative " at random ", the instruction sequences of namely filling in will meet the real behavior rule of CPU and the fill request of instruction buffer, some parameter of instruction can stochastic generation, instruction scheduling is arranged to dispatch command from different instruction buffer at random, and the instruction that so each change is filled in or change random pattern can obtain a different set of CPU arbitrary excitation;
2. the special test and excitation of focus: for some function point of hardware logic, fill in the instruction sequence of particular sequence or particular address in instruction buffer, the order of designated order scheduling, generates the specific instruction stream needed for verifier.
The test environment of single CPU or multi-CPU can be configured to easily according to the CPU memory access sequence realistic model MODEL1 based on macro instruction queue of the embodiment of the present invention.
Simply controlled according to the CPU memory access sequence realistic model MODEL1 based on macro instruction queue of the embodiment of the present invention, specifically, at the beginning of checking, verifier needs the content filled in instruction buffer, and after specifying the configuration parameters such as scheduling method, instruction stream needed for model can generate automatically, mail to consistency protocol hardware logic H1 process, in instruction stream processing procedure, if any behavior and expection repugnancy (instruction buffer respond instruction buffer that returns number and corresponding requests instruction place as certain is number inconsistent), can automatically report an error stops checking scene, otherwise can after instruction stream terminates check result, whole proof procedure does not need more human intervention.
Thus, as mentioned above, the above embodiment of the present invention provides a kind of CPU memory access sequence realistic model based on macro instruction queue that can simplify true CPU model when carrying out verifying consistency protocol.
In addition, it should be noted that, unless otherwise indicated, otherwise the term " first " in instructions, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in instructions, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1., based on a CPU memory access sequence realistic model for macro instruction queue, it is characterized in that comprising:
Instruction buffer module, it comprise with the Cache of CPU inside not hit requests hang and cushion the identical multiple instruction buffers of number quantity, the instruction sent utilizes superfluous She territory to carry the buffering number of place instruction buffer, to carry out Correctness checking according to this instruction buffer number of returning of response former state;
Second-level cache and superseded buffer module, for simulating second-level cache and eliminating the operation cushioned, and check the legitimacy of secondary request and response;
Secondary request processing module, for simulating the processing capacity to secondary request, receiving secondary request, and returning the response of respective type;
Flow Control module, for simulating the Flow Control function of a request queue and response queue;
Instruction scheduling module, performs for dispatching an instruction from multiple instruction buffer;
Instruction decode module, for performing the conversion of instruction buffer order format to the form bag of the logic interfacing between CPU and consistency protocol hardware, wherein
Load the instruction sequence that a group address is relevant in each instruction buffer, between the instruction of different buffering, there is not any address correlationship, transmitted in parallel; Instruction random schedule between instruction buffer is launched, or launch according to appointment order, the complete serial transmission of the instruction process in each instruction buffer, i.e. the response of previous instruction sends out next instruction after returning again, executing instructions between instruction buffer, each instruction buffer circulates transmission;
Flow Control module M3 controls, and makes, when only having a response to return, to send the next instruction of identical address from CPU, and whether the instruction therefore in instruction buffer can launch the restriction of the request address be not yet disposed; In addition, Flow Control module M3 controls, if make a request queue in consistency protocol hardware logic H1 not have space, cpu instruction can not be launched; And Flow Control module M3 controls, if make the response queue of CPU inside not have space, then the response in consistency protocol hardware logic H1 cannot return, and corresponding once request also cannot complete process;
Instruction scheduling module M4: dispatch an instruction execution at random or according to appointment order from multiple instruction buffer; As mentioned above, the instruction in same instruction buffer is the instruction that address is relevant, is entirely serial and performs, an instruction after just performing after only having last instruction to receive response, the executing instructions between different instruction buffer.
2. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1, is characterized in that, load one group of instruction sequence in each instruction buffer, and the instruction sequences of filling in instruction buffer module will meet the real behavior rule of CPU.
3. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, it is characterized in that, the instruction sequence that a group address has correlativity is loaded in each instruction buffer, instruction in same instruction buffer, by serial transmission, just launches a rear instruction after only having last instruction to receive response.
4. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, is characterized in that, the instruction cycles in each instruction buffer of instruction buffer module sends.
5. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, it is characterized in that, the instruction of different instruction buffer does not have address correlations, transmitted in parallel.
6. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, is characterized in that, test and excitation is configured to Random Test Stimulus or the special test and excitation of focus.
7. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, it is characterized in that, Flow Control module is used for controlling, and makes when only having a response of once asking to return, and has the next one of address correlations once to ask to send from CPU.
8. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, it is characterized in that, Flow Control module is used for controlling, if make in consistency protocol hardware logic request queue not have space, cpu instruction can not be launched.
9. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, it is characterized in that, Flow Control module is used for controlling, if make the response queue of CPU inside there is no space, response then in consistency protocol hardware logic cannot return, and corresponding once request also cannot complete process.
10. the CPU memory access sequence realistic model based on macro instruction queue according to claim 1 and 2, it is characterized in that, the time delay of secondary request process and response unloading is configured to fixed value or random value, to simulate different congestion situations by secondary request processing module.
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| US7650273B2 (en) * | 2005-09-21 | 2010-01-19 | Intel Corporation | Performance simulation of multiprocessor systems |
| JP2008186233A (en) * | 2007-01-30 | 2008-08-14 | Toshiba Corp | Instruction cache pre-fetch control method and device thereof |
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