CN102880568A - State tracking device for multi-core processor - Google Patents
State tracking device for multi-core processor Download PDFInfo
- Publication number
- CN102880568A CN102880568A CN2012103466786A CN201210346678A CN102880568A CN 102880568 A CN102880568 A CN 102880568A CN 2012103466786 A CN2012103466786 A CN 2012103466786A CN 201210346678 A CN201210346678 A CN 201210346678A CN 102880568 A CN102880568 A CN 102880568A
- Authority
- CN
- China
- Prior art keywords
- bus
- subelement
- tracking
- unit
- debugging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims abstract description 25
- 238000004891 communication Methods 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 10
- 238000001914 filtration Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 48
- 230000008569 process Effects 0.000 claims description 48
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000004148 unit process Methods 0.000 claims description 5
- 238000002224 dissection Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Images
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a state tracking device for a multi-core processor, which comprises a tracking bus interface unit, a tracking bus, a tracking control unit, and a debugging interface unit. The tracking bus interface unit is used for converting an access signal on a bus and to a storage device in the processor into a form that can be received by the corresponding storage device, and is used for converting a response signal of the storage device into a form that can be received by the bus ; the tracking bus is used for providing a communication channel and connecting the tracking bus interface unit, the tracking control unit and the debugging interface unit; the tracking control unit is used for receiving and saving debugging tracking orders inputted by an external debug host, filtering away invalid debugging tracking orders, analyzing and processing valid debugging tracking orders to send an access request to the storage device in the processor, initializing the debugging interface unit, and outputting accessed data; and the debugging interface unit is used for transmitting the debugging tracking orders from the debug host and transmitting the data request by the debug host to the debug host. The state tracking device has the advantages of good observation ability, convenience in operation and good expansibility.
Description
Technical field
The present invention relates to debugging and the tracking field of processor, especially a kind of polycaryon processor status tracking device.
Background technology
Along with the performance of modern polycaryon processor improves constantly, its scale is also in continuous increase, and complexity is also in continuous enhancing.In order to have given play to the peak performance of processor hardware, also increasingly sophisticated towards operating system and the software of multi-core platform.This is so that the system debug under multi-core environment and follow the tracks of more complex and difficulty, because multiple nucleus system exists some its distinctive characteristics, for example concurrency of cache coherence problem, TLB consistency problem, software etc.In multi-core environment, debug, also have internuclear stationary problem.
The debugging tracking module of processor all is to adopt jtag interface basically at present, configures the register of debugging in the tracking module by scan chain input debugging trace command, thus the work of control debugging tracking module.Then the instruction that can carry out by the scan chain input processor visits register and memory device in the processor by allowing processor carry out these instructions in the register of debugging tracking module.The debugging tracking module is not register and the memory device in the direct access processor, visit register and memory device but indirectly carry out instruction by processor, this can make a large amount of data of access become slow on the one hand, the execution of debugging on the other hand trace command might affect the state of processor, so that the commissioning staff becomes more difficult to the analysis of system.
Present polycaryon processor debugging tracking module often only provides the ability of access register and internal memory, and the ability of access cache and other important nuclear internal memory devices is not provided.This has increased the difficulty of system debug, because in this case, we can only come by the value of variable in register or the internal memory ruuning situation of state and the software of decision processor.But it is very difficult only coming the state of analysis processor and the ruuning situation of software by the value of variable in register and the internal memory in multiple nucleus system, in some situation or even can't realize.Because in multiple nucleus system, the state of the state of processor, the ruuning situation of software and the state of high-speed cache, maintaining cached conforming module and safeguard that the state of internuclear module of communicating by letter is closely-related.
In addition, it all is to communicate by letter with the debugging tracking module in the multiple nucleus system by jtag interface basically that Software tool is followed the tracks of in existing debugging, follow the tracks of above-mentioned these functions of increase in the software if want in existing debugging, need to revise existing debugging and follow the tracks of software, the therein corresponding debugging of adding trace command, and need the existing debugging tracking of modification hardware module to support these functions and order.After these were revised, the designer had to existing mature and stable Software tool and hardware module re-started checking.
Summary of the invention
, troublesome poeration relatively poor for the observation ability that overcomes existing polycaryon processor status tracking technology, the relatively poor deficiency of extendability the invention provides the polycaryon processor status tracking device that a kind of observation ability is good, easy to operate, extendability is good.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of polycaryon processor status tracking device, described tracking means comprises: follow the tracks of Bus Interface Unit, be used for the interrogation signal to the processor internal storage device on the bus is converted to the form that corresponding memory device can receive, and the response signal of memory device is converted to the form that bus can receive; Follow the tracks of bus, be used for providing communication port, connect and follow the tracks of Bus Interface Unit, tracking control module and debug interface unit; Follow the tracks of control module, be used for receiving the debugging trace command of preserving from extraneous debug host input, filter invalid debugging trace command; Dissection process is effectively debugged trace command, and the memory device in polycaryon processor is initiated request of access; The initialization debug interface unit; The data that output access is arrived; Debug interface unit is used for transmission from the debugging trace command of debug host, and with the data transmission of debug host request to debug host.
Further, described tracking control module comprises: order receives subelement, is used for reception and preserves debug host by the debugging trace command of debug interface unit input; The command process subelement, be used for resolving and processing debugging trace command, this unit drives corresponding control signal and visits resource in the polycaryon processor to following the tracks of according to different orders on the bus, and in needs the data communication device that has access to is crossed debug interface unit and export to extraneous debug host; Debugging interface initialization subelement is used for the initialization debug interface unit; The output subelement is used for that the data communication device that the command process subelement has access to is crossed debug interface unit and outputs to extraneous debug host; Main device bus interface subelement is that described order receives subelement, command process subelement, debugging interface initialization subelement, output subelement and follows the tracks of interface between the bus, is used for order is received subelement, command process subelement, debugging interface initialization subelement, output subelement are converted to standard to following the tracks of the signal that conducts interviews from equipment on the bus tracking bus interface signal.
Further, described order receives in the subelement, has the function of filtering invalid command, and when namely only having the debugging trace command of input to be effective order, order receives subelement and just understands notification command and process subelement and process this order; These orders are comprised of character, and it can be unit by character that order receives subelement, and reception one by one is from the character of debug host input, and the order that its composition is complete, and the process that receives order is controlled by a finite state machine;
In the described output subelement, in the process of output data, the output subelement need to be take character as unit, and a character connects the output of a character, and the work of this unit is controlled by a finite state machine.
Described tracking Bus Interface Unit comprises:
From the device bus interface subelement, be used for the interrogation signal to the polycaryon processor internal storage device on the bus is converted to the form that corresponding memory device can receive, and the response signal of memory device is converted to the form that bus can receive;
The first multi-channel gating device is used for the selection signal according to the address decoder generation, and the request of access signal since the device bus interface subelement is routed on the corresponding nuclear internal memory devices in the future;
The second multi-channel gating device is used for the selection signal according to the address decoder generation, selects effective response signal and return to from the device bus interface subelement from the response signal from a plurality of nuclear internal memory devices;
Address decoder is used for the address according to access, produces the selection signal to the nuclear internal memory devices, for the first multi-channel gating device and the second multi-channel gating device.
Described tracking bus is ahb bus.Certainly, also can select the other types bus.
Described debug interface unit is the UART unit, and described UART unit is connected with the APB bus, and described APB bus is connected with described ahb bus.Certainly, debug interface unit also can adopt other interface types.
Technical conceive of the present invention is: the ahb bus by standard visits the resource in the polycaryon processor, these resources as from equipment connection on ahb bus, control module is followed the tracks of in debugging to be connected on the ahb bus as main equipment, debugging on the outside debug host is followed the tracks of software and is sent the debugging trace command by a non-jtag interface to debugging tracking control module, debugging follow the tracks of control module receive orders just go to access on the ahb bus from equipment, be the various storeies in the polycaryon processor, then debugging is followed the tracks of control module and is followed the tracks of software by the debugging that this non-jtag interface is exported to data on the debug host again.
For the Commissioning Analysis that makes multiple nucleus system more convenient and easy, the debugging tracking module should be under the prerequisite that does not affect processor state, the ability that the important memory device in direct access cache, the maintaining cached conforming module is provided and safeguards the important memory device in the module of internuclear communication.This also is main contents of the present invention.
Beneficial effect of the present invention is: strengthened commissioning staff's observation ability to system state when the debugging multiple nucleus system, the ability of memory device important in the read-write multiple nucleus system is provided, made the commissioning staff convenient and accurate to the analysis of system.
The present invention has adopted independent interface to follow the tracks of software as debugging and the passage of communicating by letter between the hardware module is followed the tracks of in debugging, thereby has avoided existing debugging tracking software and debugging are followed the tracks of the modification of hardware module and again checking.
The present invention also has good extendability, if need other memory devices in the access multiple nucleus system, can expand easily.
Description of drawings
Fig. 1 is the structured flowchart of polycaryon processor status tracking device provided by the invention.
Fig. 2 is the structured flowchart of the tracking control module in the polycaryon processor status tracking device provided by the invention.
Fig. 3 is the workflow diagram that the order in the polycaryon processor status tracking device provided by the invention receives subelement.
Fig. 4 is the workflow diagram of the command process subelement in the polycaryon processor status tracking device provided by the invention.
Fig. 5 is the workflow diagram of the output subelement in the polycaryon processor status tracking device provided by the invention.
Fig. 6 is the structured flowchart of the tracking Bus Interface Unit in the polycaryon processor status tracking device provided by the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is further described in detail, in order to make the purpose, technical solutions and advantages of the present invention clearer.
With reference to Fig. 1 ~ Fig. 6, a kind of polycaryon processor status tracking device, this device comprises five parts, is respectively: UART unit, APB bus, tracking control module, tracking Bus Interface Unit and ahb bus.
To be described polycaryon processor status tracking device follow the tracks of the passage of software communication with the debugging on the debugging main frame in described UART unit, comprises transmission from the debugging trace command of debug host, and with the data transmission of debug host request on debug host.These communications are carried out take single character as unit, are take character as the unit input command because software is followed the tracks of in the debugging on the debug host, also show data take character as unit.
Described APB bus is used for connecting UART unit and ahb bus, is the passage of communicating by letter between other unit among described UART unit and the present invention.
Use the UART interface to follow the tracks of the interface of communicating by letter between the hardware module as debug host and debugging among the present invention, therefore need the APB bus that other unit among UART unit and the present invention are linked together.But the interface that also can use as required other is followed the tracks of communication interface between the hardware module as debug host and debugging, and only need to replace with corresponding interface with described UART unit and described APB bus and get final product this moment.This characteristic has strengthened adaptability of the present invention.
The major function of described tracking control module has: receive the debugging trace command of preserving from extraneous debug host input, filter invalid debugging trace command; Dissection process is effectively debugged trace command, and the memory device in polycaryon processor is initiated request of access; The described UART module of initialization; The data that output access is arrived.
Described tracking Bus Interface Unit is the interface between the various memory devices of ahb bus and polycaryon processor inside, this unit is used for the interrogation signal to the processor internal storage device on the bus is converted to the form that corresponding memory device can receive, and the response signal of memory device is converted to the form that bus can receive.This unit also needs the access control signal from ahb bus is routed on the corresponding nuclear internal memory devices, and selects effective response signal return to ahb bus from the response signal from a plurality of nuclear internal memory devices.
Described ahb bus is used for connecting follows the tracks of control module, tracking Bus Interface Unit and APB bus, is the passage of communicating by letter between its all parts that connects.Adopted ahb bus among the present invention, but also can adopt as required other bus, for example the AXI bus.
Described tracking control module comprises again five parts, is respectively: order receives subelement, command process subelement, UART initialization subelement, output subelement and main equipment and sums up the interface subelement;
Described order receives subelement, be used for receiving and preserving the debugging trace command that debug host is inputted by the UART interface, and having the function of filtering invalid command, when namely only having the debugging trace command of input to be effective order, the order receiving element is just understood this order of notification command processing unit processes.These orders are comprised of character, and the order receiving element can be unit by character, and reception one by one is from the character of debug host input, and the order that its composition is complete.The process that receives order is controlled by a finite state machine.
Described command process subelement is used for resolving and processing debugging trace command.This unit drives corresponding control signal on the ahb bus according to different orders and visits resource in the polycaryon processor.And in needs, the data communication device that has access to is crossed the UART interface and export to extraneous debug host.The process of processing command is controlled by a finite state machine.
Described UART initialization subelement is used for initialization UART unit.In described polycaryon processor status tracking device, there is not other ahb bus main equipment to come the described UART of initialization unit, therefore adopt an independent module to come the described UART of initialization unit here, make the UART unit can with the debug host in the external world on debugging follow the tracks of software and inner hardware module collaborative work.The work of this unit is controlled by a finite state machine.
Described output subelement is used for that the data communication device that described command process subelement has access to is crossed the UART interface and outputs to extraneous debug host.In the process of output data, output unit need to be take character as unit, and a character connects the output of a character.The work of this unit is controlled by a finite state machine.
Described main device bus interface subelement is that described order receives the interface between subelement, described command process subelement, described UART initialization subelement and described output subelement and the ahb bus, is used for order is received subelement, described command process subelement, described UART initialization subelement and described output subelement are converted to standard to the signal that conducts interviews from equipment on the ahb bus ahb bus interface signal.
Described tracking Bus Interface Unit is the interface between the various memory devices of ahb bus and polycaryon processor inside.This unit comprises again four parts, is respectively: from the device bus interface subelement, and the first multi-channel gating device, the second multi-channel gating device and address decoder.
Describedly be used for the interrogation signal to the polycaryon processor internal storage device on the bus is converted to the form that corresponding memory device can receive from the device bus interface subelement, and the response signal of memory device is converted to the form that bus can receive.This unit is with good expansibility the present invention, if need to observe other memory devices in the multiple nucleus system, only needs this unit of expansion and connect this equipment to get final product.
The selection signal that described the first multi-channel gating device produces according to address decoder, the request of access signal since the device bus interface unit is routed on the corresponding nuclear internal memory devices in the future.
Described the second multi-channel gating device is selected effective response signal and is returned to from the device bus interface unit according to the selection signal that address decoder produces from the response signal from a plurality of nuclear internal memory devices.
Described address decoder produces the selection signal to the nuclear internal memory devices, for the first multi-channel gating device and the second multi-channel gating device according to the address of access.
Fig. 1 is the structured flowchart of polycaryon processor status tracking device provided by the invention.The job step of unit is in this device:
The first step: following the tracks of control module can carry out initialization to the UART unit system reset after, comprises the control register that baud rate, configuration UART are set, make the UART unit can with debugging tracking software and the present invention in other unit collaborative works.
Second step: this device is in idle condition, waits for the debugging trace command from debug host.
The 3rd step: debug host is debugged trace command as communication port to described polycaryon processor status tracking device input with the UART unit.Effectively the debugging trace command comprises:
1. read the data-carrier store of the high-speed cache in certain nuclear.
2. read the tag ram of the high-speed cache in certain nuclear.
3. read the data mode storer of certain nuclear in the maintaining cached consistance module.
4. write the data-carrier store of the high-speed cache in certain nuclear.
5. write the tag ram of the high-speed cache in certain nuclear.
6. write the data mode storer of certain nuclear in the maintaining cached consistance module.
But effectively order is not limited to these above-mentioned orders, when reality is used, can be according to the demand of oneself, and add new order and visit other memory devices in the processor.
The 4th step: follow the tracks of control module and receive the debugging trace command of also preserving from extraneous debug host input, judge that whether order is effective, abandons invalid order afterwards the order input is complete.
The 5th step: follow the tracks of control module effective order is resolved and processed.Initiate access according to different orders to certain memory device in the polycaryon processor, be about to suitable control signal and be driven on the ahb bus.Follow the tracks of Bus Interface Unit after the control signal that receives on the ahb bus, these control signals are converted to the request of access signal that the memory device in the polycaryon processor can receive, and this request of access signal is routed on the corresponding nuclear internal memory devices, write new data in this equipment or from sense data wherein.
The 6th step: if the debugging trace command is write order, then need not carry out this step.If the debugging trace command is read command, follow the tracks of Bus Interface Unit and can from the response signal from a plurality of nuclear internal memory devices, select effective response signal, after this response signal being converted to the form that bus can receive, return to ahb bus.Follow the tracks of after the response signal of control module on monitoring ahb bus, again data message is wherein outputed on the debug host by the UART unit.Execute after this step, the present invention will return second step, so move in circles.
Fig. 2 is the structured flowchart of the tracking control module in the polycaryon processor status tracking device provided by the invention.Described tracking control module comprises again five parts, is respectively: order receives subelement, command process subelement, UART initialization subelement, output subelement and main equipment and sums up the interface subelement;
Described order receives subelement and is used for receiving and preserving the debugging trace command that debug host is passed through the input of UART interface, and has a function of filtering invalid command, when namely only having the debugging trace command of input to be effective order, order receives subelement and just understands this order of notification command processing unit processes.These orders are comprised of character, and order receives subelement needs a character to connect the reception order of a character.The worker state machine that described order receives subelement as shown in Figure 3, its job step is:
The first step: order receives subelement and is in idle condition.If UART did not carry out initialization in the unit, this moment can not work in the UART unit, and extraneous debug host can't be inputted the debugging trace command, and the order receiving element just is in idle condition always.
Second step: complete when the initialization of UART unit, the order receiving element changes query State over to.At this state, the order receiving element can be inquired about a register in the UART unit always, this register is indicating the character whether the UART unit has received the input of extraneous debug host, if extraneous debug host input character not, the order receiving element just is in query State always.
The 3rd step: inputted significant character when order reception subelement inquires extraneous debug host, the order receiving element just changes the character state of reading over to.At this state, the character that the order receiving element can receive the UART unit reads in own one group of inner register to be preserved, so that the back is resolved and processed order.
If order does not finish, just repeat second step and the 3rd step, until the order input is complete.
The 4th step: it is invalid to order if order finishes, and the order receiving element abandons and change over to idle condition with this invalid command, restarts operation from the first step, does not rerun for the 5th step.
The 5th step: if order finishes and be effectively, the order receiving element changes treatment state over to.At this state, the order of order receiving element meeting notification command processing unit processes, and this order of wait command processing unit processes.Until command process is complete, the order receiving element changes idle condition over to, restarts operation from the first step.
Described command process subelement is used for resolving and processes and debug trace command.This unit drives corresponding control signal on the bus according to different orders and visits resource in the polycaryon processor.And in needs, the data communication device that has access to is crossed the UART interface and export to extraneous debug host.The worker state machine of this unit as shown in Figure 4, its job step is:
The first step: the command process unit is in idle condition.At this state, the command process unit is waited for needs order to be processed, if order does not need to process, this unit will be in idle condition always.
Second step: when there being order to need to process, the command process unit changes Access status over to.At this state, the command process unit can be driven into control signal on the ahb bus by the main device bus interface unit, thus the storer of access debugging trace command appointment.If a write order, the command process unit can write corresponding storer with data at this state; If a read command, the command process unit can be at this state from corresponding storer readback data.
The 3rd step: if a write order, the command process unit will change idle condition over to.If a read command, command processor will change output state over to.At output state, the command process unit will output to extraneous debug host with the data of reading back by output unit.
The 4th step: if read operation is complete, the command process unit will change idle condition over to.If it is complete that read operation does not also have, namely also need to read other address, the command process unit will change Access status over to, repeat second step, the 3rd step and the 4th step, until read operation is complete.
Described UART initialization subelement is used for initialization UART unit, comprises the control register that baud rate, configuration UART are set, and makes the UART unit follow the tracks of other unit collaborative works among software and the present invention with debugging.In described polycaryon processor status tracking device, there is not other bus master to come the described UART of initialization unit, therefore adopt an independent unit to come the described UART of initialization unit here, make the UART unit can with the debug host in the external world on debugging follow the tracks of software collaboration work.
Described output subelement be used for described command process unit access to data communication device cross the UART interface and output to extraneous debug host.The worker state machine of this unit as shown in Figure 5, its job step is:
The first step: output unit is in idle condition, waits for the output data from the command process unit.If the command process unit does not have data to need output, then output unit is in idle condition always.
Second step: when the command process unit had data to export, output unit changed query State over to.At query State, output unit can be inquired about a register in the UART unit always, and whether this register is indicating the UART unit can receive character, if the UART unit can not receive character, this output unit is in query State always.
The 3rd step: when UART can receive character, output unit changed the output character state over to.At the output character state, a character in the data that output unit can will need to export by UART outputs on the extraneous debug host.
The 4th step: if all characters in the data have all outputed on the extraneous debug host, output unit changes idle condition over to.If it is complete that data are not also exported, output unit just changes query State over to, repeats second step, the 3rd step and the 4th step, until all characters have all outputed on the extraneous debug host.
Described main device bus interface subelement is that described order receives the interface between subelement, described command process subelement, described UART initialization subelement and described output subelement and the ahb bus, is used for order is received subelement, described command process subelement, described UART initialization subelement and described output subelement are converted to standard to the signal that conducts interviews from equipment on the ahb bus ahb bus interface signal.
Fig. 6 is the structured flowchart of the tracking Bus Interface Unit in the polycaryon processor status tracking device provided by the invention.Described tracking Bus Interface Unit is the interface between the various memory devices of ahb bus and polycaryon processor inside, this unit comprises again four parts, be respectively: from the device bus interface subelement, the first multi-channel gating device, the second multi-channel gating device and address decoder.
Describedly be used for the interrogation signal to the polycaryon processor internal storage device on the ahb bus is converted to the form that corresponding memory device can receive from the device bus interface subelement, and the response signal of memory device is converted to the form that bus can receive.The memory device of these polycaryon processor inside comprises:
1. the data-carrier store of the high-speed cache during each is examined.
2. the tag ram of the high-speed cache during each is examined.
3. the data mode storer of each nuclear in the maintaining cached consistance module.
But the memory device of polycaryon processor inside is not limited to above-mentioned equipment, in needs, can increase other equipment.
The selection signal that described the first multi-channel gating device produces according to address decoder, the request signal since the device bus interface unit is routed on the corresponding nuclear internal memory devices in the future.
Described the second multi-channel gating device is selected effective response signal and is returned to from the device bus interface unit according to the selection signal that address decoder produces from the response signal from a plurality of nuclear internal memory devices.
Described address decoder produces the selection signal to the nuclear internal memory devices, for the first multi-channel gating device and the second multi-channel gating device according to the address of access.
The job step of described tracking Bus Interface Unit is:
The first step: the access control signal on from the device bus interface unit inspection to ahb bus just is converted to this access control signal the request of access signal that the nuclear internal memory devices can receive.
Second step: the address signal in the address decoder request signal produces the selection signal to the nuclear internal memory devices.The first multi-channel gating device is according to selecting signal, and the request of access signal since the device bus interface unit is routed on the corresponding nuclear internal memory devices in the future, and memory device is carried out read or write.
The 3rd step: the selection signal that the second multi-channel gating device produces according to address decoder, from the response signal from a plurality of nuclear internal memory devices, select effective response signal and return to from the device bus interface unit, this response signal is converted to form that ahb bus can receive from the device bus interface unit and it is driven on the ahb bus.
Above explanation only is a specific embodiment of the present invention, is not limited to the present invention, and is all in basic thought of the present invention and the modification of doing in principle, replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. polycaryon processor status tracking device, it is characterized in that: described tracking means comprises:
Follow the tracks of Bus Interface Unit, be used for the interrogation signal to the processor internal storage device on the bus is converted to the form that corresponding memory device can receive, and the response signal of memory device is converted to the form that bus can receive;
Follow the tracks of bus, be used for providing communication port, connect and follow the tracks of Bus Interface Unit, tracking control module and debug interface unit;
Follow the tracks of control module, be used for receiving the debugging trace command of preserving from extraneous debug host input, filter invalid debugging trace command; Dissection process is effectively debugged trace command, and the memory device in polycaryon processor is initiated request of access; The initialization debug interface unit; The data that output access is arrived;
Debug interface unit is used for transmission from the debugging trace command of debug host, and with the data transmission of debug host request to debug host.
2. polycaryon processor status tracking device as claimed in claim 1, it is characterized in that: described tracking control module comprises:
Order receives subelement, is used for reception and preserves debug host by the debugging trace command of debug interface unit input;
The command process subelement, be used for resolving and processing debugging trace command, this unit drives corresponding control signal and visits resource in the polycaryon processor to following the tracks of according to different orders on the bus, and in needs the data communication device that has access to is crossed debug interface unit and export to extraneous debug host;
Debugging interface initialization subelement is used for the initialization debug interface unit;
The output subelement is used for that the data communication device that the command process subelement has access to is crossed debug interface unit and outputs to extraneous debug host;
Main device bus interface subelement is that described order receives subelement, command process subelement, debugging interface initialization subelement, output subelement and follows the tracks of interface between the bus, is used for order is received subelement, command process subelement, debugging interface initialization subelement, output subelement are converted to standard to following the tracks of the signal that conducts interviews from equipment on the bus tracking bus interface signal.
3. polycaryon processor status tracking device as claimed in claim 2, it is characterized in that: described order receives in the subelement, have the function of filtering invalid command, when namely only having the debugging trace command of input to be effective order, the order receiving element is just understood this order of notification command processing unit processes; These orders are comprised of character, and the order receiving element can be unit by character, and reception one by one is from the character of debug host input, and the order that its composition is complete, and the process that receives order is controlled by a finite state machine;
In the described output subelement, in the process of output data, output unit need to be take character as unit, and a character connects the output of a character, and the work of this unit is controlled by a finite state machine.
4. such as the described polycaryon processor status tracking of one of claim 1 ~ 3 device, it is characterized in that: described tracking Bus Interface Unit comprises:
From the device bus interface subelement, be used for the interrogation signal to the polycaryon processor internal storage device on the bus is converted to the form that corresponding memory device can receive, and the response signal of memory device is converted to the form that bus can receive;
The first multi-channel gating device is used for the selection signal according to the address decoder generation, and the request of access signal since the device bus interface unit is routed on the corresponding nuclear internal memory devices in the future;
The second multi-channel gating device is used for the selection signal according to the address decoder generation, selects effective response signal and return to from the device bus interface unit from the response signal from a plurality of nuclear internal memory devices;
Address decoder is used for the address according to access, produces the selection signal to the nuclear internal memory devices, for the first multi-channel gating device and the second multi-channel gating device.
5. such as the described polycaryon processor status tracking of one of claim 1 ~ 3 device, it is characterized in that: described tracking bus is ahb bus.
6. polycaryon processor status tracking device as claimed in claim 5, it is characterized in that: described debug interface unit is the UART unit, and described UART unit is connected with the APB bus, and described APB bus is connected with described ahb bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103466786A CN102880568A (en) | 2012-09-18 | 2012-09-18 | State tracking device for multi-core processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103466786A CN102880568A (en) | 2012-09-18 | 2012-09-18 | State tracking device for multi-core processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102880568A true CN102880568A (en) | 2013-01-16 |
Family
ID=47481899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103466786A Pending CN102880568A (en) | 2012-09-18 | 2012-09-18 | State tracking device for multi-core processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102880568A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105389235A (en) * | 2015-10-28 | 2016-03-09 | 致象尔微电子科技（上海）有限公司 | Heterogeneous multi-core debug system and method |
| CN110134640A (en) * | 2018-02-09 | 2019-08-16 | 上海中研久弋科技有限公司 | Multi-core sensing data handles chip and operation method |
| CN111427826A (en) * | 2020-06-11 | 2020-07-17 | 杭州万高科技股份有限公司 | Heterogeneous multi-core processor with bus connection adjustment function |
| CN112486752A (en) * | 2020-12-18 | 2021-03-12 | 时擎智能科技(上海)有限公司 | Processor tracking system, method, storage medium and terminal |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556558A (en) * | 2008-04-08 | 2009-10-14 | 株式会社瑞萨科技 | Information processing device |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
-
2012
- 2012-09-18 CN CN2012103466786A patent/CN102880568A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101556558A (en) * | 2008-04-08 | 2009-10-14 | 株式会社瑞萨科技 | Information processing device |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
Non-Patent Citations (1)
| Title |
|---|
| ALAN P. SU: "《A Multi-core Software/Hardware Co-debug Platform with ARM CoreSightTM,On-chip Test Architecture and AXI/AHB Bus Monitor》", 《VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2011 INTERNATIONAL SYMPOSIUM ON》, 31 December 2011 (2011-12-31), pages 129 - 136 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105389235A (en) * | 2015-10-28 | 2016-03-09 | 致象尔微电子科技（上海）有限公司 | Heterogeneous multi-core debug system and method |
| CN110134640A (en) * | 2018-02-09 | 2019-08-16 | 上海中研久弋科技有限公司 | Multi-core sensing data handles chip and operation method |
| CN110134640B (en) * | 2018-02-09 | 2024-03-01 | 上海中研久弋科技有限公司 | Multi-core sensor data processing chip and operation method |
| CN111427826A (en) * | 2020-06-11 | 2020-07-17 | 杭州万高科技股份有限公司 | Heterogeneous multi-core processor with bus connection adjustment function |
| CN112486752A (en) * | 2020-12-18 | 2021-03-12 | 时擎智能科技(上海)有限公司 | Processor tracking system, method, storage medium and terminal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100565472C (en) | A kind of adjustment method that is applicable to multiprocessor karyonide system chip | |
| CN101529391B (en) | Performing diagnostic operations upon an asymmetric multiprocessor apparatus | |
| CN103309786B (en) | For non-can the method and apparatus of interactive debug in preemptive type Graphics Processing Unit | |
| CN101458725B (en) | Microcontroller chip and debug method thereof | |
| CN104461970B (en) | Dma controller, mobile terminal and data method for carrying | |
| CN100476650C (en) | SCM memory system | |
| CN101278293A (en) | Performance simulation of multiprocessor systems | |
| CN102880568A (en) | State tracking device for multi-core processor | |
| EP2838024B1 (en) | Cache debug system for programmable circuits | |
| Koehler et al. | Performance analysis challenges and framework for high-performance reconfigurable computing | |
| CN107255961B (en) | A wireless intelligent oscilloscope for efficient data interaction | |
| JP5756554B2 (en) | Semiconductor device | |
| Ye et al. | SimICT: A fast and flexible framework for performance and power evaluation of large-scale architecture | |
| US8275954B2 (en) | Using DMA for copying performance counter data to memory | |
| US20130007398A1 (en) | Device and method for exchanging data between memory controllers | |
| CN110727611B (en) | Configurable consistency verification system with state monitoring function | |
| CN100371907C (en) | Tracing debugging method and system for processor | |
| CN109100440A (en) | On-line chromatograph control analysis system and its application method based on network server | |
| CN116757132A (en) | Heterogeneous multi-core FPGA circuit architecture, construction method and data transmission method | |
| CN101621549B (en) | LonWorks node multi-I/O device based on nerve cell chip | |
| Delange et al. | Design and analysis of multi-core architecture for cyber-physical systems | |
| CN205594346U (en) | Real -time data assists analytic system based on RTX | |
| CN111444102A (en) | An offline computing engine testing method and system | |
| Faes et al. | FPGA-aware garbage collection in Java | |
| CN113672554B (en) | Processor core, processor, system on chip and debug system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130116 |