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CN102867814A - Chip packaging body - Google Patents

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Publication number
CN102867814A
CN102867814A CN2011101881347A CN201110188134A CN102867814A CN 102867814 A CN102867814 A CN 102867814A CN 2011101881347 A CN2011101881347 A CN 2011101881347A CN 201110188134 A CN201110188134 A CN 201110188134A CN 102867814 A CN102867814 A CN 102867814A
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CN
China
Prior art keywords
chip
layer
top surface
chip package
metal bottom
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Pending
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CN2011101881347A
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Chinese (zh)
Inventor
吴开文
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN2011101881347A priority Critical patent/CN102867814A/en
Publication of CN102867814A publication Critical patent/CN102867814A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本发明涉及一种芯片封装体，其包括电路板、芯片及导线。该电路板包括金属底层、形成在该金属底层的中间层及形成在该中间层的导电线路层，该金属底层用于连接地端，该芯片封装体开设有贯穿该导电线路层及该中间层的通孔以暴露该金属底层，该芯片置于该通孔内且位于该金属底层上，该芯片与该金属底层相互绝缘，该导线连接该芯片及该导电线路层。

Figure 201110188134

The invention relates to a chip packaging body, which includes a circuit board, a chip and wires. The circuit board includes a metal bottom layer, an intermediate layer formed on the metal bottom layer, and a conductive circuit layer formed on the intermediate layer. The metal bottom layer is used to connect to the ground terminal. The through hole is used to expose the metal bottom layer, the chip is placed in the through hole and on the metal bottom layer, the chip and the metal bottom layer are insulated from each other, and the wire is connected to the chip and the conductive circuit layer.

Figure 201110188134

Description

芯片封装体chip package

技术领域 technical field

本发明涉及一种芯片封装体。 The invention relates to a chip packaging body.

背景技术 Background technique

一般地，芯片封装体包括芯片、电路板及其它电子组件。将芯片与电路板或其它组件达成电连接的方法包括打线接合(wire bonding)。在这方法中，金线或铝线等材质的金属线会被作为导线使用。这些金属线的等效电路为电感。电感效应（特别是当操作在高频时电感效应会特别显著）会影响电路特性，使电路阻抗难以匹配，并增加信号损耗。 Generally, a chip package includes a chip, a circuit board, and other electronic components. Methods for electrically connecting chips to circuit boards or other components include wire bonding. In this method, metal wires such as gold wires or aluminum wires are used as wires. The equivalent circuit of these metal lines is an inductor. Inductive effects, especially when operating at high frequencies, can affect circuit characteristics, making circuit impedance matching difficult and increasing signal loss.

发明内容 Contents of the invention

有鉴于此，有必要提供一种可降低电感效应的芯片封装体，以使电路阻抗容易匹配，并减少信号损耗。 In view of this, it is necessary to provide a chip package that can reduce the inductance effect, so as to easily match the circuit impedance and reduce signal loss.

一种芯片封装体，其包括电路板、芯片及导线。该电路板包括金属底层、形成在该金属底层的中间层及形成在该中间层的导电线路层，该金属底层用于连接地端，该芯片封装体开设有贯穿该导电线路层及该中间层的通孔以暴露该金属底层，该芯片置于该通孔内且位于该金属底层上，该芯片与该金属底层相互绝缘，该导线连接该芯片及该导电线路层。 A chip packaging body, which includes a circuit board, a chip and wires. The circuit board includes a metal bottom layer, an intermediate layer formed on the metal bottom layer, and a conductive circuit layer formed on the intermediate layer. The metal bottom layer is used to connect to the ground terminal. The through hole is used to expose the metal bottom layer, the chip is placed in the through hole and on the metal bottom layer, the chip and the metal bottom layer are insulated from each other, and the wire is connected to the chip and the conductive circuit layer.

本发明提供的芯片封装体，将芯片置于该通孔内且位于该金属底层上，使芯片相对于导电线路层的高度降低，进而使得连接芯片与导电线路层的导线变短，因此可降低导线的等效电感值而降低导线的电感效应而使得电路阻抗容易匹配并减少信号损耗，同时也可以减少导线的使用，节约成本。 In the chip package provided by the present invention, the chip is placed in the through hole and on the metal bottom layer, so that the height of the chip relative to the conductive circuit layer is reduced, and the wires connecting the chip and the conductive circuit layer are shortened, so that the chip can be reduced. The equivalent inductance value of the wire reduces the inductance effect of the wire, which makes the circuit impedance easy to match and reduces signal loss. At the same time, it can also reduce the use of wires and save costs.

附图说明 Description of drawings

图1为本发明第一实施方式提供的一种具有封装玻璃的芯片封装体的截面示意图。 FIG. 1 is a schematic cross-sectional view of a chip package provided with packaging glass according to the first embodiment of the present invention.

图2为图1的芯片封装体未安装该封装玻璃时的俯视图。 FIG. 2 is a top view of the chip package in FIG. 1 when the packaging glass is not installed.

图3为本发明第二实施方式提供的一种芯片封装体的截面示意图。 FIG. 3 is a schematic cross-sectional view of a chip package provided by a second embodiment of the present invention.

主要元件符号说明 Description of main component symbols

芯片封装体chip package 100，200100, 200 电路板circuit board 1010 芯片chip 20，22020,220 导线wire 3030 保护层The protective layer 40，8040, 80 封装玻璃Encapsulation glass 5050 基层grassroots 101101 金属底层metal bottom 102102 中间层middle layer 103103 导电线路层Conductive circuit layer 104104 连接垫connection pad 114114 通孔through hole 60，12060,120 第一顶面first top surface 201201 芯片电极垫Chip electrode pad 202202 暴露区域exposed area 203203 第二顶面second top surface 124124

如下具体实施方式将结合上述附图进一步说明本发明。 The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

具体实施方式 Detailed ways

下面将结合图式对本发明作进一步详细说明。 The present invention will be further described in detail below in conjunction with the drawings.

请参阅图1至图2，本发明第一实施方式提供的一种芯片封装体100包括电路板10、芯片20、导线30、保护层40及封装玻璃50。 Referring to FIG. 1 to FIG. 2 , a chip package 100 provided by the first embodiment of the present invention includes a circuit board 10 , a chip 20 , wires 30 , a protective layer 40 and a packaging glass 50 .

该电路板10包括基层101、金属底层102、中间层103及导电线路层104。该金属底层102形成在该基层101上，该中间层103形成在该金属底层102上，该导电线路层104形成在该中间层103上。该中间层103可为一层绝缘层或可为包含如金属层与绝缘层交替堆叠的多层结构。 The circuit board 10 includes a base layer 101 , a metal base layer 102 , an intermediate layer 103 and a conductive circuit layer 104 . The metal base layer 102 is formed on the base layer 101 , the intermediate layer 103 is formed on the metal base layer 102 , and the conductive circuit layer 104 is formed on the intermediate layer 103 . The intermediate layer 103 may be an insulating layer or may be a multi-layer structure including alternately stacked metal layers and insulating layers.

本实施方式中，该基层101的材料为陶瓷。金属底层102用于接地。本实施方式中，请参图2，（图2为去掉封装玻璃50及保护层40的芯片封装体100的俯视图）该导电线路层104包括4个连接垫114。 In this embodiment, the material of the base layer 101 is ceramics. The metal bottom layer 102 is used for grounding. In this embodiment, please refer to FIG. 2 , ( FIG. 2 is a top view of the chip package 100 without the encapsulation glass 50 and the protective layer 40 ). The conductive circuit layer 104 includes four connection pads 114 .

该芯片封装体100开设有贯穿该导电线路层104及该中间层103的通孔60以暴露该金属底层102。该芯片20置于该通孔60内且位于该金属底层102上。该芯片20与该金属底层102相互绝缘。金属底层102有利于芯片20的散热从而提升芯片封装体100的散热性能，而接地的金属底层102可以滤除掉来自芯片20附近电路产生的电磁波干扰及滤除掉芯片20在工作时产生的电磁波干扰，避免了芯片20与该附近电路的互相干扰。该附近电路可包括该芯片封装体100包含的其它电路及/或该芯片封装体100应用至其它电子装置时，该电子装置包含的电路。本实施方式中，芯片20的背面通过绝缘粘胶粘着在金属底层102上。可以理解，若芯片20的背面是不导电的，则也可省略绝缘粘胶而将芯片20直接与金属底层102接触，或采用一般的粘胶将芯片20粘着于金属底层102。 The chip package 100 is opened with a through hole 60 penetrating through the conductive circuit layer 104 and the intermediate layer 103 to expose the metal bottom layer 102 . The chip 20 is disposed in the through hole 60 and on the metal bottom layer 102 . The chip 20 and the metal bottom layer 102 are insulated from each other. The metal bottom layer 102 is conducive to the heat dissipation of the chip 20 so as to improve the heat dissipation performance of the chip package 100, and the grounded metal bottom layer 102 can filter out the electromagnetic wave interference generated by the circuit near the chip 20 and the electromagnetic wave generated by the chip 20 during operation. Interference avoids mutual interference between the chip 20 and the nearby circuits. The nearby circuits may include other circuits contained in the chip package 100 and/or circuits contained in the electronic device when the chip package 100 is applied to other electronic devices. In this embodiment, the backside of the chip 20 is adhered to the metal bottom layer 102 by insulating adhesive. It can be understood that if the backside of the chip 20 is non-conductive, the insulating adhesive can also be omitted and the chip 20 can be directly contacted with the metal bottom layer 102 , or the chip 20 can be adhered to the metal bottom layer 102 with common glue.

该导线30连接该芯片20及该导电线路层104。具体地，该芯片20包括第一顶面201及位于该第一顶面201上的4个芯片电极垫202，该导电线路层104包括第二顶面124，该第一顶面201与该第二顶面124处于同一水平面。导线30包括4个导线，导线30连接芯片电极垫202及该连接垫114。导线30可通过如打线接合(wire bonding)的方法而连接该芯片电极垫202及该连接垫114。导线30可为金线，铝线或铜线等金属线。 The wire 30 connects the chip 20 and the conductive circuit layer 104 . Specifically, the chip 20 includes a first top surface 201 and four chip electrode pads 202 located on the first top surface 201, the conductive circuit layer 104 includes a second top surface 124, the first top surface 201 and the first top surface 201 The two top surfaces 124 are at the same level. The wires 30 include four wires, and the wires 30 connect the chip electrode pads 202 and the connection pads 114 . The wire 30 can be connected to the chip electrode pad 202 and the connection pad 114 by a method such as wire bonding. The wire 30 can be metal wires such as gold wires, aluminum wires or copper wires.

保护层40的材料为热固化树脂，如聚酰亚胺树脂(polyimide resin)、环氧树脂(epoxy resin)、有机硅树脂(silicone resin)或类似物。当然，保护层40的材料也不限于上述所列举，本领域内的其它保护层材料也可用于本发明。本实施方式中，该保护层40覆盖该导线30、该导线30与该芯片电极垫202的连接处及该导线30与该连接垫114的连接处及填充通孔60。保护层40可加强导线30分别与导电线路层104及芯片20的连接强度同时还可增加导线30、芯片电极垫202及连接垫114的抗氧化性以延长芯片封装体100的使用寿命。本实施方式中，芯片20的第一顶面201包括未被保护层40覆盖的暴露区域203。当芯片20为发光芯片或感光芯片时，这种结构有利于提升芯片20的出光效率或收光效率。该暴露区域203对应为发光部分或感光部分。 The material of the protective layer 40 is a thermosetting resin, such as polyimide resin, epoxy resin, silicone resin or the like. Of course, the material of the protective layer 40 is not limited to the above list, and other protective layer materials in the field can also be used in the present invention. In this embodiment, the protection layer 40 covers the wire 30 , the connection between the wire 30 and the chip electrode pad 202 , the connection between the wire 30 and the connection pad 114 , and fills the through hole 60 . The protective layer 40 can strengthen the connection strength between the wire 30 and the conductive circuit layer 104 and the chip 20 respectively, and can also increase the oxidation resistance of the wire 30 , the chip electrode pad 202 and the connection pad 114 to prolong the service life of the chip package 100 . In this embodiment, the first top surface 201 of the chip 20 includes an exposed area 203 not covered by the protection layer 40 . When the chip 20 is a light-emitting chip or a photosensitive chip, this structure is beneficial to improve the light extraction efficiency or light collection efficiency of the chip 20 . The exposed area 203 corresponds to a light emitting part or a photosensitive part.

封装玻璃50黏合于保护层40上，以将芯片20封装在芯片封装体100中以保护芯片20免受水汽及灰尘的侵蚀及密封该暴露区域203。 The encapsulation glass 50 is bonded on the passivation layer 40 to package the chip 20 in the chip package 100 to protect the chip 20 from moisture and dust and seal the exposed area 203 .

上术芯片封装体100，将芯片20置于该通孔60内且位于该金属底层102上，使芯片20相对于导电线路层104的高度降低，进而使得连接芯片20与导电线路层104的导线30变短，因此可降低导线30的等效电感值而降低导线30的电感效应，同时也可以减少导线30的使用，节约成本。可以理解，芯片20的类型也不限于上述所列的类型，也可为本领域内的包括高频芯片的其它类型芯片。 In the chip package 100 described above, the chip 20 is placed in the through hole 60 and on the metal bottom layer 102, so that the height of the chip 20 relative to the conductive circuit layer 104 is reduced, so that the wires connecting the chip 20 and the conductive circuit layer 104 30 is shortened, so the equivalent inductance value of the wire 30 can be reduced and the inductance effect of the wire 30 can be reduced, and the use of the wire 30 can also be reduced to save costs. It can be understood that the type of the chip 20 is not limited to the types listed above, and may also be other types of chips including high-frequency chips in the art.

请参阅图3，本发明第二实施方式提供的一种芯片封装体200。该芯片封装体200与第一实施方式的芯片封装体100不同之处在于：保护层80填充通孔120并覆盖芯片220，而省略了封装玻璃。 Please refer to FIG. 3 , a chip package 200 provided in a second embodiment of the present invention. The chip package 200 differs from the chip package 100 of the first embodiment in that the protective layer 80 fills the through hole 120 and covers the chip 220 , and the packaging glass is omitted.

另外，本领域技术人员还可以在本发明精神内做其它变化，如在其它实施方式中，芯片20可部分地位于通孔60内而使得芯片20的第一顶面201比第二顶面124高，使得相较于没开设通孔60的芯片封装体，导线30也能缩短；或在其它实施方式中，芯片20的第一顶面201比第二顶面124稍低，使得相较于没开设通孔60的芯片封装体，导线30也能缩短等。当然，这些依据本发明精神所做的变化，都应包含在本发明所要求保护的范围之内。 In addition, those skilled in the art can also make other changes within the spirit of the present invention. For example, in other embodiments, the chip 20 can be partially located in the through hole 60 so that the first top surface 201 of the chip 20 is smaller than the second top surface 124. High, so that compared with the chip package without the through hole 60, the wire 30 can also be shortened; or in other embodiments, the first top surface 201 of the chip 20 is slightly lower than the second top surface 124, so that compared with In the chip package without the through hole 60, the wire 30 can also be shortened. Of course, these changes made according to the spirit of the present invention should all be included within the scope of protection claimed by the present invention.

Claims (10)

1.一种芯片封装体，其包括电路板、芯片及导线，该电路板包括金属底层、形成在该金属底层的中间层及形成在该中间层的导电线路层，该金属底层用于接地，该芯片封装体开设贯穿该导电线路层及该中间层的通孔以暴露该金属底层，该芯片置于该通孔内且位于该金属底层上，该芯片与该金属底层相互绝缘，该导线连接该芯片及该导电线路层。 1. A chip package, which includes a circuit board, a chip and wires, the circuit board includes a metal bottom layer, an intermediate layer formed on the metal bottom layer and a conductive circuit layer formed on the intermediate layer, the metal bottom layer is used for grounding, The chip package opens a through hole through the conductive circuit layer and the intermediate layer to expose the metal bottom layer, the chip is placed in the through hole and on the metal bottom layer, the chip and the metal bottom layer are insulated from each other, and the wire is connected The chip and the conductive circuit layer. 2.如权利要求1所述的芯片封装体，其特征在于，该芯片包括芯片电极垫，该导电线路层包括连接垫，该导线连接该芯片电极垫及该连接垫。 2 . The chip package as claimed in claim 1 , wherein the chip includes a chip electrode pad, the conductive circuit layer includes a connection pad, and the wire connects the chip electrode pad and the connection pad. 3.如权利要求1所述的芯片封装体，其特征在于，该芯片包括第一顶面，该导电线路层包括第二顶面，该第一顶面与该第二顶面处于同一水平面。 3 . The chip package as claimed in claim 1 , wherein the chip comprises a first top surface, the conductive circuit layer comprises a second top surface, and the first top surface and the second top surface are at the same level. 4.如权利要求2所述的芯片封装体，其特征在于，该芯片封装体还包括保护层，该保护层覆盖该导线、该导线与该芯片电极垫的连接处及该导线与该连接垫的连接处。 4. The chip package according to claim 2, wherein the chip package further comprises a protective layer, the protective layer covers the wire, the connection between the wire and the chip electrode pad, and the wire and the connection pad of the connection. 5.如权利要求4所述的芯片封装体，其特征在于，该保护层的材料为热固化树脂。 5 . The chip package as claimed in claim 4 , wherein a material of the protective layer is a thermosetting resin. 6.如权利要求4所述的芯片封装体，其特征在于，该芯片封装体包括黏合于该保护层的封装玻璃，该芯片包括第一顶面，该第一顶面包括未被保护层覆盖的暴露区域，该封装玻璃与该保护层密封该暴露区域。 6. The chip package as claimed in claim 4, wherein the chip package comprises encapsulation glass bonded to the protective layer, the chip comprises a first top surface, and the first top surface includes a top surface not covered by the protective layer. The exposed area, the encapsulating glass and the protective layer seal the exposed area. 7.如权利要求4所述的芯片封装体，其特征在于，该保护层填充该通孔并覆盖该芯片。 7. The chip package as claimed in claim 4, wherein the passivation layer fills the through hole and covers the chip. 8.如权利要求1所述的芯片封装体，其特征在于，该芯片封装体包括将该芯片粘着于该金属底层上的粘胶。 8 . The chip package as claimed in claim 1 , wherein the chip package comprises adhesive for adhering the chip on the metal bottom layer. 9.如权利要求1所述的芯片封装体，其特征在于，该芯片包括第一顶面，该导电线路层包括第二顶面，该第一顶面比该第二顶面高。 9. The chip package as claimed in claim 1, wherein the chip comprises a first top surface, the conductive wiring layer comprises a second top surface, and the first top surface is higher than the second top surface. 10.如权利要求1所述的芯片封装体，其特征在于，该芯片包括第一顶面，该导电线路层包括第二顶面，该第一顶面比该第二顶面低。 10 . The chip package as claimed in claim 1 , wherein the chip comprises a first top surface, the conductive circuit layer comprises a second top surface, and the first top surface is lower than the second top surface. 11 .
CN2011101881347A 2011-07-06 2011-07-06 Chip packaging body Pending CN102867814A (en)

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