CN102866262B - Array type single-chip integrated digital microaccelerometer - Google Patents

Abstract

The invention relates to a microaccelerometer, in particular to an array type single-chip integrated microaccelerometer. The technical problems of large size of the conventional acceleration sensor, incapability of realizing the full scale output of the conventional accelerometer unit, high breakage rate of the root of a clamped beam and incapability of realizing the optimal configuration of a high-low-range accelerator are solved. The array type single-chip integrated microaccelerometer comprises a monocrystalline silicon material structural layer (2), and the structural layer (2) is divided into a left part and a right part. A first piezoresistive accelerometer unit (21) and a second piezoresistive accelerometer unit (22) are integrated on the upper and lower parts of the right part of the structural layer (2) respectively, and have different ranges. A complementary metal oxide semiconductor (CMOS) circuit for amplifying and filtering output signals of the first and second piezoresistive accelerometer units (21 and 22) is integrated on the left part of the structural layer (2). Accelerometer array units and a signal processing circuit are integrated on the same chip, so that the microaccelerometer is miniaturized and integrated.

Description

Array Single Chip Integrated Digital Microaccelerometer

technical field

The invention relates to a micro accelerometer, in particular to an array type single chip integrated digital micro accelerometer.

Background technique

At present, with the continuous expansion of the application range of the acceleration sensor, the requirements for the acceleration sensor are getting higher and higher, that is, miniaturization, integration, low cost, and high performance. The sensor of MEMS technology is small in size and light in weight, but the large size and low reliability of the board-level circuit used to process the output signal of the acceleration sensor cannot meet the development trend of miniaturization of MEMS devices. If the processing circuit (board-level circuit) of the sensor can be miniaturized, the volume and weight of the sensor can be greatly reduced, and the reliability of the sensor can also be improved. The micro sensor system replaces the existing sensor system and expands the application range of the sensor.

CMOS technology has become the main manufacturing process of integrated circuits. While the manufacturing cost has decreased, the yield and output have also been greatly improved. CMOS is the abbreviation of Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor), which refers to a technology used to manufacture large-scale integrated circuit chips or chips manufactured by this technology.

The processing circuit of the existing compound-range accelerometer usually adopts the board-level circuit mode, and the disadvantages are as follows: 1. Large volume; 2. The root of the fixed beam in the piezoresistive accelerometer unit is under high impact (ie high overload) 3. In order to highlight the characteristics of the accelerometer covering high and low ranges, considering the limitations of the accelerometer’s processing technology, some structural dimensions of the high-range and low-range accelerometer units must be consistent, and the fixed beam and mass The thickness of the block is the same, and the dimensions of the accelerometer unit should also be consistent. In view of these constraints, it is often difficult to achieve the optimal configuration of the performance of the high and low range accelerometer unit, and become a high and low range accelerometer unit. A difficult point of monolithic integration.

Therefore, it is necessary to invent a new monolithic integrated array digital micro accelerometer.

Contents of the invention

The present invention aims to solve the technical problem of the large size of the existing acceleration sensor. In addition, the present invention also optimizes the design of the existing accelerometer covering high and low ranges and solves the problem of high overload resistance, and provides a new type of array single chip Integrated digital micro accelerometer.

The present invention is realized by adopting the following technical solutions:

An array-type single-chip integrated digital micro-accelerometer, including a structural layer of monocrystalline silicon material; the structural layer is divided into left and right parts, and the upper and lower parts on the right side of the structural layer are respectively integrated with the first piezoresistive acceleration of different ranges A meter unit and a second piezoresistive accelerometer unit; the left side of the structural layer is integrated with a CMOS circuit that amplifies and filters the output signals of the first and second piezoresistive accelerometer units; the first piezoresistive accelerometer unit includes The first quality block placed in the structural layer, the first mass block is integrally formed with the structural layer through four first fixed beams; the four first fixed beams are respectively provided with equal resistance and connected into The piezoresistor of the Wheatstone bridge; the second piezoresistive accelerometer unit includes a second quality block placed in the structural layer, and the second mass block is integrally formed with the structural layer by four second fixed beams ; The four second fixed support beams are respectively provided with piezoresistors with equal resistance and connected to form a Wheatstone bridge; the Wheatstone bridges are respectively connected to the CMOS circuit.

When working, piezoresistors with equal resistance are manufactured on each fixed beam of the accelerometer unit by ion implantation, and then connected to form a Wheatstone bridge. According to the piezoresistive effect, when the accelerometer unit feels acceleration in the working direction, the mass block moves up and down, and the four fixed beams of each accelerometer unit are subjected to stress, and the resistance of the piezoresistor on the fixed beam changes. , the output voltage of the Wheatstone bridge will also change accordingly, and its output voltage is proportional to the applied acceleration. The output voltage of the Wheatstone bridge is processed by the CMOS circuit with the function of amplification and filtering, and then the measured acceleration can be obtained through calculation and processing.

The invention integrates the accelerometer array unit and the signal processing circuit (CMOS circuit with amplification and filtering function) into one chip, realizes miniaturization and integration, greatly reduces the volume and weight of the acceleration sensor, and reduces the The number and weight of components provide important testing means and early development for the development of a new generation of aircraft and weaponry.

The invention has reasonable design and simple structure, and effectively solves the technical problem of large volume of the existing micro sensor.

Description of drawings

Figure 1 is a schematic diagram of the structure of the structural layer.

Fig. 2 is a bottom view of Fig. 1 .

Fig. 3 is a schematic diagram of the structure of the glass layer.

Fig. 4 is a schematic structural diagram of an embodiment of the present invention.

Fig. 5 is a structural schematic diagram of a Wheatstone bridge circuit.

In the figure, 1-cover plate, 2-structural layer, 3-glass layer, 20-varistor, 21-first piezoresistive accelerometer unit, 211-first fixed beam, 212-first mass block, 22-second piezoresistive accelerometer unit, 221-second fixed beam, 222-second mass, 23-groove, 31-metal electrode, 32-metal lead, 33-pressure welding point.

Detailed ways

Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

As shown in Figures 1 and 2, an array-type single-chip integrated digital micro-accelerometer includes a structural layer 2 of monocrystalline silicon material; the structural layer 2 is divided into left and right parts, and the upper and lower parts on the right side of the structural layer 2 are respectively The first piezoresistive accelerometer unit 21 and the second piezoresistive accelerometer unit 22 with different ranges are integrated; the left side of the structural layer 2 is integrated with amplifying the output signals of the first and second piezoresistive accelerometer units 21 and 22 CMOS circuit for filter processing; the first piezoresistive accelerometer unit 21 includes a first quality block 212 placed in the structural layer 2, and the first mass block 212 connects with the structural layer through four first fixed beams 211 2 integral structure; the four first fixed support beams 211 are respectively provided with piezoresistors 20 with equal resistance and connected to form a Wheatstone bridge; the second piezoresistive accelerometer unit 22 includes 2, the second quality block 222 is integrally formed with the structural layer 2 through four second fixed beams 221; the four second fixed beams 221 are respectively provided with equal resistance, The piezoresistors 20 connected as Wheatstone bridges; the Wheatstone bridges are respectively connected to the CMOS circuits.

It also includes a cover plate 1 of monocrystalline silicon material placed on the structure layer 2 and a glass layer 3 placed below the structure layer 2; The corresponding place is provided with a concave surface (concave surface can be corroded during specific processing); the thickness of the first mass block 212 and the second mass block 222 are both smaller than the thickness of the structural layer 2, and the first mass block 212 and the second mass block The glass layer 3 corresponding to the block 222 is respectively provided with metal electrodes 31; the glass layer 3 is provided with two pads 33, and the metal electrodes 31 are respectively connected to the corresponding pads 33 through metal leads 32; Corresponding grooves 23 are provided below the structure layer 2 corresponding to the metal leads 32 and bonding points 33 on the glass layer (during specific processing, shallow grooves are corroded below the structure layer 2 corresponding to the metal leads 32 , Corresponding to the place where the pad 33 is corroded with a deep groove). As shown in Figures 2, 3, and 4.

During specific implementation, the four first fixed beams 211 are laterally symmetrically distributed on two opposite sides of the first mass block 212 (four-beam structure at both ends); the four second fixed beams 221 are respectively distributed on the second The four sides of the two-mass block 222 (four-end four-beam structure).

The measuring range of the first piezoresistive accelerometer unit 21 is 10g, the specification of the first fixed support beam 211 is: beam length 700um, beam width 80um, beam thickness 20um, the specification of the first mass block 212 is : length 2000um, width 1200um, thickness 395um; the measuring range of the second piezoresistive accelerometer unit 22 is 10000g, the specifications of the second fixed support beam 221 are: beam length 800um, beam width 1000um, beam thickness 20um, The specification of the second mass block 222 is: length 1000um, width 1000um, thickness 395um; the specification of the cover plate 1 is: length 10000um, width 10000um, height 320um, the specification of the concave surface on the inner side of the cover plate 1 is: The length is 8000um, the width is 8000um, and the depth is 50um.

In addition, the first mass block 212 can also be in a cross structure. The specifications of the added parts on the left and right sides of the first mass block 212 are: length 1240um, width 500um, thickness 395um, making full use of the limited space structure, increasing the first The weight of mass block 212.

Each of the first fixed support beams 211 is provided with two piezoresistors 20 along its length, which is beneficial to the accurate output of the Wheatstone bridge.

The first stage of the CMOS circuit with amplification and filtering processing functions uses a low-noise and low-offset front-end operational amplifier, the second stage uses an active low-pass filter circuit, and the third stage uses a low-noise high-gain operational amplifier.

The CMOS circuit is integrated on the structural layer 2 through a CMOS integrated circuit process; the first piezoresistive accelerometer unit 21 and the second piezoresistive accelerometer unit 22 are integrated on the structural layer 2 through silicon micromachining technology; The piezoresistor 20 is fabricated on the first fixed beam 211 and the second fixed beam 221 by ion implantation.

The cover plate 1 is placed on the structural layer 2 through a silicon-silicon direct bonding process, and the glass layer 3 is placed under the structural layer 2 through a silicon-glass electrostatic bonding process.

During specific use, since the thicknesses of the first mass block 212 and the second mass block 222 are smaller than the thickness of the structural layer 2, there is a certain gap between the bottom surface of the mass block and the glass layer 3, which is equal to the mass of the structural layer 2 and the mass. The thickness of the block is different, and the metal electrode 31 is just placed in this gap, but not in contact with the first and second mass blocks 212, 222; because the inner surface of the cover plate 1 is corroded with a concave surface, so the mass block and the cover plate There is also a certain gap between 1; the function of cover plate 1 and glass layer 3 is to prevent the overload of the accelerometer unit, when the accelerometer unit feels acceleration in the working direction, the mass block is in the space formed by cover plate 1 and glass layer 3 move up and down inside, so as to protect the piezoresistive accelerometer unit, so that the roots of the first and second solid support beams 211, 221 will not break due to the blocking effect of the cover plate 1 and the glass layer 3 under high overload conditions Case. The function of the metal electrode 31 on the glass layer 3 is to eliminate static electricity.

At present, the main difficulty in the monolithic integration design of the array accelerometer unit is how to optimize the design of the sensitive structure (mass block and fixed support beam) with high and low ranges. Considering the limitations of the processing technology of the accelerometer unit, in order to highlight the characteristics of the acceleration sensor covering the high and low ranges, to realize the monolithic integration of the high and low range accelerometer units, and to optimize the performance of the two, then the low range accelerometer unit requires a higher Sensitivity requires a larger mass block structure and a smaller thickness of the fixed beam; while the high-range accelerometer unit is often less sensitive in order to obtain a large range range and full-scale output. In some cases, the mass block structure of the high-range accelerometer unit should be smaller, and the fixed support beam can also be thicker. Moreover, the sensitivity, natural frequency and damping characteristics of the acceleration sensor have certain mutual constraints on the structural size. According to the analysis of a large number of test results, the size structure of the accelerometer unit is the main influencing factor of the acceleration sensor. Therefore, in order to make full use of the space structure of the first accelerometer unit (low range), the shape of the first mass block is designed as a cross structure, and the weight of the first mass block is increased as much as possible. In order to further improve the sensitivity of the first accelerometer unit , the first accelerometer unit is designed as a four-beam structure at both ends, and the first fixed beam and the first mass block have the above-mentioned size optimization structure (the first fixed beam: the beam length is 700um, the beam width is 80um, and the beam thickness is 20um ; The first mass: 2000um in length, 1200um in width, and 395um in thickness, and the increased part on both sides is 1240um in length, 500um in width, and 395um in thickness). In consideration of improving the range of the second accelerometer unit (high range), it is necessary to properly reduce the sensitivity, improve the overload resistance, and achieve full-scale output. The second accelerometer unit chooses a four-terminal four-beam structure, and the second fixed beam and The second mass block has the above-mentioned size-optimized structure (second fixed beam: beam length 800um, beam width 1000um, beam thickness 20um, second mass block: length 1000um, width 1000um, thickness 395um), and can also reduce its lateral direction Sensitivity index. Therefore, the optimal design of the structural size of the first accelerometer unit and the second accelerometer unit enables the accelerometer unit with a large range to output at full scale, and the performance of the accelerometer unit with a high and low range is optimized. More importantly, this The maximum overload of the accelerometer unit of the invention can reach 20000g, and when the accelerometer unit reaches the maximum overload of 20000g, the low-range accelerometer unit will not be damaged, which improves the reliability of the acceleration sensor.

The main function of the CMOS circuit is to amplify and filter the output signal of the sensitive structure of the accelerometer unit; considering the noise and offset introduced when collecting weak signals, the first stage of the CMOS circuit adopts a low-noise and low-offset front-end operational amplifier, which can Effectively suppress signal noise, reduce signal offset voltage, and ensure the collection and amplification of weak front-end signals; the second stage uses an active low-pass filter circuit to further filter out other frequency signals and noise; the third stage uses low-noise high-gain operations The amplifier further amplifies the weak signal to meet the requirements of post-stage signal processing. The CMOS circuit uses an internal reference power supply to distribute power to each part of the circuit. Further improve the accuracy of the acceleration sensor.

The test results are analyzed as follows:

1. Sampling piece (array type single-chip integrated digital micro-accelerometer), test the static performance index of the first accelerometer unit (low range) as shown in Table 1.1:

1.1 Sample static performance index

the Sensitivity (mv/g) Linearity (F.S) Repeatability (F.S) Hysteresis (F.S) Transverse Sensitivity (F.S) sample 65.18 0.282% 0.259% 0.268% 2.57% Design specifications 60 ≤0.5% ≤0.3% ≤0.3% ≤3%

2. The test results of the second accelerometer unit (high range) are shown in Table 1.2:

Table 1.2 Sensitivity, linearity and repeatability of each sample

the Sample 1 Sample 2 Sample 3 Sample 4 Design specifications Sensitivity (μv/g) 177.3 193.3 173.4 181.9 20×5.5 Linearity 3.00% 2.96% 3.01% 2.82% ≤±3% repeatability 0.89% 0.91% 0.87% 0.90% ≤0.9%

From the analysis of the above test results, it can be seen that the high and low range samples basically meet the design index requirements, making the array accelerometer single-chip integrated high and low range sensitive structure achieve optimal design.

Semiconductor Silicon Micromachining Technology Introduction:

(1) Photolithography: It is a precision surface processing technology that combines graphic printing and chemical etching. In the production process of semiconductor devices, the purpose of lithography is to etch a geometric pattern completely corresponding to the mask on the silicon dioxide film or metal film according to the requirements of device design, so as to realize selective diffusion and metal film wiring. Purpose. Photolithography is one of the key processes in the semiconductor device manufacturing process. The quality of photolithography directly affects the performance and yield of semiconductor devices.

(2) Corrosion: The photoresist micropattern structure made by photolithography can only give the morphology of the device, not the real device structure. In order to obtain the structure of the device, the pattern of the photoresist must be transferred to the layers of material below the photoresist. Etching refers to the selective removal of parts not masked by photoresist (such as silicon dioxide, silicon nitride, polysilicon or metal aluminum film) by chemical, physical or chemical physical methods at the same time, so as to finally achieve Transfer the mask pattern to the film. Ideal corrosion requires vertical corrosion (anisotropic corrosion), high selectivity ratio (only for thin film corrosion, no corrosion or minimal corrosion for substrate) and controllability of corrosion indicators. Corrosion methods can be roughly divided into two categories: wet etching and dry etching.

a. Wet etching: The wet etching pattern is limited by the crystal orientation, the aspect ratio is poor, and the side wall is inclined. Wet etching is divided into isotropic etching and anisotropic etching. The comparison of different types of wet etching is shown in Table 1.3.

Table 1.3 Different types of wet etching

Using KOH etchant to perform anisotropic etching on (100) crystal plane is a simple and important processing technology in semiconductor silicon micromachining technology.

b. Dry etching: including PE (plasma etching), RIE (reactive ion etching), ICP (inductively coupled plasma etching), TCP (transformer coupled plasma etching), ECR (electron cyclotron resonance etching), etc. Dry etching Clean, dry, no floating glue phenomenon, simple process, high graphics resolution, high cost. Table 1.4 is a comparison of several dry etching methods.

Table 1.4 Comparison of several dry etching methods

the Plasma etching (PE) Reactive Ion Etching (RIE) Inductively Coupled Plasma Erosion (ICP) Reaction mechanism chemical reaction Chemical Reaction/Physical Reaction Chemical Reaction/Physical Reaction corrosion direction Isotropic general anisotropy anisotropy features High speed, good process compatibility, good mask selectivity, good surface morphology High resolution, fast corrosion rate, less damage to devices High corrosion rate, good verticality, large selection ratio, large corrosion depth use Active Structures and High Aspect Ratio Structures Corrosion of aluminum wiring, etc. High aspect ratio structures, beam structures

In terms of high aspect ratio silicon etching and etching technology, the Institute of Microelectronics of Peking University has carried out fruitful research. The silicon deep groove etching technology adopts the STSMultiplex ICP high-density plasma etching system. This etching technology only uses F-based gas as an etchant, and a polymer generator for sidewall passivation, which solves the problems of system corrosion and process exhaust gas pollution.

(3) Deep groove reactive ion (RDEI) etching technology

In the past, dry etching was mainly used for surface micromachining, but recently due to the rise of many reactive ion etching techniques with fast etching rate, good anisotropy and high selective ratio of mask etching rate, RDEI is widely used for Bulk silicon micromachining has become a powerful tool for fabricating high aspect ratio micromechanical structures. Surface Teehnozogy Systen, (STS) company develops T inductively coupled plasma (CIP) system, uses photoresist as a mask, and the polymerization of photoresist on the sidewall can passivate the sidewall, so the etching depth can be controlled up to 500 microns. The mass block structure of the piezoresistive accelerometer described in the present invention is completed by RDEI technology.

(4) Ion implantation

The varistor described in the present invention is completed by ion implantation process. Ion implantation is a kind of doping technology, which is to dope the required impurities into the specified area of the semiconductor substrate in a certain way, and achieve the specified quantity and distribution in order to change the electrical properties of the material and make PN Junctions, resistance of integrated circuits and purpose of interconnecting wires.

(5) Bonding process

盖板与结构层采用的是硅-硅直接键合工艺：用BCB胶将上盖板与器件热粘结键合，这个过程相对简单，这里简要介绍一下BCB胶。BCB（benzo-cyclo-butene，苯并环丁烯）从90年代开始商业化，是一种先进的电子封装材料。BCB用于硅-硅圆片级粘结时，有如下一些优点：

The cover plate and the structural layer adopt a silicon-silicon direct bonding process: the upper cover plate and the device are thermally bonded and bonded with BCB glue. This process is relatively simple. Here is a brief introduction to BCB glue. BCB (benzo-cyclo-butene, benzocyclobutene) has been commercialized since the 1990s and is an advanced electronic packaging material. When BCB is used for silicon-silicon wafer level bonding, it has the following advantages:

a. High planarization capability: For 25um lines and spaces, the planarity is greater than 80%.

b. Low curing temperature: 200~300 degrees, even at 180 degrees.

c. Good bonding performance, very high bonding strength.

d. BCB can also be photolithographic or etched, so that it can be selectively pasted.

e. The cured BCB has a transparent transmittance of 90% for visible light, so it can be used in optical devices.

f. The cured BCB can resist the erosion of many acids, alkalis and solvents, and is suitable for fluid applications.

g. The water absorption rate is very low and the dielectric constant is relatively low.

The glass layer and the structure layer adopt the silicon-glass electrostatic bonding process. The silicon-glass bonding process is as follows: the polished silicon wafer surface is in contact with the polished glass surface. This structure is placed on a heating plate, and the two ends are connected to an electrostatic voltage, the glass is connected to the negative electrode, and the silicon wafer is connected to the anode. When the temperature reaches a certain height, the glass begins to soften, so that the activity of Na+ in the glass is enough to make the glass have the same conductivity as metal. Under the action of an electric field, Na+ drifts to the cathode and neutralizes with the cathode, thereby generating a negative space charge region near the anode, and the drift stops after equilibrium. At this time, a chemical reaction occurs on the surface in close contact to form a strong Si-O bond and complete the bond.

Claims (9)

1. an array type single integrated chip numeral micro-acceleration gauge, is characterized in that: the structural sheet (2) that comprises single crystal silicon material; Described structural sheet (2) is divided into left and right two parts, and the two parts up and down on structural sheet (2) right side are integrated with respectively the first piezoresistive accelerometer unit (21) and the second piezoresistive accelerometer unit (22) of different ranges; Structural sheet (2) left side is integrated with the cmos circuit that the output signal of first and second piezoresistive accelerometer unit (21,22) is carried out to amplification filtering processing; Described the first piezoresistive accelerometer unit (21) comprises the first mass (212) being placed in structural sheet (2), and described the first mass (212) consists of four the first clamped beams (211) and structural sheet (2) one; On described four the first clamped beams (211), be respectively equipped with the voltage dependent resistor (VDR) (20) that resistance equates, connects into Wheatstone bridge; Described the second piezoresistive accelerometer unit (22) comprises the second mass (222) being placed in structural sheet (2), and described the second mass (222) consists of four the second clamped beams (221) and structural sheet (2) one; On described four the second clamped beams (221), be respectively equipped with the voltage dependent resistor (VDR) (20) that resistance equates, connects into Wheatstone bridge; Described Wheatstone bridge accesses respectively described cmos circuit;

Described four the first clamped beams (211) lateral symmetry is distributed in two opposite flanks of the first mass (212); Described four the second clamped beams (221) are distributed in respectively four sides of the second mass (222);

The range of described the first piezoresistive accelerometer unit (21) is 10g, the specification of described the first clamped beam (211) is: beam length 700um, deck-siding 80um, the thick 20um of beam, and the specification of described the first mass (212) is: long 2000um, wide 1200um, thick 395um; The range of described the second piezoresistive accelerometer unit (22) is 10000g, the specification of described the second clamped beam (221) is: beam length 800um, deck-siding 1000um, the thick 20um of beam, the specification of described the second mass (222) is: long 1000um, wide 1000um, thick 395um.

2. array type single integrated chip according to claim 1 numeral micro-acceleration gauge, is characterized in that: also comprise be placed in structural sheet (2) above, the cover plate (1) of single crystal silicon material and be placed in structural sheet (2) glassy layer (3) below; Place corresponding with the first mass (212) and the second mass (222) on the medial surface of described cover plate (1) is provided with concave surface; The thickness of described the first mass (212) and the second mass (222) is all less than on the thickness of structural sheet (2) and the glassy layer (3) of the first mass (212) and the second mass (222) correspondence and is respectively equipped with metal electrode (31); Described glassy layer (3) is provided with two pressure welding point (33), and described metal electrode (31) is connected with corresponding pressure welding point (33) by metal lead wire (32) respectively; Place corresponding to the metal lead wire on glassy layer (32) and pressure welding point (33) below described structural sheet (2) is provided with corresponding groove (23).

3. array type single integrated chip according to claim 2 numeral micro-acceleration gauge, it is characterized in that: described cover plate (1) is placed in structural sheet (2) above by silicon-Si direct bonding technique, described glassy layer (3) is placed in structural sheet (2) below by si-glass static bonding process.

4. array type single integrated chip according to claim 3 numeral micro-acceleration gauge, it is characterized in that: the specification of described cover plate (1) is: long 10000um, wide 10000um, high 320um, the specification of the concave surface on cover plate (1) medial surface is: long 8000um, wide 8000um, dark 50um.

5. array type single integrated chip according to claim 4 numeral micro-acceleration gauge, it is characterized in that: described the first mass (212) extends respectively the part of increase and is cross structure on its two sides, left and right, and the specification of the part of described increase is: long 1240um, wide 500um, thick 395um.

6. array type single integrated chip numeral micro-acceleration gauge according to claim 4, is characterized in that: on described each first clamped beam (211), be provided with along its length two voltage dependent resistor (VDR)s (20).

7. array type single integrated chip numeral micro-acceleration gauge according to claim 5, is characterized in that: on described each first clamped beam (211), be provided with along its length two voltage dependent resistor (VDR)s (20).

8. array type single integrated chip according to claim 7 numeral micro-acceleration gauge, it is characterized in that: the first order of described cmos circuit adopts low-noise low-offset front end operational amplifier, the second level adopts active low-pass filter circuit, and the third level adopts low noise high gain operational amplifier.

9. array type single integrated chip numeral micro-acceleration gauge according to claim 8, is characterized in that: described cmos circuit is integrated on structural sheet (2) by CMOS integrated circuit technology; Described the first piezoresistive accelerometer unit (21) and the second piezoresistive accelerometer unit (22) are integrated on structural sheet (2) by silicon micromachining technique; Described voltage dependent resistor (VDR) (20) is produced on the first clamped beam (211) and the second clamped beam (221) by ion injection method.

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