CN112034204A - Linked contact capacitance type acceleration sensitive chip and manufacturing method thereof - Google Patents

Abstract

The invention discloses a linkage contact capacitance type acceleration sensitive chip and a manufacturing method thereof. The chip is manufactured by adopting silicon-on-insulator (SOI) and combining with silicon-silicon direct bonding technology, the Z axis is the sensitive direction of the chip, and the chip comprises a monocrystalline silicon substrate carved with a groove, a suspended movable lower polar plate, a silicon nitride dielectric layer, a sealed cavity, an upper polar plate and a metal layer. In an initial state, the interior of the cavity of the sensitive structure has air pressure difference with the outside, and the upper polar plate and the dielectric layer on the lower polar plate are in a contact state; when external acceleration acts on the sensitive structure, the contact area of the two polar plates changes, the lower polar plate is suspended and movable, the upper polar plate and the lower polar plate form a linkage effect, and the lower polar plate and an external circuit are connected through a pressure welding point to form a capacitance detection circuit, so that an acceleration signal is converted into a capacitance signal to be output. The linkage contact capacitance type acceleration sensitive chip has the advantages of good linearity, large linear measuring range, strong overload capacity, small cross coupling coefficient, high reliability, small temperature drift and the like.

Description

A linkage contact capacitive acceleration sensitive chip and its manufacturing method

technical field

The invention mainly relates to a linkage contact capacitive acceleration sensitive chip and a manufacturing method thereof, belonging to the field of micro-electromechanical systems (MEMS).

Background technique

With the development of MEMS technology, accelerometers have become an indispensable key device in various industries, and have been widely used in automotive electronics, industrial control, biomedicine, and defense and military industries. Compared with piezoresistive acceleration sensors, capacitive acceleration sensors have the advantages of high sensitivity, low power consumption, and good temperature characteristics, and are more suitable for the development of high-precision acceleration sensors, especially in modern aerospace technology and modern defense equipment. Under the background of increasing measurement accuracy and reliability requirements, the research of MEMS capacitive accelerometer has been highly valued at home and abroad.

At present, the mainstream capacitive acceleration sensors usually adopt the "comb type" and "sandwich type" structures. These two sensitive structures mainly realize acceleration detection by changing the capacitance change caused by the change of the distance between the electrode plates. The nonlinearity between the input and output signals is serious, and it is usually necessary to control the displacement of the mass block to obtain a relatively linear working area. The range is relatively small, the linearity has room for further improvement, and there is a shortcoming of small capacitance change, which not only brings great difficulties to the subsequent processing circuit, but also affects the accuracy and sensitivity of the device. In order to improve the performance of the capacitive acceleration sensor, the present invention proposes a contact capacitive acceleration sensitive structure, which realizes the acceleration measurement by changing the mutual contact area of the upper and lower pole plates. The characteristics of this structure are: the metal layer is made on the upper plate to increase the mass of the upper plate, so that the deformation of the upper plate is more sensitive to the external acceleration, and the lower plate in the structure is suspended and movable; , due to the pressure difference between the inside of the sensitive structure cavity and the outside world, the upper plate and the lower plate are already in contact with each other; when an acceleration acts on the sensitive structure, the contact area between the upper and lower plates will change, and the output The capacitance is mainly based on the contact capacitance between the two pole plates. During this process, the lower pole plate also deforms and adjusts with the movement of the upper pole plate, forming a linkage effect, so that the contact area changes at a nearly constant rate. , so the output capacitance value will show an approximate linear relationship with the acceleration change, the sensor shows superior linearity and higher output capacitance value, so as to solve the problem of linearity difference between the input and output of ordinary capacitive acceleration sensor, small capacitance change, etc. question.

The structure can be realized by using SOI material and using dry etching and silicon-silicon direct bonding technology. The thickness of the top layer of the SOI silicon wafer can be controlled within a few nanometers. Therefore, the use of the SOI material silicon film to prepare the upper and lower plates of the sensitive structure will significantly improve the accuracy of the plate thickness. Silicon-silicon direct bonding technology refers to a method of closely combining silicon wafers with silicon wafers, oxide wafers and other materials through chemical and physical effects, which can realize the perfect transfer of the single crystal silicon film on the top layer of SOI silicon wafers. The manufacturing process of the board is more controllable and easy to implement, and the internal air pressure of the sensitive structure cavity can be precisely set by controlling the air pressure of the bonding chamber.

It is under this research background that the present invention proposes a linked contact capacitive acceleration sensing chip and a manufacturing method thereof.

SUMMARY OF THE INVENTION

Purpose of invention:

The present invention, a linked contact capacitive acceleration sensitive chip and its manufacturing method, refers to the acceleration sensitive chip and its manufacturing method shown in the accompanying drawings of the present invention. The purpose is to improve the linearity, sensitivity and overload capacity of the MEMS capacitive acceleration sensor, increase the range of the linear region, make the manufacturing process of the chip easier to control and realize, reduce the chip area and reduce the cost.

The present invention is achieved through the following technical solutions:

A linked contact capacitive acceleration sensitive chip and a manufacturing method thereof, characterized in that: the chip comprises a monocrystalline silicon substrate etched with grooves, a lower pole plate located on the substrate, and a dielectric layer on the lower pole plate , the upper plate, the sealed cavity formed by the upper plate and the groove of the substrate, and the metal layer above the upper plate; the upper and lower plates are connected to the external circuit through pressure welding points to form an acceleration detection circuit, and the acceleration signal Converted to capacitive signal output.

The upper plate and the groove of the substrate form a sealed cavity, and the lower plate is located between the upper plate and the groove on the substrate, and is suspended relative to the silicon substrate, and its suspended height is etched by the groove on the substrate. depth to decide.

There is an air pressure difference between the inside of the sealed cavity and the outside world. When the sensitive chip is not subjected to acceleration, the dielectric layer on the upper plate and the lower plate is already in a certain degree of contact. The contact area changes, and the lower plate deforms with the deformation of the upper plate, and the two form a linkage effect. Within the range, the dielectric layer on the upper plate and the lower plate is always in contact.

The lower electrode plate is made of the silicon film on the first SOI substrate (A), and the silicon film side of the first SOI substrate (A) is connected to the substrate silicon wafer with etched grooves through the silicon-silicon direct bonding technology. are bonded together, and the silicon substrate and oxide layer of the original SOI substrate (A) are removed to realize the fabrication of the lower electrode plate.

The upper plate is made of the silicon film on the second SOI substrate (B), and one side of the second SOI substrate (B) silicon film is made of a suspended lower plate and etched through the silicon-silicon direct bonding technology. The substrate silicon wafers of the cavity are bonded together, the substrate and oxide layer of the original SOI substrate (B) are removed, and the fabrication of the upper electrode plate and the sealing of the cavity are completed.

When using the silicon-silicon direct bonding technology to fabricate the upper plate, the air pressure difference between the inside of the sealed cavity and the outside world is set by controlling the air pressure of the bonding chamber of the bonding equipment.

A metal layer is formed on the upper plate.

A dielectric layer is deposited on the lower electrode plate, and through holes are provided.

A linkage contact capacitive acceleration sensitive chip and a manufacturing method thereof, the main process steps are as follows:

(1) etching a single crystal silicon substrate to form a groove, as shown in Figure 4;

(2) thermally oxidize a layer of silicon dioxide on the monocrystalline silicon substrate engraved with grooves in FIG. 4 as an insulating layer, as shown in FIG. 5 ;

(3) bonding one side of the silicon film of the first SOI substrate (A) in FIG. 3 to the silicon substrate with grooves in FIG. 5 , as shown in FIG. 6 ;

(4) Remove the substrate silicon of the original SOI substrate (A) in the structure of FIG. 6 , as shown in FIG. 7 ;

(5) Etch the oxide layer above the lower plate in the structure of FIG. 7 to form a cavity structure, as shown in FIG. 8 ;

(6) deposit a layer of silicon nitride as a dielectric layer in the structure of FIG. 8, as shown in FIG. 9;

(7) Etch the silicon nitride dielectric layer in the structure of FIG. 9, and etch the lower electrode plate to form through holes, as shown in FIG. 10 (a) and (b);

(8) bonding one side of the silicon film of the second SOI substrate (B) in FIG. 11 to the structure in FIG. 10 , as shown in FIG. 12 ;

(9) Remove the substrate silicon and oxide layer of the original SOI substrate (B) in the structure of FIG. 12, as shown in FIG. 13;

(10) Sputtering a layer of metal gold (Au) on the structure shown in FIG. 13 , as shown in FIG. 14 ;

(11) Etch the metal gold and single crystal silicon layer in the structure of FIG. 14, and etch to the surface of the oxide layer below the upper pole plate to form the upper pole plate and the metal layer structure, as shown in FIG. 15;

(12) Etch the silicon oxide and single crystal silicon layer in the structure of FIG. 15, and etch to the silicon oxide surface below the lower electrode plate to form the lower electrode plate, as shown in FIG. 16;

(13) deposit a layer of silicon dioxide as the insulating passivation layer in the structure of FIG. 16, as shown in FIG. 17;

(14) The electrode contact holes of the upper and lower electrode plates are etched in the structure of FIG. 17, as shown in FIG. 18;

(15) A layer of metal gold is sputtered in the structure of FIG. 18 , and gold leads are etched to form the acceleration-sensitive structure as shown in FIG. 19 .

Advantages and Effects

The present invention has the following advantages and beneficial effects:

The linked contact capacitive acceleration sensitive chip of the present invention mainly realizes acceleration measurement by changing the contact area between the two polar plates, and designs a suspended movable lower electrode plate in the structure, so that the upper and lower electrode plates They all become movable structures, thereby improving the linearity and increasing the range of the linear region; in the manufacturing method, dry etching can greatly reduce the technical difficulty in front pattern protection, and can safely complete the grooves The precision of the thickness of the top silicon film of the SOI substrate can be controlled within a few nanometers. Therefore, using the silicon film of SOI material to prepare the upper and lower plates of the sensitive structure will significantly improve the accuracy of the thickness of the plates. ;Silicon-silicon direct bonding technology can realize the perfect transfer of single crystal silicon film on the top layer of SOI substrate, making the manufacturing process of the bipolar plate easier to control and realize, and can accurately set the sensitive structure by controlling the air pressure of the bonding chamber The internal air pressure of the cavity.

Description of drawings

FIG. 1 is a top view of the chip of the present invention.

Fig. 2 is a schematic view of the AA' section of the chip of the present invention.

3 is a schematic cross-sectional view of the first SOI substrate (A) used in the chip processing process of the present invention.

FIG. 4 is a schematic cross-sectional view of AA′ after etching a single crystal silicon substrate to form grooves in the chip processing process of the present invention.

5 is a schematic cross-sectional view of AA' after thermal oxidation of a silicon substrate with grooves to form a layer of silicon dioxide in the process of chip processing of the present invention.

6 is a schematic cross-sectional view of AA' after bonding one side of the silicon thin film of the first SOI substrate (A) to the silicon substrate with grooves during the chip processing of the present invention.

Fig. 7 is a schematic cross-sectional view of AA' after removing the substrate silicon of the original SOI substrate (A) in the structure during the chip processing of the present invention.

FIG. 8 is a schematic cross-sectional view of AA′ after the oxide layer above the lower plate in the structure is etched to form a cavity structure in the process of chip processing of the present invention.

FIG. 9 is a schematic cross-sectional view of AA′ after depositing a silicon nitride dielectric layer in the chip processing process of the present invention.

Fig. 10(a) is a schematic cross-sectional view of AA' after etching the silicon nitride dielectric layer and the through hole of the lower electrode plate during the chip processing of the present invention; Fig. 10(b) is the etching of the silicon nitride dielectric during the chip processing of the present invention. Top view of the layer and lower plate after the through holes.

11 is a schematic cross-sectional view of the second SOI substrate (B) used in the chip processing process of the present invention.

12 is a schematic cross-sectional view of AA' after the silicon film side of the second SOI substrate (B) is bonded to the substrate silicon during the chip processing process of the present invention.

13 is a schematic cross-sectional view of AA' after removing the substrate silicon and oxide layer of the original SOI substrate (B) in the structure in the process of chip processing of the present invention.

14 is a schematic cross-sectional view of AA′ after a layer of metal gold (Au) is sputtered on the structure during the chip processing of the present invention.

15 is a schematic cross-sectional view of AA′ after etching the metal gold and single crystal silicon layer above the silicon wafer to form the upper electrode plate during the chip processing process of the present invention.

16 is a schematic cross-sectional view of AA′ after etching the silicon oxide and single crystal silicon layer above the silicon wafer to form the lower electrode plate during the chip processing process of the present invention.

Fig. 17 is a schematic cross-sectional view of AA' after depositing a layer of silicon dioxide as an insulating passivation layer in the chip processing process of the present invention.

FIG. 18 is a schematic cross-sectional view of AA′ after the electrode contact holes are etched in the chip processing process of the present invention.

19 is a schematic cross-sectional view of AA' after sputtering a layer of metal gold and etching the gold leads during the chip processing of the present invention.

FIG. 20 is an output characteristic curve of an acceleration-sensitive chip with a designed range of 30,000 g in the embodiment.

Description of reference numbers:

1. Silicon substrate, 2. Lower plate, 3. Dielectric layer, 4. Upper plate, 5. Cavity, 6. Gold, 7. Through hole.

The four squares in the lower part of the figure mark the materials represented by the different color patterns.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings:

The present invention provides a linked contact capacitive acceleration sensitive chip and a manufacturing method thereof, which refers to the manufacturing method of the acceleration sensitive chip or the similar sensitive chip shown in the accompanying drawings of the present invention. It is characterized in that: the chip includes a monocrystalline silicon substrate 1 etched with grooves, a lower electrode plate 2 located on the substrate 1, a dielectric layer 3 on the lower electrode plate 2, an upper electrode plate 4, and an upper electrode plate. 4. The sealed cavity 5 formed with the groove of the substrate, and the metal layer 6 on the upper plate; the upper and lower plates are connected to the external circuit through pressure welding points to form an acceleration detection circuit, and the acceleration signal is converted into a capacitance signal for output .

The upper plate 4 and the groove of the substrate constitute a sealed cavity 5, and the lower plate 2 is located between the upper plate 4 and the groove on the substrate 1, and is suspended relative to the silicon substrate 1, and its suspended height is determined by the substrate. The etch depth of the upper groove is determined.

There is an air pressure difference between the inside of the sealed cavity 5 and the outside world. When the sensitive chip is not subjected to acceleration, the upper plate 4 and the dielectric layer 3 on the lower plate 2 are already in a certain degree of contact. The contact area between the two pole plates changes, and the lower pole plate 2 deforms with the deformation of the upper pole plate 4, and the two form a linkage effect. Within the range, the upper pole plate 4 and the dielectric layer 3 on the lower pole plate 2 Always in touch.

The lower plate 2 is made of the silicon film on the first SOI substrate (A), and the silicon film side of the first SOI substrate (A) is etched with the grooved substrate silicon through the silicon-silicon direct bonding technology. The sheets 1 are bonded together, and the silicon substrate and the oxide layer of the original SOI substrate (A) are removed to realize the fabrication of the lower plate 2 .

The upper plate 4 is made of the silicon film on the second SOI substrate (B), and the side of the silicon film of the second SOI substrate (B) is formed with the suspended lower plate 2 and the engraving through the silicon-silicon direct bonding technology. The substrate silicon wafers 1 etched with the cavity 5 are bonded together, the substrate and oxide layer of the original SOI substrate (B) are removed, and the fabrication of the upper electrode plate 4 and the sealing of the cavity 5 are completed.

When the upper electrode plate 4 is fabricated by using the silicon-silicon direct bonding technology, the air pressure difference between the inside of the sealed cavity 5 and the outside world is set by controlling the air pressure of the bonding chamber of the bonding equipment.

A metal layer 6 is formed on the upper electrode plate 4 .

A dielectric layer 3 is deposited on the lower electrode plate 2 and a through hole 7 is provided.

The design principle of the present invention:

The invention proposes a linked contact capacitive acceleration sensitive structure, which is mainly composed of a silicon substrate, a lower electrode plate, a dielectric layer, an upper electrode plate and a metal layer. In the structure, the upper and lower electrode plates are both movable structures, and the lower electrode plate is arranged on the single crystal silicon substrate with grooves etched in advance, and is suspended and movable relative to the single crystal silicon substrate. The silicon nitride dielectric layer is etched with through holes; a sealed cavity is formed between the upper plate and the groove on the substrate, and there is a pressure difference between the inside of the cavity and the outside world, and a metal layer is made on the upper plate to increase the upper plate The quality of the upper plate makes the deformation of the upper plate more sensitive to the external acceleration; the two plates are connected to the external circuit through the pressure welding point, and the acceleration signal is converted into a capacitance signal for output. This structure realizes the acceleration measurement by changing the mutual contact area of the upper and lower plates. When the acceleration is not applied, the upper plate and the lower plate are already in mutual contact due to the pressure difference between the inside of the sensitive structure cavity and the outside world; When acceleration acts on the sensitive structure, the contact area between the upper and lower plates will change, and the output capacitance is dominated by the contact capacitance between the two plates. During this process, the lower plate also follows the movement of the upper plate. It deforms and acts as an adjustment, forming a linkage effect, so that the contact area changes at a nearly constant rate, so the output capacitance value will have an approximate linear relationship with the acceleration change, and the sensor shows superior linearity and higher output Capacitance value, so as to solve the problems of poor linearity and small capacitance change between the input and output of ordinary capacitive acceleration sensors.

The manufacturing method of the present invention mainly utilizes MEMS technologies such as silicon-silicon direct bonding, dry etching, etc., to make the SOI substrate and the substrate silicon chip into a linkage contact capacitive acceleration sensitive chip. The grooves on the substrate are made by dry etching, and the depth of the grooves is determined by the suspended height of the designed lower plate; the upper and lower plates are both made of SOI substrate silicon film combined with silicon-silicon direct bonding technology , When making the upper plate, control the air pressure of the bonding chamber of the bonding equipment to set the air pressure inside the cavity of the sensitive structure to ensure that there is a pressure difference between the inside of the cavity and the outside world, so that the upper pole of the sensitive chip is not affected by acceleration. The plate is already in a certain degree of contact with the dielectric layer on the lower plate.

Example:

Using the linkage contact capacitive acceleration sensitive structure proposed by the present invention, an acceleration sensitive chip with a design range of 30000g (g=9.8m/s ² ) is designed, and its structural parameters are as follows:

The upper and lower electrode plates are circular in shape, with a radius of 400 μm. The thickness of the upper electrode plate is 5 μm, the thickness of the lower electrode plate is 10 μm, and the suspended height of the lower electrode plate relative to the silicon substrate is 5 μm. The silicon nitride dielectric The layer thickness is 50 nm, the distance between the upper plate and the dielectric layer is 0.5 μm, the thickness of metal gold (Au) is 5 μm, and the air pressure inside the cavity is 81.5 kPa.

For the acceleration-sensitive chip with the above size parameters, the finite element software is used for simulation analysis, and the output characteristic curve is obtained as shown in Figure 20. In Figure 20, point A is the initial state of the sensitive chip, at this time the upper plate has been in contact with the dielectric layer on the lower plate; when the sensitive chip is subjected to external acceleration, it is within the linear region (point B ~ C point) operation, the output capacitance and acceleration show an excellent linear relationship, the nonlinearity is about 0.87%FS, the capacitance change at full scale is about 3.23pF, reaching 15.4% of the initial capacitance value (21pF), inherent The frequency is about 94264Hz, the overload reaches 36 times the range, and the cross-coupling coefficient is less than 1%.

The manufacturing method of the above-mentioned linked contact capacitive acceleration sensitive chip is as follows:

The first SOI substrate (A) used is shown in Figure 3, and its specifications are as follows:

Top layer silicon film thickness: 10μm, doping type: P type, resistivity: 0.01～0.02Ω·cm; oxide layer thickness: 0.5μm; substrate silicon thickness: 500μm;

The second SOI substrate (B) used is shown in Figure 11, and its specifications are as follows:

Top layer silicon film thickness: 5μm, doping type: P type, resistivity: 0.01～0.02Ω·cm; oxide layer thickness: 0.5μm; substrate silicon thickness: 500μm;

(1) etching the single crystal silicon substrate to form a groove with a depth of 5 μm, as shown in FIG. 4 ;

(2) thermally oxidize the silicon substrate engraved with grooves in FIG. 4 to form a layer of SiO ₂ with a thickness of 1 μm as an insulating layer, as shown in FIG. 5 ;

(3) bonding one side of the silicon film of the first SOI substrate (A) in FIG. 3 to the silicon substrate with grooves in FIG. 5 , as shown in FIG. 6 ;

(4) Remove the substrate silicon of the original SOI substrate (A) in the structure of FIG. 6 , as shown in FIG. 7 ;

(5) Etch the oxide layer above the lower plate in the structure of FIG. 7 to form a cavity structure, as shown in FIG. 8 ;

(6) using low pressure chemical vapor deposition (LPCVD) to deposit a 50nm thick low stress silicon nitride dielectric layer, as shown in Figure 9;

(7) Etch the silicon nitride dielectric layer in the structure of FIG. 9, and etch the lower electrode plate to form through holes, as shown in FIG. 10 (a) and (b);

(8) Set the air pressure of the bonding chamber of the bonding equipment to 81.5kPa, and bond the silicon film side of the second SOI substrate (B) in FIG. 11 to the structure in FIG. 10 , as shown in FIG. 12 ;

(9) Remove the substrate silicon and oxide layer of the original SOI substrate (B) in the structure of FIG. 12, as shown in FIG. 13;

(10) Sputtering a layer of metal gold (Au) with a thickness of 5 μm on the structure shown in FIG. 13 , as shown in FIG. 14 ;

(11) Etch the metal gold and single crystal silicon layer in the structure of FIG. 14, and etch to the surface of the oxide layer below the upper pole plate to form the upper pole plate and the metal layer structure, as shown in FIG. 15;

(12) Etch the silicon oxide and single crystal silicon layer in the structure of FIG. 15, and etch to the silicon oxide surface below the lower electrode plate to form the lower electrode plate, as shown in FIG. 16;

(13) A layer of silicon dioxide with a thickness of 0.5 μm is deposited as an insulating passivation layer in the structure of FIG. 16 , as shown in FIG. 17 ;

(14) The electrode contact holes of the upper and lower electrode plates are etched in the structure of FIG. 17, as shown in FIG. 18;

(15) Sputtering a layer of metal gold with a thickness of 1 μm in the structure of FIG. 18 , and etching the gold leads to form the acceleration-sensitive structure as shown in FIG. 19 .

The linkage contact capacitive acceleration sensitive chip of the invention can be widely used in the measurement of acceleration signals in various fields such as industrial control, automotive electronics, aerospace, national defense and military industries.

Claims (9)

1. A linkage contact capacitive acceleration sensitive chip and a manufacturing method thereof, characterized in that: the chip comprises a monocrystalline silicon substrate (1) etched with a groove, a lower pole plate positioned on the substrate (1) (2), the dielectric layer (3) on the lower electrode plate (2), the upper electrode plate (4), the sealed cavity (5) formed by the upper electrode plate (4) and the groove of the substrate, and the The upper metal layer (6); the upper and lower pole plates are connected to an external circuit through pressure welding points to form an acceleration detection circuit, and the acceleration signal is converted into a capacitance signal for output. 2. A kind of linkage contact capacitive acceleration sensitive chip according to claim 1 and its manufacturing method, it is characterized in that: upper pole plate (4) and substrate groove form sealed cavity (5), lower pole plate ( 2) It is located between the upper plate (4) and the groove on the substrate (1), and is suspended relative to the silicon substrate (1), and its suspended height is determined by the etching depth of the groove on the substrate. 3. A kind of linkage contact capacitive acceleration sensitive chip according to claim 1 and its manufacturing method, it is characterized in that: there is a pressure difference between the inside of the sealed cavity (5) and the outside world, and when the sensitive chip is not subjected to acceleration, The upper electrode plate (4) and the dielectric layer (3) on the lower electrode plate (2) are already in a certain degree of contact state. When subjected to external acceleration, the contact area between the two electrode plates changes, and the lower electrode plate (2) ) is deformed with the deformation of the upper plate (4), and the two form a linkage effect. Within the range, the dielectric layer (3) on the upper plate (4) and the lower plate (2) is always in contact. 4. A kind of linked contact capacitive acceleration sensitive chip and its manufacturing method according to claim 1, it is characterized in that: lower pole plate (2) is made of silicon film on the first SOI substrate (A), through The silicon-silicon direct bonding technology bonds one side of the silicon film of the first SOI substrate (A) with the substrate silicon wafer (1) etched with grooves, and removes the silicon lining of the original SOI substrate (A) The bottom and the oxide layer are used to realize the fabrication of the lower electrode plate (2). 5. A kind of linked contact capacitive acceleration sensitive chip according to claim 1 and its manufacturing method, it is characterized in that: the upper pole plate (4) is made of the silicon film on the second SOI substrate (B), through The silicon-silicon direct bonding technology bonds one side of the silicon thin film of the second SOI substrate (B) with the silicon substrate (1) on which the suspended lower plate (2) is formed and the cavity (5) is etched together. , removing the substrate and oxide layer of the original SOI substrate (B), and completing the fabrication of the upper electrode plate (4) and the sealing of the cavity (5). 6. A linkage contact capacitive acceleration sensitive chip according to claim 1 and a manufacturing method thereof, characterized in that: when using silicon-silicon direct bonding technology to make the upper plate (4), the bonding is performed by controlling the bonding equipment. The air pressure of the chamber is used to set the air pressure difference between the inside of the sealed chamber (5) and the outside. 7 . The linked contact capacitive acceleration sensitive chip and its manufacturing method according to claim 1 , wherein a metal layer ( 6 ) is fabricated on the upper plate ( 4 ). 8 . 8. A linkage contact capacitive acceleration sensitive chip and its manufacturing method according to claim 1, characterized in that: a dielectric layer (3) is deposited on the lower plate (2), and a through hole (7) is provided. ). 9. A kind of linkage contact capacitive acceleration sensitive chip according to claim 1 and its manufacture method, and its main process steps are as follows: (1) etching a single crystal silicon substrate to form a groove, as shown in Figure 4; (2) thermally oxidize a layer of silicon dioxide on the monocrystalline silicon substrate engraved with grooves in FIG. 4 as an insulating layer, as shown in FIG. 5 ; (3) bonding one side of the silicon film of the first SOI substrate (A) in FIG. 3 to the silicon substrate with grooves in FIG. 5 , as shown in FIG. 6 ; (4) Remove the substrate silicon of the original SOI substrate (A) in the structure of FIG. 6 , as shown in FIG. 7 ; (5) Etch the oxide layer above the lower plate in the structure of FIG. 7 to form a cavity structure, as shown in FIG. 8 ; (6) deposit a layer of silicon nitride as a dielectric layer in the structure of FIG. 8, as shown in FIG. 9; (7) Etch the silicon nitride dielectric layer in the structure of FIG. 9, and etch the lower electrode plate to form through holes, as shown in FIG. 10(a) and (b); (8) bonding one side of the silicon film of the second SOI substrate (B) in FIG. 11 to the structure in FIG. 10 , as shown in FIG. 12 ; (9) Remove the substrate silicon and oxide layer of the original SOI substrate (B) in the structure of FIG. 12, as shown in FIG. 13; (10) Sputtering a layer of metal gold (Au) on the structure shown in FIG. 13 , as shown in FIG. 14 ; (11) Etch the metal gold and single crystal silicon layer in the structure of FIG. 14, and etch to the surface of the oxide layer below the upper pole plate to form the upper pole plate and the metal layer structure, as shown in FIG. 15; (12) Etch the silicon oxide and single crystal silicon layer in the structure of FIG. 15, and etch to the silicon oxide surface below the lower electrode plate to form the lower electrode plate, as shown in FIG. 16; (13) deposit a layer of silicon dioxide as the insulating passivation layer in the structure of FIG. 16, as shown in FIG. 17; (14) The electrode contact holes of the upper and lower electrode plates are etched in the structure of FIG. 17, as shown in FIG. 18; (15) A layer of metal gold is sputtered in the structure of FIG. 18 , and gold leads are etched to form the acceleration-sensitive structure as shown in FIG. 19 .

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