CN102841878B - Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) - Google Patents
Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) Download PDFInfo
- Publication number
- CN102841878B CN102841878B CN201210283567.5A CN201210283567A CN102841878B CN 102841878 B CN102841878 B CN 102841878B CN 201210283567 A CN201210283567 A CN 201210283567A CN 102841878 B CN102841878 B CN 102841878B
- Authority
- CN
- China
- Prior art keywords
- register
- control
- isa
- cpu
- port ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000001133 acceleration Effects 0.000 title abstract 2
- 230000003993 interaction Effects 0.000 claims abstract description 5
- 230000009977 dual effect Effects 0.000 claims description 38
- 238000005070 sampling Methods 0.000 claims description 19
- 230000007704 transition Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 230000002457 bidirectional effect Effects 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 5
- 241001269238 Data Species 0.000 claims description 4
- 230000006870 function Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
Abstract
The invention relates to an internet security and acceleration (ISA) interface internet protocol (IP) core based on a processor local bus (PLB), and the ISA interface IP core is characterized by comprising a decoder, a double-port random access memory (RAM), a register array, a read-write state machine and a user logic module; the decoder is connected with the user logic module through a control wire, and the decoder is connected with the double-port RAM and the register array through an address line; the input end of the read-write state machine is connected with an ISA bus, and the output end of the read-write state machine is connected with the double-port RAM; one end of the register array is connected with the ISA bus, the other end of the double-port RAM and the other end of the register array are respectively connected with the user logic module through a two-directional data line, the other end of the user logic module is connected with the PLB, the ISA bus is connected with a principal computer control unit, and the PLB bus is connected with a central processing unit (CPU). The ISA bus is connected with the principal computer control unit, and the PLB bus is connected with the CPU, so that a data interaction function is realized, and the ISA interface IP core has characteristics of simpleness in control logic, high reliability, rapid speed, strong compatibility, easiness in expansion and the like.
Description
Technical field
The invention belongs to mobile robot field, especially a kind of ISA Interface IP Core based on PLB bus.
Background technology
In mobile robot field, PC104 is usually used to control motor or sensor.Due to the design feature of PC104 self, it directly can not control motor, and therefore, the information interaction between PC104 and motor needs an intermediate link, Here it is interface board.At present, usual use microcontroller (MCU) module is as interface board, that is: the control mode of PC104+ microcontroller+motor (or sensor), this control mode Problems existing is: 1, the programming language of MCU is mainly C language, realize with soft logic, it performs instruction by order and realizes specific function, keeps away the shortcoming that unavoidable speed is low; 2, the feature that MCU can only process an instruction at one time also have impact on its application, and it can only be used for the design of some algorithms and simply control.In sum, adopt PC104+ microcontroller+motor (or sensor) control mode complex logic controls, parallel high-speed, interface board can again use and scalable in, implement all very difficult.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of reasonable in design, steering logic is simple, speed is fast and the maintainable good ISA Interface IP Core based on PLB bus.
The present invention solves its technical matters and takes following technical scheme to realize:
Based on an ISA Interface IP Core for PLB bus, comprise code translator, dual port RAM, register array, read-write state machine and user logic module; Code translator is connected with user logic module by control line, and code translator is connected with register array with dual port RAM by address wire; The input end of read-write state machine is connected with isa bus, and read-write state machine output terminal is connected with dual port RAM; Register array one end is connected with isa bus, dual port RAM is connected with user logic module respectively by bidirectional data line with the other end of register array, the other end of user logic module is connected with PLB bus, described isa bus is connected with PC control unit, and PLB bus is connected with CPU, realize the data interaction between PC control unit and CPU.
And described code translator, dual port RAM, register array, read-write state machine, user logic module and logic judgment module are inlaid in FPGA.
And, a logic judgment module is also comprised in FPGA, the input end of this logic judgment module is connected with the high-order enable signal SBHE of the system byte of isa bus, the output terminal of logic judgment module is connected with 16 of isa bus chip selection signal IOCS16, and the switching for the process of isa bus 16 bit data controls.
And the signal that described read-write state machine is connected with isa bus is IO read-write, DMA control signal and clock signal.
And described dual port RAM stores following register data: 8 motor data, 4 scrambler controling parameters, 2 sensor controling parameters, 8 motor status data, 4 encoder data and 2 sensing datas.
And described register array stores and controls related register; Described control related register comprises following register: start actuating motor command port register, complete Electric Machine Control flag register, interrupt control register and external sensor control port register.
And the two-way look-at-me between PC control unit and PLB core supported by described interrupt control register.
And, described user logic module comprises two logical transition interfaces, a logical transition interface is used for conversion and the transmission of the data register between dual port RAM and CPU, and another logical transition interface is used for conversion and the transmission of the control related register between register array and CPU.
And described PC control unit is PC104 mainboard, CPU is the CPU based on the soft core of MicroBlaze.
And described dual port RAM is that asynchronous clock stores.
Advantage of the present invention and good effect are:
1, this ISA Interface IP Core is effectively by code translator, read-write state machine, dual port RAM, register array and user logic module etc. integrate, be connected with PC control unit PC104 by isa bus on the one hand, be connected with CPU by PLB bus on the other hand, can shift between various technique and structure easily, can to function in addition cutting to meet specific application, it is variable that configurable I P parameter comprises code translator address realm, interruptable controller purposes is variable, register number is variable, enable or disable function block is variable, achieve and can use again, retargetable and configurable functionality.
2, this ISA Interface IP Core to be embedded in FPGA and to be connected by the soft nuclear phase that PLB bus and the soft core of MicroBlaze or other meet PLB specification, have travelling speed fast, take the advantages such as resource is few, configurability is strong, can interrupt from dynamic response software and hardware, carry out abnormality processing, by additional steering logic, external interrupt can be expanded; PC control unit can also be assisted to complete computer peripheral equipment running status real-time collecting, memory read/write task, alleviate operation burden and the resource consumption of PC control unit, improve system performance.
3, this ISA Interface IP Core provides ISA interface and is connected with host computer PC 104 mainboard, it is advantageous that: PC104 have small size, high reliability, module can spread, low-power consumption, stacking-type connect (PC104 system have employed the form that multiple functional module plate carries out mutual storehouse in form, and it is very little to take up room, and power consumption is also much lower than conventional P C.The form of storehouse brings the convenience of system upgrade and the reliability of system height.), the feature such as the construction cycle is short.
4, isa bus have that reliability is high, availability and the feature such as compatible strong, simultaneously because isa bus is faster than the much peripherals etc. be attached thereto, therefore, its circuit structure is simple, be convenient to realize.
Accompanying drawing explanation
Fig. 1 is circuit block diagram of the present invention and application connection diagram thereof;
Fig. 2 is the processing flow chart of the PC104 pick-up transducers data be connected with the present invention;
Fig. 3 is the processing flow chart that the PC104 be connected with the present invention controls motor;
Fig. 4 is the CPU processing flow chart be connected with the present invention.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of the present invention is further described:
Based on an ISA Interface IP Core for PLB bus, as shown in Figure 1, code translator, dual port RAM, register array, read-write state machine, logic judgment module and user logic module is comprised; Code translator is connected with user logic module by control line, and code translator is connected with register array with dual port RAM by address wire; One end of user logic module is connected with PLB bus, and the other end of user logic module is connected with register array with dual port RAM respectively by bidirectional data line; The input end of read-write state machine is connected with the IO read-write (IOR, IOW signal) of isa bus, DMA control signal (AEN signal), clock signal (CLK signal), and the control signal (WEA signal) that read-write state machine exports is connected with dual port RAM; The input end of logic judgment module is connected with the high-order enable signal SBHE of the system byte of isa bus, the output terminal of logic judgment module is connected with 16 of isa bus chip selection signal IOCS16, namely as isa bus enable signal SBHE high-order to logic judgment module system byte, logic judgment module exports 16 chip selection signal IOCS16 to isa bus, and the switching for the process of isa bus 16 bit data controls; Register array one end is connected with isa bus, and the other end is connected with user logic module by bidirectional data line.ISA Interface IP Core is embedded in FPGA, the side of ISA Interface IP Core provides ISA interface to be connected with PC control unit (PC104), opposite side is connected with the CPU in FPGA by PLB bus, thus realizes the data interaction function between PC control unit (PC104) and CPU.Below modules is described respectively.
Dual port RAM and register array together form the register included by this ISA Interface IP Core, as shown in the table:
1 to 6 is stored in dual port RAM as data register, and this dual port RAM can store 256 byte datas and be asynchronous clock storage; These data registers comprise: 8 motor data, 4 scrambler controling parameters, 2 sensor controling parameters, 8 motor status data, 4 encoder data, 2 sensing datas.
7th is 4 and controls related register and be stored in register array.Control related register and can need self-defining according to user, in the present embodiment, define following four control registers: 1, start actuating motor command port register (only writing): write by PC104, after PC104 writes this order, a look-at-me will be sent to CPU; 2, complete Electric Machine Control flag register (read-only): write by CPU, after completing Electric Machine Control, CPU writes this register; 3, interrupt control register (read-write): read interrupt control register after PC104 receives IRQ, process according to different zone bits, CPU reads interrupt control register, processing motor and sensor after producing and interrupting; 4, external sensor control port register.
In register array, interrupt control register and uses thereof can by User Defined with quantity, in the present embodiment, interrupt control register is for transmitting the two-way look-at-me between PC control unit PC104 and CPU, one end of interrupt control register is from the interrupt request control line IRQ of isa bus, and one end to be connected with user logic module by bidirectional data line and by user logic model calling on CPU in addition.Such as, when PC104 initiates the interrupt request of write sampling interval to CPU, interruptable controller control word is set to 1 by PC104, fill order after CPU receives PC104 interrupt request, by the data copy that returns in dual port RAM, write interrupt control register settling signal simultaneously, CPU also initiates the interrupt request of data acquisition to PC104 immediately, and interruptable controller control word is set to 1, after PC104 receives interrupt request, read IO address and obtain sampled data, and remove the interruption status of interrupt control register.
The decoding range of code translator is: be more than or equal to 600H and be less than 710H.Code translator is connected with user logic module by control line, output for controlling user logic module according to address realm exports trend, code translator is connected with register array with dual port RAM by address wire, for realizing the switching control function of dual port RAM and register array.The mode of operation of this code translator access dual port RAM or register array is: as SA>=700H, ISA_INF_CTRL line is effective, now, the data that isa bus writes by user logic module export to register array, and the data of reading are taken out and are placed on isa bus from register array; As SA>=600H and <=6FFH time, ISA_INF_CTRL line is invalid, now, the data that isa bus writes by user logic module export to dual port RAM, and the data of reading are taken out and are placed on isa bus from dual port RAM.
User logic inside modules arranges two logical transition interfaces, a logical transition interface is used for conversion and the transmission of the data register between dual port RAM and CPU, and another logical transition interface is used for conversion and the transmission of the control related register between register array and CPU.
The present invention can with PC104 PC control unit, linking together based on the CPU of the soft core of MicroBlaze realizes collecting sensor signal to mobile robot and Electric Machine Control function by cooperation control, as shown in Figure 1.The relevant treatment flow process of various piece is as follows:
As shown in Figure 2, the treatment scheme of PC104 pick-up transducers data is: PC104 starts the order of sampling to the write of IO address, and initiates to interrupt to CPU by the interrupt control register of register array, and control word is set to 1, CPU receive interruption signal, performs PC104 order; After sampling completes, to the interrupt control register write sampling completion status data in register array, and send look-at-me to PC104, PC104 receives signal, from dual port RAM, read sampled data.
As shown in Figure 3, the treatment scheme that PC104 controls motor is: PC104 controls order and the data of motor to the write of IO address, and initiate to interrupt to CPU by the interrupt control register of register array, control word is set to 1, CPU receive interruption signal, perform PC104 order, after sampling completes, the status data of Electric Machine Control has been write to dual port RAM, and initiate to interrupt to PC104 by the interrupt control register of register array, control word is set to 1, PC104 and receives signal, from twoport, read the data of Electric Machine Control.
As shown in Figure 4, the treatment scheme of CPU is: CPU waits for that PC104 sends the look-at-me of starting outfit operation, after receiving look-at-me, from the external sensor control interface register read starting outfit information of register array, judgement is that gyroscope starts sampling, accelerometer starts sampling, scrambler starts sampling, perform relevant device and start sample command, by the data write dual port RAM after sampling, and write sampling settling signal to the control register of register array.
It is emphasized that; embodiment of the present invention is illustrative; instead of it is determinate; therefore the present invention is not limited to the embodiment described in embodiment; every other embodiments drawn by those skilled in the art's technical scheme according to the present invention, belong to the scope of protection of the invention equally.
Claims (5)
1. based on an ISA Interface IP Core for PLB bus, it is characterized in that: comprise code translator, dual port RAM, register array, read-write state machine, logic judgment module and user logic module; Described code translator, dual port RAM, register array, read-write state machine, logic judgment module and user logic module are inlaid in FPGA; Code translator is connected with user logic module by control line, and code translator is connected with register array with dual port RAM by address wire; The input end of read-write state machine is connected with isa bus, and read-write state machine output terminal is connected with dual port RAM; Register array one end is connected with isa bus, dual port RAM is connected with user logic module respectively by bidirectional data line with the other end of register array, the other end of user logic module is connected with PLB bus, described isa bus is connected with PC control unit, and PLB bus is connected with CPU, realize the data interaction function between PC control unit and CPU; Described CPU is the CPU based on the soft core of MicroBlaze being arranged on FPGA inside;
Described PC control unit starts the order of sampling to the write of ISA address, and initiates to interrupt to CPU by the interrupt control register of register array, control word is set to 1, CPU receive interruption signal, performs PC control cell command; After sampling completes, to the interrupt control register write sampling completion status data in register array, and send look-at-me to host computer control module, PC control unit receives signal, from dual port RAM, read sampled data;
PC control unit controls order and the data of motor to the write of ISA address, and initiate to interrupt to CPU by the interrupt control register of register array, control word is set to 1, CPU receive interruption signal, perform PC control cell command, after sampling completes, the status data of Electric Machine Control has been write to dual port RAM, and initiate to interrupt to host computer control module by the interrupt control register of register array, control word is set to 1, PC control unit receives signal, has read the data of Electric Machine Control from dual port RAM;
CPU waits for that PC control unit sends the look-at-me of starting outfit operation, after receiving look-at-me, from the external sensor control port register read starting outfit information of register array, judgement is that gyroscope starts sampling, accelerometer starts sampling, scrambler starts sampling, perform relevant device and start sample command, by in the data write dual port RAM after sampling, and to the interrupt control register write sampling settling signal in register array;
Described register array stores and controls related register; Described control related register comprises following register: start actuating motor command port register, complete Electric Machine Control flag register, interrupt control register and external sensor control port register; The two-way look-at-me between PC control unit and CPU supported by described interrupt control register;
Described user logic module comprises two logical transition interfaces, and a logical transition interface is used for the data conversion between dual port RAM and CPU and transmits, and another logical transition interface is used for conversion and the transmission of the control signal between register array and CPU.
2. the ISA Interface IP Core based on PLB bus according to claim 1, it is characterized in that: the input end of the logic judgment module in described FPGA is connected with the high-order enable signal SBHE of the system byte of isa bus, the output terminal of logic judgment module is connected with 16 of isa bus chip selection signal IOCS16, and the switching for the process of isa bus 16 bit data controls.
3. the ISA Interface IP Core based on PLB bus according to claim 1 and 2, is characterized in that: the signal that described read-write state machine is connected with isa bus is IO read-write, DMA control signal and clock signal.
4. the ISA Interface IP Core based on PLB bus according to claim 1 and 2, is characterized in that: described dual port RAM stores following register data: 8 motor data, 4 scrambler controling parameters, 2 sensor controling parameters, 8 motor status data, 4 encoder data and 2 sensing datas.
5. the ISA Interface IP Core based on PLB bus according to claim 1 and 2, is characterized in that: described dual port RAM is that asynchronous clock stores.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210283567.5A CN102841878B (en) | 2012-08-10 | 2012-08-10 | Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210283567.5A CN102841878B (en) | 2012-08-10 | 2012-08-10 | Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102841878A CN102841878A (en) | 2012-12-26 |
| CN102841878B true CN102841878B (en) | 2015-03-11 |
Family
ID=47369254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210283567.5A Expired - Fee Related CN102841878B (en) | 2012-08-10 | 2012-08-10 | Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102841878B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103218325B (en) * | 2013-01-14 | 2016-03-16 | 无锡普智联科高新技术有限公司 | Based on SJA1000 Interface IP Core and the control method thereof of PLB bus |
| CN111988417B (en) * | 2020-08-28 | 2022-07-19 | 电子科技大学 | Communication control method of IoT terminal |
| CN112433966B (en) * | 2020-11-15 | 2023-02-10 | 中国航空工业集团公司洛阳电光设备研究所 | Multi-interface architecture based on Windows platform and implementation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0772107A2 (en) * | 1995-10-10 | 1997-05-07 | The Foxboro Company | Distributed control system including a compact easily-extensible and serviceable field controller |
| CN102169462A (en) * | 2011-04-27 | 2011-08-31 | 中国科学院光电技术研究所 | Data recording method and recording controller based on NAND Flash |
| CN202735722U (en) * | 2012-08-10 | 2013-02-13 | 无锡普智联科高新技术有限公司 | ISA interface IP core of novel PLB bus |
-
2012
- 2012-08-10 CN CN201210283567.5A patent/CN102841878B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0772107A2 (en) * | 1995-10-10 | 1997-05-07 | The Foxboro Company | Distributed control system including a compact easily-extensible and serviceable field controller |
| CN102169462A (en) * | 2011-04-27 | 2011-08-31 | 中国科学院光电技术研究所 | Data recording method and recording controller based on NAND Flash |
| CN202735722U (en) * | 2012-08-10 | 2013-02-13 | 无锡普智联科高新技术有限公司 | ISA interface IP core of novel PLB bus |
Non-Patent Citations (1)
| Title |
|---|
| 基于DSP和FPGA的机器人运动控制系统的研究;刘永锋;《南京理工大学硕士学位论文》;20070601;第9页、第22至55页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102841878A (en) | 2012-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202167015U (en) | Serial interface conversion circuit | |
| CN109412914A (en) | Flow data and AXI interface communication equipment | |
| CN203812236U (en) | Data exchange system based on processor and field programmable gate array | |
| CN102567280A (en) | A Design Method of Computer Hardware Platform Based on DSP and FPGA | |
| CN102841878B (en) | Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB) | |
| CN111736115A (en) | High-speed transmission method of MIMO millimeter-wave radar based on improved SGDMA+PCIE | |
| CN107908587A (en) | Real-time data acquisition transmitting device based on USB3.0 | |
| CN201438269U (en) | Motion control main board, motion control board and motion controller | |
| CN202362460U (en) | Intermediate frequency data acquisition and playback device of GNSS receiver | |
| CN202735722U (en) | ISA interface IP core of novel PLB bus | |
| CN105550133A (en) | AXIS-FIFO bridge circuit based on ZYNQ and data transmission method using same | |
| CN201936294U (en) | Caching system for high-speed image acquisition system | |
| CN111444131B (en) | Data acquisition and transmission device based on USB3.0 | |
| CN102622319A (en) | Data exchange system of high-speed storage interface IP (Internet Protocol) core based on MPMC (Multi-Port Memory Controller) | |
| CN202422113U (en) | Switching system for realizing industry standard architecture (ISA) bus on performance optimization with enhanced RISC-performance computing (PowerPC) embedded computer | |
| CN203084719U (en) | SJA1000 interface IP core based on processor local bus (PLB) | |
| CN103218325B (en) | Based on SJA1000 Interface IP Core and the control method thereof of PLB bus | |
| CN102855210B (en) | Method for realizing intercommunication and data sharing between two single-chip microcomputers | |
| CN105955205A (en) | Motion simulator embedded real-time control system | |
| CN111913899A (en) | UART (universal asynchronous receiver/transmitter) expansion method based on FSMC (frequency selective multi-media card) and FPGA (field programmable gate array) | |
| CN203164668U (en) | Miniature programmable logic controller | |
| CN105740179A (en) | Parallel data acquisition system | |
| CN2763043Y (en) | Pneumatic marking device | |
| CN201397487Y (en) | Embedded network computer terminal unit | |
| CN116186793B (en) | RISC-V based security chip architecture and working method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180813 Address after: 518000 room 503, block A, sang Tai Building, Xili University, Xili street, Shenzhen, Guangdong, Nanshan District Patentee after: SHENZHEN PUZHI LIANKE ROBOT TECHNOLOGY Co.,Ltd. Address before: 214135 floor 4, block A, whale block, Wuxi (National) software park, 18, Zhen Ze Road, Wuxi New District, Jiangsu. Patentee before: WUXI PUZHI LIANKE HIGH-TECH Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150311 |