CN102800586B - Design process for chip-type power diode - Google Patents

Abstract

The invention discloses a design process for a chip-type power diode, belonging to a design process for a semiconductor. The design process for the chip-type power diode comprises the following steps of: design for a rated current, design for a rated reverse repetition voltage, design for a chip size, design for a layout, design for diffusion conditions, and product evaluation; and a micro-table GPP (glass passivation parts) glass passivation process is adopted for the chip-type diode. The micro-table GPP glass passivation process is adopted; the working junction temperature in the chip design is 150 DEG C, which can completely meet applications in the field of green illumination; and chip size can be reduced to 32 mil from 0.3 A specification, so that the application requirements of the present green illumination of lower than 20 W can be widely met.

Description

A Chip Power Diode Design Process

technical field

The invention relates to a semiconductor design process, in particular to a chip power diode design process.

Background technique

Power diodes mainly include Schottky diodes, fast recovery diodes and power frequency diodes. As electronic products become thinner and smaller, power diodes, which are basic components, have also started a trend of miniaturization, integration, and high frequency. At present, most of the integrated electronic ballasts for green lighting use plug-in power diodes with a specification of 1A. This is the smallest shape of plug-in power diodes that can meet the specification of 1A at this stage, and is widely used by green lighting manufacturers. With the in-depth development of the miniaturization of green lighting electronic products, the market's requirements for power diodes are constantly increasing, and products designed by traditional processes can no longer meet the needs of technology improvement and product upgrading.

In the field of green lighting, plug-in power diodes with specifications of 1A and 1000V are the most widely used products at present, and the chip passivation mainly adopts silicon rubber technology. Due to the limitations of the silicone rubber passivation process, its designed operating junction temperature is less than 125°C, and its chips are in a critical and over-limit working state in the high-temperature environment of the integrated electronic ballast, which brings stability and safety to the product. Hidden danger.

In view of this, the inventor of the present invention conducted research on this, and specially developed a chip power diode design process, from which this case arose.

Contents of the invention

The purpose of the present invention is to provide a chip power diode design process with high working junction temperature and small appearance size.

In order to achieve the above object, the solution of the present invention is:

A chip power diode design process includes rated current design, rated reverse repetitive voltage design, chip size design, layout design, diffusion condition design and product evaluation. The chip diode adopts a micro-mesa GPP glass passivation process.

The rated current of the chip power diode is 0.3A-0.7A.

The rated reverse repetition voltage of the chip power diode is 600V-1000V.

The chip size of the chip power diode is 32mil-45mil.

The size of the chip active area of a chip power diode with a rated current of 0.3A is 21mil. In order to form an effective protection ring, the size of the nickel-plated area on the secondary photolithography table is 18mil*18mil, and the width of the photolithography lines is selected to be 2, 3, 4, 5mil.

Diffusion condition design: In order to ensure sufficient mesa size of the chip power diode, the etching depth should not be too deep to reduce lateral corrosion. The depth is composed of two parts: the PN junction depth and the space expansion area, where the width of the space expansion area is determined by the avalanche breakdown voltage and is a constant value. Therefore, in order to reduce the etching depth, the only way to reduce the depth of the PN junction is to reduce the boron diffusion time. Since the phosphorus junction depth is mainly promoted by boron expansion, when the boron expansion time is reduced, it is necessary to increase the phosphorus expansion time to increase the phosphorus junction and reduce VF.

Product evaluation: Evaluate the chip using thermal resistance characteristic testing technology.

Using the micro-mesa GPP glass passivation process, the chip is designed to work at a junction temperature of 150°C. This junction temperature can fully meet the application in the field of green lighting. The chip size of 0.3A can be reduced to 32mil, which can be widely used under 20W. Application requirements of green lighting.

The present invention will be further described in detail below in conjunction with specific embodiments.

Detailed ways

Example 1

A chip power diode design process includes rated current design, rated reverse repetitive voltage design, chip size design, layout design, diffusion condition design and product evaluation. The chip diode adopts a micro-mesa GPP glass passivation process.

The rated current of the chip power diode is 0.3A, and the chip size is 32mil.

The rated reverse repetition voltage of the chip power diode is 600V.

The size of the chip active area of the above-mentioned chip power diode is 21mil. In order to form an effective protection ring, the size of the nickel-plated area on the secondary photolithography table is 18mil*18mil, and the width of the photolithography lines is selected to be 2, 3, 4, and 5mil respectively. .

Diffusion condition design: In order to ensure sufficient mesa size of the chip power diode, the etching depth should not be too deep to reduce lateral corrosion. The depth is composed of two parts: the PN junction depth and the space expansion area, where the width of the space expansion area is determined by the avalanche breakdown voltage and is a constant value. Therefore, in order to reduce the etching depth, the only way to reduce the depth of the PN junction is to reduce the boron diffusion time. Since the phosphorus junction depth is mainly promoted by boron expansion, when the boron expansion time is reduced, it is necessary to increase the phosphorus expansion time to increase the phosphorus junction and reduce VF.

Product evaluation: Evaluate the chip using thermal resistance characteristic testing technology.

(1) Evaluation of thermal resistance characteristics

The chip power diode packaged in a 32mil chip is tested for thermal characteristics. At a maximum junction temperature of 150°C, the relationship between the chip’s allowable ambient temperature TA, the junction-to-ambient thermal resistance RJA, and the rated current IF(AV) is shown in the table below :

The following conclusions can be drawn from the table:

Under the same RJA, TA decreases with the increase of IF(AV); under the same IF(AV), TA decreases with the increase of RJA. The above data shows that when the rated current IF(AV)=0.3A, TA is above 90°C, but when IF(AV)=0.4A, TA is below 90°C, therefore, the design of IF(AV)=0.3A It works.

(2) Reliability assessment:

According to the reliability test results, the two indicators of forward surge current and HTRB have met the requirements, and the reliability of the device meets the design and application requirements.

Using the micro-mesa GPP glass passivation process, the chip is designed to work at a junction temperature of 150°C. This junction temperature can fully meet the application in the field of green lighting. The chip size of 0.3A can be reduced to 32mil, which can be widely used under 20W. Application requirements of green lighting.

Example 2

A chip power diode design process includes rated current design, rated reverse repetitive voltage design, chip size design, layout design, diffusion condition design and product evaluation. The chip diode adopts a micro-mesa GPP glass passivation process.

The rated current of the chip power diode is 0.5A, and the chip size is 42mil.

The rated reverse repetition voltage of the chip power diode is 800V.

Diffusion condition design: In order to ensure sufficient mesa size of the chip power diode, the etching depth should not be too deep to reduce lateral corrosion. The depth is composed of two parts: the PN junction depth and the space expansion area, where the width of the space expansion area is determined by the avalanche breakdown voltage and is a constant value. Therefore, in order to reduce the etching depth, the only way to reduce the depth of the PN junction is to reduce the boron diffusion time. Since the phosphorus junction depth is mainly promoted by boron expansion, when the boron expansion time is reduced, it is necessary to increase the phosphorus expansion time to increase the phosphorus junction and reduce VF.

Product evaluation: Evaluate the chip using thermal resistance characteristic testing technology.

Using the micro-mesa GPP glass passivation process, the chip is designed to work at a junction temperature of 150°C. This junction temperature can fully meet the application in the field of green lighting. The chip size of 0.5A can be reduced to 42mil, which can widely meet the current requirements below 20W. Application requirements of green lighting.

Example 3

A chip power diode design process includes rated current design, rated reverse repetitive voltage design, chip size design, layout design, diffusion condition design and product evaluation. The chip diode adopts a micro-mesa GPP glass passivation process.

The rated current of the chip power diode is 0.7A, and the chip size is 45mil.

The rated reverse repetition voltage of the chip power diode is 1000V.

Diffusion condition design: In order to ensure sufficient mesa size of the chip power diode, the etching depth should not be too deep to reduce lateral corrosion. The depth is composed of two parts: the PN junction depth and the space expansion area, where the width of the space expansion area is determined by the avalanche breakdown voltage and is a constant value. Therefore, in order to reduce the etching depth, the only way to reduce the depth of the PN junction is to reduce the boron diffusion time. Since the phosphorus junction depth is mainly promoted by boron expansion, when the boron expansion time is reduced, it is necessary to increase the phosphorus expansion time to increase the phosphorus junction and reduce VF.

Product evaluation: Evaluate the chip using thermal resistance characteristic testing technology.

Using the micro-mesa GPP glass passivation process, the chip is designed to work at a junction temperature of 150°C, which can fully meet the application in the field of green lighting. The chip size of 0.7A specification can be reduced to 45mil, which can widely meet the current requirements below 20W. Application requirements of green lighting.

The above-mentioned embodiments and drawings do not limit the form and style of the product of the present invention, and any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of the present invention.

Claims (1)

1. a slice power diode design technique, it is characterized in that: comprise rated current design, specified inverted repeat voltage design, chip size design, layout design, diffusion conditions design and Product evaluation, described sheet type diode adopts miniature table top GPP glass passivation process, wherein, the rated current of described slice power diode is 0.3A-0.7A;

The specified inverted repeat voltage of described slice power diode is 600V-1000V;

The chip size of described slice power diode is 32mil-45mil;

Rated current is that the chip active district of the slice power diode of 0.3A is of a size of 21mil, and for secondary photoetching table top nickel plating, district is of a size of 18mil*18mil, choose photoetching line thickness be respectively 2,3,4,5mil;

Product evaluation adopts heat resistance characteristic measuring technology to assess chip.